PLX Technology PEX 8618, Quick Start Manual

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Another mechanism that can increase jitter seen by a Receiver in common clocked systems is the fixed phase
difference (transport delay delta) between Transmitter data at the CDR input and a Receiver’s recovered clock,
relative to the 100 MHz Reference Clock source. This delay should not exceed 12ns per PCI Express
specification. The delay budget includes on-chip and off-chip delays. In general terms, all Reference Clock nets in
a system should be matched within 38.1 cm (15 in.).
Figure 3 illustrates Reference Clock transport delay delta.
The PEX 8618 PEX_REFCLKn/p signal is the Reference Clock Input buffer. It has an internal DC-biasing circuit,
and hence, should be AC-coupled from the RefClk source driver. Use 0.01 to 0.1 µF capacitors (0603 or 0402-
size) to AC-couple the Reference Clock input, as illustrated in
Figure 4 .
PLL1
CDR1
PLL2
CDR2
RefClk
Rx1
Rx2 Tx1
Tx2
Channel
Channel
Device 1 Device 2
T1
T2
T3
T4
T5
Transport Delay Delta = (T1+T2+T3) – (T4+T5) < 12 ns
Figure 3. Transport Delay Delta
Figure 4. PEX 8618 RefClk Circuit
PEX 8618 Quick Start Hardware Design Guide – Version 1.2
Copyright © 2009 by PLX Technology, Inc. All rights reserved.
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