1.4
Spread Spectrum Clocking (SSC)
Many PCI Express systems implement spread spectrum clocking in order to minimize EMI by spreading the
spectral energy of the clock signal over a wide frequency band. In SSC systems, PCI Express components
generally need to use a reference clock provided by the same source. This allows a transmitter PLL and receiver
clock recovery function (CDR) to track the modulation frequency and stay in sync with each other. If only one side
of the link uses a SSC reference clock and the other side does not, the transmitter and receiver circuits will not be
able to properly track one another. For example, if a system designer implements a PCI Express add-in card that
interfaces to an SSC system and also has a cable connection to a downstream card that is utilizing a constant
frequency clock source (CFC), the downstream interface will not link-up. To solve this problem, a system designer
using the PEX 8618 can either use the SSC isolation feature (explained in section
) or provide a means to
pass the SSC clock to the downstream component.
1.4.1
Spread Spectrum Clock Isolation
The PEX 8618 provides a new feature that helps eliminate the issues that exist when trying to communicate
between two different systems, where one or both of those systems use SSC clocking.
The PEX 8618 has the necessary buffering and logic required to allow the upstream port to operate using both an
SSC clock and a constant frequency clock (CFC) source. This feature is enabled when the signal
STRAP_SSC_ISO_ENABLE# is pulled down to VSS. In order to use the SSC isolation feature, the upstream port
must be port 0, and its programmed port width must be x4 or x8.
Enabling this feature provides the benefit of allowing downstream components to operate using an independent
CFC clock source. If a PEX 8618 is placed into a system that uses spread spectrum clocking, and the SSC
isolation feature is enabled, the downstream ports of the PEX 8618 will be clocked by a CFC clock source.
System designers can then connect to a remote system without the requirements of sharing a reference clock
source. The remote system must utilize a CFC clock source that meets the PCI E/-300ppm requirements.
Figure 5
depicts running the PEX 8618 using the standard distributed clocking scheme for PCI Express. If SSC
isolation is not used, the PEX_REFCLK_CFCp/n inputs can be left unconnected.
PEX 8618
Port 0
Port 1
. . .
Port N
VDD25
PEX_REFCLKp/n
Upstream
STRAP_SSC_ISO_ENABLE#
Downstream
Device
RefClk
Generator
(If SSC then required
to be from same
source)
Downstream
Device
Device
Figure 5. Single Reference Clock Scheme (STRAP_SSC_ISO_ENABLE# pulled high)
PEX 8618 Quick Start Hardware Design Guide – Version 1.2
Copyright © 2009 by PLX Technology, Inc. All rights reserved.
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