Circuit-, IC descriptions and list of abbreviations
EN 128
LX7500R
9.
The sound processing is always done in stereo (that means
separate left- and right-channel).
a) Record-Path:
The complete selection of the audio signal for recording is done
by a HEF4052 [7501], which is a dual four-to-one multiplexer.
The input lines for the selector [7501] are coming either from
MSP [7600] (“AFEL”/”AFER”) or cinch rear in 1 (“AIN1L”/
”AIN1R”) or cinch rear in 2 (“AIN2L”/”AIN2R”) or the cinch in
front (“AINFL”/AINFR”). The [7501] is controlled via “RSA1”-
and “RSA2”-signals coming from the MSP [7600]. The MSP
acts as a port expander of the CC-P. The Op-Amp on the
output [7504] is necessary for performance reasons and acts
also as a driver. The selected signals “ARADC” and “ALADC”
are directly fed to the Audio-ADC.
As there can exist also a fifth input in case of DV-In is present
the corresponding analog audio signals from the DVIO-board
are firstly routed via extra cable and connector [1960] to the
MSP, which acts as a preselector between audio from internal
frontend or the DV-Input.
b) Line-Out-Path:
see chapter 9.4.3
c) Digital Audio Output-Path without IOE-Print:
Additionally to analog audio the set is also equipped with a
digital output via cinch plug [1951]. The signal is generated on
the dig. board and routed via audio interface cable and
connector [1900] to the Ana-PCB. Here the “DAOUT”-line first
passes a 6-fold inverter [7580] being used as a driver and for
performance reasons (noise reduction, jitter, etc.). Afterwards
a transformer [5580] is necessary to achieve the correct level
and also to have a floating output with isolated ground before
the signal is fed via [3580] to cinch plug [1951]. The capacitors
[2580], [2582] and [2583] perform an AC-coupling between
connector- and set-ground.
d) Digital Audio Output-Path with IOE-Print:
see chapter 9.3.4.f
e) Digital Audio Input-Path with IOE-Print:
see chapter 9.3.4.g
9.4.3
Audio ADC/DAC
The conversion of analog audio signals from the record-
selector [7501] in the I/O (“ALADC”- & “ARADC”) is done via
UDA1361TS [7005]. This IC can process input signals up to
2Vrms by using an external resistor [3039], [3041] in series to
the input pins. As the level from the DVIO-Board is only 1Vrms
a 6dB step can be performed by setting pin 7 of [7005] to 3,3V
via [7006] and “PWONSW”-line controlled by the CC-P to use
the whole dynamic range of the ADC. All required clock signals
are generated on the dig. board and only the audio data
(“A_DAT”-line) are routed from Ana- to Dig.-PCB for further
processing.
The transformation of dig. audio back to the analog domain is
done by UDA1334BTS [7001]. All necessary clock signals are
coming from the dig. board and dig. audio data (“D_DATA0”-
line) are converted into analog signals, which are available at
pin 14 and pin 16 of [7001]. Afterwards an Op-Amp. [7002] (line
driver & level adaptation) which also works as a low-pass-filter
to increase signal performance (noise, distortions,...) is
passed. Then both signals (“ALDAC” & “ARDAC”) are directly
routed to the rear cinch output. The DAC has also a mute
possibility, which can be activated by setting pin 8 to 3,3V via
[7003]. This mute is controlled either by the dig. board
(“D_IKLL”-line) or the “IPFAIL”-signal from power-supply-unit.
In addition to that the DAC [7001] and the cinch outputs can be
killed (muted) in case of “digital silence” by the circuit around
[7008], [7009] and [7010], when no audio data are available
(e.g. “D_DATA0”-line zero).
The signals from the audio DAC part (“ARDAC”/”ALDAC”) are
directly routed to both cinch rear outputs, which are connected
in parallel. To avoid plops and any other audible noise on the
output there is a mute-stage implemented [7509], [7511] for
each channel. The activation is done via “AKILL”-line, which is
a combination of the “KILL” from CC-P, “DAC_MUTE” from
DAC-part and “IPFAIL” from the power-supply-unit. The circuit
around [6430], [6431], [7430] and [7404] generates this signal.
