EN 106
7.
LX7500R
Circuit Diagrams and PWB Layouts
TESTPIN
GND
VDD
RESER
VED
DVDD
AVDD
NC
PLLGND
DGND
AGND
DECODER/
BIAS
DATA
INTERFACE
LINK
RECEIVED
CONTROL
STATE
MACHINE
LOGIC
TRANSMIT
CLOCK
PLL
XTAL OSC.
ENCODER
DATA
GENERATOR
CURRENT
AND
VOLTAGE
TEST1
TEST0
C|LKON
ISO_
LPS
CPS
PLLVDD
R0
R1
TPBIAS0
TPA0+
TESTM
TPA0-
TPB0+
TPB0-
XI
XO
TIMER
ARBITR’N
AND
PD
RESET_
CNA
PC2
PC1
PC0
D7
D6
D5
D4
D3
D2
D1
D0
CTL1
CTL0
LREQ
SYSCLK
1%
F212 C13
F213 C13
F214 C13
F215 C13
F216 D13
F217 C13
I213 D6
I214 D6
I215 A6
I201 F2
I211 B7
I227 C7
not used
BOARD_ID
1%
for DV_IN only
I225 C7
5201 F5
always present
5203 H2
5204 I1
6200 G4
7200 A5
7201 B12
7202 H5
F1201 B1
F1202 A1
F1203 A1
F1205 A2
I216 B6
I217 A8
I218 C7
I219 C7
I220 G12
I221 G12
I222 C7
I223 G12
I224 G8
F210 C13
I226 C7
1%
3289 H13
3290 I13
3291 I13
3292 I13
3293 I13
3294 F12
3295 F12
3296 F12
3297 F8
I200 H4
3299 F8
I202 G2
I203 H2
I204 I2
I205 H11
I206 G4
I207 A3
I208 B3
I209 B3
I210 C2
4204 G12
I212 C7
5200 F2
3265 G8
5202 G2
3267 G8
3268 G8
3269 G8
3270 G12
3271 G12
3272 G13
3273 G8
3274 F12
3275 G5
F1204 A2
3277 F12
F200 D12
F201 C9
F203 C3
F204 C13
F205 C13
F206 C13
F207 C13
F208 C13
F209 C13
3287 H13
F211 C13
not used
not used
3245 D6
3246 E12
3247 E12
3248 D8
3249 E12
3250 E12
3251 E12
3298 F8
3253 D2
3315 F8
3316 F8
3317 F8
3318 F8
3319 F8
3320 F13
4201 D6
4202 D6
4203 G12
3263 F8
4205 A4
not used
not used
3266 G8
3223 B6
3224 C12
3225 C7
3226 C12
3227 C12
3228 C6
3229 C12
3230 D13
3231 C7
3276 G7
3233 C2
3278 F12
3279 F12
3280 A7
3281 A7
3282 A8
3283 A2
3284 A8
3285 A6
3286 H13
3243 D12
3288 H13
1%
not used
3204 D6
3205 A2
3206 B7
3207 B8
3252 E12
3209 B8
3254 E12
3255 E13
3256 E13
3257 E13
3258 E13
3259 E13
3260 F12
3261 E3
3262 F8
3219 D13
3264 F8
3221 C12
220R FOR C2
220R FOR C2
220R FOR C2
220R FOR C2
220R FOR C2
LINK
3222 C12
22R FOR C2
2226 I5
2227 I5
3232 C2
2229 I5
3234 C6
3235 C13
3236 C7
3237 D12
3238 C6
3239 D12
3240 C2
3241 D12
3242 C7
3200 E6
3244 D12
3203 H5
1%
1%
2206 G3
2207 F2
3208 B7
2210 G2
3210 C12
3211 C12
3212 B2
3213 B3
3214 C12
3215 C12
3216 B6
3217 C12
3218 C12
2223 I4
3220 B7
2225 I4
3
4
5
6
7
8
2228 I5
10
2230 I6
2231 I6
2232 I6
2233 I7
2234 I7
2235 A5
2236 G3
2237 B9
2238 B6
3202 F12
G
1
2
3
4
5
2209 G2
7
2212 H1
2214 H2
2215 H2
2217 I2
2218 I2
2219 I3
2220 I3
2221 I3
2222 I3
2224 I4
H
I
A
B
C
D
E
F
9
H
11
12
13
14
A
B
C
D
E
1201 D1
F
PHY
allways present
not used
not used
not used
I
1203 A1
6
8
9
10
11
12
13
14
1
2
2200 B2
2201 C2
2202 D1
2203 D2
2204 D2
2205 D2
F211
G
1203
SR
1
2
3
4
5
6
7
8
3205
6K34
I208
100n
2209
33R
3222
1R0
3209
3288
4K7
I216
I221
100R
3272
3237
100n
2231
33R
3317
100R
I213
F203
100n
2222
100R
3319
4K7
3250
I204
3259
4K7
82R
3224
33R
3243
3297
100R
3245
10R
I211
3221
33R
33R
3211
2233
100n
100u
2212
3270
100R
I201
2229
100n
4K7
3267
10K
3283
10K
3206
33R
3214
F209
2223
100n
F210
F208
I205
F206
I226
100n
2226
I206
330R
3275
3233
56R
10K
3219
100n
2219
4K7
3286
F1203
12p
2203
100n
2218
10R
3236
2202
F217
12p
I207
33R
3251
2227
100n
3293
4K7
F1202
2205
100n
3298
100R
3274
100R
4204
1R0
3261
I218
I219
10R
3242
I215
10R
3231
56R
3232
33R
3254
4K7
3256
3320
10K
F204
3225
10R
F1204
3255
4K7
3277
100R
PDTC144EU
7202
I225
F207
2217
100n
33R
3229
3266
4K7
4201
10R
3228
10R
3248
3215
33R
2237
100n
2235
1n0
I220
100n
3291
4K7
2214
33R
3241
100R
3318
100n
2234
TLMH3100
6200
33R
3226
10K
3235
4K7
3263
2220
100n
3294
100R
5K1
3240
I224
100R
3315
10R
3285
33R
3217
4203
100n
2224
10R
3234
100n
2230
270p
2201
100n
2215
F1201
2232
100n
3249
33R
100R
3278
5201
I222
3200
10K
4K7
3287
4K7
3289
22K
3257
33R
3273
3203
10K
3218
33R
F200
I217
3253
1R0
61
70
I203
107
113
120
132
138
12
18
24
35
44
54
SCLK
88
1
62
2
63
3
64
6
78
84
90
95
3
51
4
52
5
58
6
59
7
72
8
71
9
104
RESET_
42
11
66
67
12
13
68
14
105
15
129
16
144
17
130
2
50
PHYD2
80
79
PHYD3
PHYD4
76
PHYD5
75
PHYD6
74
PHYD7
73
1
49
10
65
LINKON
92
LPS
91
LREQ
87
PD
48
PHYCTL0
86
PHYCTL1
85
PHYD0
82
PHYD1
81
38
HIFINT_
HIFMUX
46
40
HIFRD_
36
HIFSC_
HIFWAIT
41
37
HIFWR_
ISON
93
39
HIFD10
8
HIFD11
7
HIFD12
4
HIFD13
3
HIFD14
2
HIFD15
1
HIFD8
10
HIFD9
9
22
21
HIFAD1
HIFAD2
20
HIFAD3
19
HIFAD4
16
HIFAD5
15
HIFAD6
14
HIFAD7
13
HIFALE
32
31
HIFA2
HIFA3
30
HIFA4
29
HIFA5
28
HIFA6
27
HIFA7
26
HIFA8
25
HIFAD0
17
23
34
43
53
60
69
HIF16BIT
45
HIFA0
33
HIFA1
5
77
83
89
94
106
112
119
131
137
11
AV2FSYNC
125
143
AV2READY
AV2SY
126
AV2SYNC
128
AV2VALID
127
CLK50
55
CYCLEIN
56
CYCLEOUT
57
AV2D3
136
139
AV2D4
AV2D5
140
AV2D6
141
142
AV2D7
AV2ENDPCK
123
AV2ERR0|LTLEND
121
122
AV2ERR1|DATINV
AV1READY
118
AV1SY
101
AV1SYNC
103
AV1VALID
102
124
AV2CLK
AV2D0
133
AV2D1
134
AV2D2
135
AV1D4
114
AV1D5
115
116
AV1D6
AV1D7
117
AV1ENDPCK
98
96
AV1ERR0
AV1ERR1
97
AV1FSYNC
100
STATUS
CONTROL
REGISTERS
AND
1394MODE
47
AV1CLK
99
AV1D0
108
109
AV1D1
AV1D2
110
AV1D3
111
TRANSMITTER / RECEIVER
AV
2
TRANSMITTER / RECEIVER
AV
1
PDI1394L40
7201
LINK
CORE
AND
4205
ASYNC
RECEIVER
8-BIT
TRANSMITTER
MEMORY
PACKETS
12KB BUFFER
INTERFACE
ISOCH & ASYNC
3258
22K
I223
100n
2210
F214
4K7
3269
100R
3260
28
27
37
36
35
34
38
59
60
22
14
57
58
56
40
41
53
2
29
1
54
55
16
43
44
45
46
47
20
21
13
17
18
63
64
25
26
61
62
23
15
4
5
19
6
7
8
9
10
11
12
48
49
50
30
31
42
51
52
3
24
7200
PDI1394P25
PDI1394P25
32
33
39
33R
3246
F213
2200
1u0
100R
3271
3239
33R
4202
2204
100n
5202
24M576
1201
CX-11F
5204
4K7
3292
3280
10K
3284
1R0
I214
100n
2221
100R
3299
2228
100n
3268
4K7
3238
10R
100R
3279
3282
10K
10R
3220
100R
3202
3216
10R
3230
10K
F212
2236
4u7
35V
3276
100n
2238
1K0
3264
4K7
5203
F1205
3244
33R
F215
100n
2206
I227
2207
100n
3252
33R
100n
2225
10K
3204
3295
100R
3210
33R
100R
3296
10K
3207
3262
4K7
F205
33R
3247
5200
56R
3212
4K7
3265
I210
I202
100R
I209
3316
3290
4K7
3227
33R
56R
3213
3223
10R
3208
10K
3281
10K
I200
F201
F216
I212
L_D(5)
L_FSYNC
L_VAL
L_SYNC
+3V3_LINK
MPIO2_1394_IRQn
L_D(1)
MPIO23_1394_LED
PCI_AD(31:0)
PCI_AD(0)
PCI_AD(1)
L_D(2)
L_CLK
L_D_CTL
MPIO9_BOARD_ID_0
MPIO10_BOARD_ID_1
MPIO11_BOARD_ID_2
MPIO12_BOARD_ID_3
MPIO21_1394_PO
WERDO
W
N
+3V3_IEEE_D
MPIO8_1394_CNA
RESET_1394n
+3V3_LINK
+3V3_IEEE_D
PCI_AD(31:0)
+3V3_IEEE_D
+3V3_IEEE_PLL
+3V3_IEEE_A
+3V3
MX_D(5)
MX_D(6)
MX_D(7)
MX_D(7:0)
MX_VAL
MX_SYNC
MX_CLK
+3V3_LINK
AV1SY
AV1ENDPCK
+5V
MX_D_CTL
+3V3_LINK
+3V3_LINK
AV2ENDPCK
AV2FSYNC
MX_D(0)
MX_D(1)
MX_D(2)
MX_D(3)
MX_D(4)
+3V3_IEEE_D
+3V3_IEEE_D
+3V3_IEEE_PLL
+3V3_LINK
L_D(7:0)
L_D(7)
L_D(6)
L_D(4)
L_D(3)
L_D(0)
+3V3_IEEE_A
+3V3_IEEE_D
+3V3_IEEE_D
+3V3_LINK
+3V3_LINK
+3V3
+3V3
PCI_AD(6)
PCI_AD(7)
PCI_AD(8)
+3V3_LINK
PCI_CBE(1)
PCI_CBE(2)
XIO_SEL1
PCI_AD(24)
PCI_AD(25)
PCI_AD(26)
PCI_AD(27)
PCI_AD(28)
PCI_AD(29)
PCI_AD(30)
PCI_AD(31)
+3V3_LINK
PCI_AD(2)
PCI_AD(3)
PCI_AD(4)
PCI_AD(5)
DIGITAL BOARD Chrysalis PPS E4 AV3+