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Philips LPC214 Series, User Manual

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Philips Semiconductors

UM10139

Volume 1

Chapter 25: Supplementary information

 

© Koninklijke Philips Electronics N.V. 2005. All rights reserved.

User manual

Rev. 01 — 15 August 2005 

342

continued >>

 

10.3.4

UART1 Fractional Divider Register (U1FDR - 
0xE001 0028) . . . . . . . . . . . . . . . . . . . . . . . .  116

10.3.5

UART1 baudrate calculation . . . . . . . . . . . . .  117

10.3.6

UART1 Interrupt Enable Register (U1IER - 
0xE001 0004, when DLAB = 0)  . . . . . . . . . .  118

10.3.7

UART1 Interrupt Identification Register (U1IIR - 
0xE001 0008, Read Only)  . . . . . . . . . . . . . .  119

10.3.8

UART1 FIFO Control Register (U1FCR - 
0xE001 0008) . . . . . . . . . . . . . . . . . . . . . . . .  121

10.3.9

UART1 Line Control Register (U1LCR - 
0xE001 000C). . . . . . . . . . . . . . . . . . . . . . . .  122

10.3.10

UART1 Modem Control Register (U1MCR - 
0xE001 0010),  LPC2144/6/8 only . . . . . . . .  123

10.3.11

UART1 Line Status Register (U1LSR - 
0xE001 0014, Read Only) . . . . . . . . . . . . . .   125

10.3.12

UART1 Modem Status Register (U1MSR - 
0xE001 0018), LPC2144/6/8 only  . . . . . . . .   127

10.3.13

UART1 Scratch pad register (U1SCR - 
0xE001 001C)  . . . . . . . . . . . . . . . . . . . . . . .   127

10.3.14

UART1 Auto-baud Control Register (U1ACR - 
0xE001 0020). . . . . . . . . . . . . . . . . . . . . . . .   127

10.3.15

Auto-baud. . . . . . . . . . . . . . . . . . . . . . . . . . .   128

10.3.16

Auto-baud Modes. . . . . . . . . . . . . . . . . . . . .   129

10.3.17

UART1 Transmit Enable Register (U1TER - 
0xE001 0030). . . . . . . . . . . . . . . . . . . . . . . .   130

10.4

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . .   131

Chapter 11: I

2

C interfaces I

2

C0 and I

2

C1

11.1

Features  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  133

11.2

Applications . . . . . . . . . . . . . . . . . . . . . . . . . .  133

11.3

Description . . . . . . . . . . . . . . . . . . . . . . . . . . .  133

11.4

Pin description . . . . . . . . . . . . . . . . . . . . . . . .  134

11.5

I

2

C operating modes . . . . . . . . . . . . . . . . . . .  134

11.5.1

Master Transmitter mode  . . . . . . . . . . . . . . .  134

11.5.2

Master Receiver mode . . . . . . . . . . . . . . . . .  135

11.5.3

Slave Receiver mode . . . . . . . . . . . . . . . . . .  136

11.5.4

Slave Transmitter mode  . . . . . . . . . . . . . . . .  137

11.6

I

2

C Implementation and operation . . . . . . . .  138

11.6.1

Input filters and output stages  . . . . . . . . . . .  138

11.6.2

Address Register, I2ADDR . . . . . . . . . . . . . .  140

11.6.3

Comparator. . . . . . . . . . . . . . . . . . . . . . . . . .  140

11.6.4

Shift register, I2DAT  . . . . . . . . . . . . . . . . . . .  140

11.6.5

Arbitration and synchronization logic  . . . . . .  140

11.6.6

Serial clock generator . . . . . . . . . . . . . . . . . .  141

11.6.7

Timing and control  . . . . . . . . . . . . . . . . . . . .  141

11.6.8

Control register, I2CONSET and I2CONCLR  141

11.6.9

Status decoder and Status register  . . . . . . .  142

11.7

Register description  . . . . . . . . . . . . . . . . . . .  142

11.7.1

I

2

C Control Set register (I2CONSET: I2C0, 

I2C0CONSET - 0xE001 C000 and I2C1, 
I2C1CONSET - 0xE005 C000) . . . . . . . . . . .  143

11.7.2

I

2

C Control Clear register (I2CONCLR: I2C0, 

I2C0CONCLR - 0xE001 C018 and I2C1, 
I2C1CONCLR - 0xE005 C018). . . . . . . . . . .  144

11.7.3

I

2

C Status register (I2STAT: I2C0, I2C0STAT - 

0xE001 C004 and I2C1, I2C1STAT - 
0xE005 C004). . . . . . . . . . . . . . . . . . . . . . . .  145

11.7.4

I

2

C Data register (I2DAT: 

 

I2C0, I2C0DAT - 0xE001 C008 and 

 

I2C1, I2C1DAT - 0xE005 C008) . . . . . . . . . .  145

11.7.5

I

2

C Slave Address register (I2ADR: I2C0, 

I2C0ADR - 0xE001 C00C and I2C1, I2C1ADR - 
address 0xE005 C00C) . . . . . . . . . . . . . . . .   146

11.7.6

I

2

C SCL High duty cycle register (I2SCLH: I2C0, 

I2C0SCLH - 0xE001 C010 and I2C1, I2C1SCLH - 
0xE0015 C010)  . . . . . . . . . . . . . . . . . . . . . .   146

11.7.7

I

2

C SCL Low duty cycle register (I2SCLL: I2C0 - 

I2C0SCLL: 0xE001 C014; I2C1 - I2C1SCLL: 
0xE0015 C014)  . . . . . . . . . . . . . . . . . . . . . .   146

11.7.8

Selecting the appropriate I

2

C data rate and duty 

cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   146

11.8

Details of I

2

C operating modes  . . . . . . . . . .   147

11.8.1

Master Transmitter mode . . . . . . . . . . . . . . .   148

11.8.2

Master Receiver mode . . . . . . . . . . . . . . . . .   148

11.8.3

Slave Receiver mode . . . . . . . . . . . . . . . . . .   149

11.8.4

Slave Transmitter mode . . . . . . . . . . . . . . . .   153

11.8.5

Miscellaneous States . . . . . . . . . . . . . . . . . .   159

11.8.6

I2STAT = 0xF8 . . . . . . . . . . . . . . . . . . . . . . .   159

11.8.7

I2STAT = 0x00 . . . . . . . . . . . . . . . . . . . . . . .   159

11.8.8

Some special cases . . . . . . . . . . . . . . . . . . .   160

11.8.9

Simultaneous repeated START conditions from 
two masters . . . . . . . . . . . . . . . . . . . . . . . . .   160

11.8.10

Data transfer after loss of arbitration . . . . . .   160

11.8.11

Forced access to the I

2

C-bus. . . . . . . . . . . .   160

11.8.12

I

2

C-bus obstructed by a low level on 

 

SCL or SDA . . . . . . . . . . . . . . . . . . . . . . . . .   161

11.8.13

Bus error  . . . . . . . . . . . . . . . . . . . . . . . . . . .   161

11.8.14

I

2

C State service routines  . . . . . . . . . . . . . .   162

11.8.15

Initialization  . . . . . . . . . . . . . . . . . . . . . . . . .   163

11.8.16

I

2

C interrupt service . . . . . . . . . . . . . . . . . . .   163

11.8.17

The State service routines . . . . . . . . . . . . . .   163

11.8.18

Adapting State services to an application  . .   163

11.9

Software example . . . . . . . . . . . . . . . . . . . . .   163

11.9.1

Initialization routine  . . . . . . . . . . . . . . . . . . .   163

Summary of Contents for LPC214 Series

Page 1: ...ev 01 15 August 2005 User manual Document information Info Content Keywords LPC2141 LPC2142 LPC2144 LPC2146 LPC2148 LPC2000 LPC214x ARM ARM7 embedded 32 bit microcontroller USB 2 0 USB device Abstract An initial LPC214x User Manual revision ...

Page 2: ...emiconductors UM10139 Volume 1 LPC2141 2 4 6 8 UM Contact information For additional information please visit http www semiconductors philips com For sales office addresses please send an email to sales addresses www semiconductors philips com Revision history Rev Date Description 01 20050815 Initial version ...

Page 3: ...l systems 1 2 Features 16 32 bit ARM7TDMI S microcontroller in a tiny LQFP64 package 8 to 40 kB of on chip static RAM and 32 to 512 kB of on chip flash program memory 128 bit wide interface accelerator enables high speed 60 MHz operation In System In Application Programming ISP IAP via on chip boot loader software Single flash sector or full chip erase in 400 ms and programming of 256 bytes in 1 m...

Page 4: ...cations Industrial control Medical systems Access control Point of sale Communication gateway Embedded soft modem General purpose applications 1 4 Device information 1 While the USB DMA is the primary user of the additional 8 kB RAM this RAM is also accessible at any time by the CPU as a general purpose RAM for data and code storage 1 5 Architectural overview The LPC2141 2 4 6 8 consists of an ARM...

Page 5: ...ced Instruction Set Computer RISC principles and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers This simplicity results in a high instruction throughput and impressive real time interrupt response from a small and cost effective processor core Pipeline techniques are employed so that all parts of the processing and ...

Page 6: ...addressed memory Word and halfword accesses to the memory ignore the alignment of the address and access the naturally aligned value that is addressed so a memory access ignores address bits 0 and 1 for word accesses and ignores bit 0 for halfword accesses Therefore valid reads and writes require data accessed as halfwords to originate from addresses with address line 0 being 0 addresses ending wi...

Page 7: ...LER SYSTEM FUNCTIONS PLL0 USB clock PLL1 SYSTEM CONTROL 32 64 128 256 512 kB FLASH ARM7TDMI S LPC2141 42 44 46 48 INTERNAL SRAM CONTROLLER 8 16 32 kB SRAM ARM7 local bus VPB VLSI peripheral bus SCL0 SCL1 SDA0 SDA1 4 CAP0 4 CAP1 8 MAT0 8 MAT1 I2C BUS SERIAL INTERFACES 0 AND 1 CAPTURE COMPARE W EXTERNAL CLOCK TIMER 0 TIMER 1 EINT3 to EINT0 EXTERNAL INTERRUPTS D D UP_LED CONNECT VBUS USB 2 0 FULL SPE...

Page 8: ...AL OF 64 kB ON CHIP NON VOLATILE MEMORY LPC2142 RESERVED ADDRESS SPACE 8 kB ON CHIP STATIC RAM LPC2141 16 kB ON CHIP STATIC RAM LPC2142 2144 32 kB ON CHIP STATIC RAM LPC2146 2148 RESERVED ADDRESS SPACE BOOT BLOCK 12 kB REMAPPED FROM ON CHIP FLASH MEMORY RESERVED ADDRESS SPACE AHB PERIPHERALS VPB PERIPHERALS 3 5 GB 0x4000 4000 0x4000 3FFF 0x4000 8000 0x4000 7FFF 0xE000 0000 0xF000 0000 0xFFFF FFFF ...

Page 9: ...heral areas are 2 megabyte spaces which are divided up into 128 peripherals Each peripheral space is 16 kilobytes in size This allows simplifying the Fig 3 Peripheral memory map AHB PERIPHERALS RESERVED RESERVED VPB PERIPHERALS 0xFFFF FFFF 0xFFE0 0000 0xFFDF FFFF 0xF000 0000 0xEFFF FFFF 0xE020 0000 0xE01F FFFF 0xE000 0000 3 5 GB 3 5 GB 2 MB 3 75 GB 4 0 GB 2 MB 4 0 GB Notes AHB section is 128 x 16 ...

Page 10: ...ies An implication of this is that word and half word registers must be accessed all at once For example it is not possible to read or write the upper byte of a word register separately Fig 4 AHB peripheral map Table 2 VPB peripheries and base addresses VPB peripheral Base address Peripheral name 0 0xE000 0000 Watchdog timer 1 0xE000 4000 Timer 0 2 0xE000 8000 Timer 1 VECTORED INTERRUPT CONTROLLER...

Page 11: ...0 001C as shown in Table 3 below a small portion of the Boot Block and SRAM spaces need to be re mapped in order to allow alternative uses of interrupts in the different operating modes described in Table 4 Re mapping of the interrupts is accomplished via the Memory Mapping Control feature Section 3 7 Memory mapping control on page 26 3 0xE000 C000 UART0 4 0xE001 0000 UART1 5 0xE001 4000 PWM 6 0xE...

Page 12: ...the branch to the interrupt handlers There are three reasons this configuration was chosen 1 To give the FIQ handler in the Flash memory the advantage of not having to take a memory boundary caused by the remapping into account Table 3 ARM exception vector locations Address Exception 0x0000 0000 Reset 0x0000 0004 Undefined Instruction 0x0000 0008 Software Interrupt 0x0000 000C Prefetch Abort instr...

Page 13: ...ors to deal with arbitrary boundaries in the middle of code space 3 To provide space to store constants for jumping beyond the range of single word branch instructions Re mapped memory areas including the Boot Block and interrupt vectors continue to appear in their original location in addition to the re mapped address Details on re mapping and examples can be found in Section 3 7 Memory mapping c...

Page 14: ... FROM TOP OF FLASH MEMORY RESERVED ADDRESSING SPACE 32 kB ON CHIP SRAM 0 0 GB ACTIVE INTERRUPT VECTORS FROM FLASH SRAM OR BOOT BLOCK 0x8000 0000 0x4000 8000 0x4000 7FFF 0x4000 0000 0x3FFF FFFF 0x0000 0000 0x7FFF FFFF Note Memory regions are not drawn to scale 1 0 GB 2 0 GB 12 kB 2 0 GB BOOT BLOCK INTERRUPT VECTORS SRAM INTERRUPT VECTORS 512 kB FLASH MEMORY 12 kB BOOT BLOCK RE MAPPED TO HIGHER ADDR...

Page 15: ...vice this range is from 0x4000 8000 to 0x7FCF FFFF where the 8 kB USB DMA RAM starts and from 0x7FD0 2000 to 0x7FFF CFFF Address space between 0x8000 0000 and 0xDFFF FFFF labelled Reserved Adress Space Reserved regions of the AHB and VPB spaces See Figure 3 Unassigned AHB peripheral spaces See Figure 4 Unassigned VPB peripheral spaces See Table 2 For these areas both attempted data access and inst...

Page 16: ...block functions UM10139 Chapter 3 System Control Block Rev 01 15 August 2005 User manual Table 5 Pin summary Pin name Pin direction Pin description X1 Input Crystal Oscillator Input Input to the oscillator and internal clock generator circuits X2 Output Crystal Oscillator Output Output from the oscillator amplifier EINT0 Input External Interrupt Input 0 An active low high level or falling rising e...

Page 17: ... control registers Name Description Access Reset value 1 Address External Interrupts EXTINT External Interrupt Flag Register R W 0 0xE01F C140 INTWAKE Interrupt Wakeup Register R W 0 0xE01F C144 EXTMODE External Interrupt Mode Register R W 0 0xE01F C148 EXTPOLAR External Interrupt Polarity Register R W 0 0xE01F C14C Memory Mapping Control MEMMAP Memory Mapping Control R W 0 0xE01F C040 Phase Locke...

Page 18: ...in the LPC2141 2 4 6 8 can operate in one of two modes slave mode and oscillation mode In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF CC in Figure 6 drawing a with an amplitude of at least 200 mVrms The X2 pin in this configuration can be left not connected If slave mode is selected the FOSC signal of 50 50 duty cycle can range from 1 MHz to 50 MHz Externa...

Page 19: ... Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1 CX2 1 MHz 5 MHz 10 pF NA NA 20 pF NA NA 30 pF 300 Ω 58 pF 58 pF 5 MHz 10 MHz 10 pF 300 Ω 18 pF 18 pF 20 pF 300 Ω 38 pF 38 pF 30 pF 300 Ω 58 pF 58 pF 10 MHz 15 MHz 10 pF 300 Ω 18 pF 18 pF 20 pF 220 Ω 38 pF 38 pF 30 pF 140 Ω 58 pF 58 pF 15 MHz 20 MHz 10 pF 220 Ω 18 pF 18 pF 20 pF 140 Ω 38 pF 38 pF 30 pF 80...

Page 20: ...UP register contains bits that enable individual external interrupts to wake up the microcontroller from Power down mode The EXTMODE and EXTPOLAR registers specify the level and edge sensitivity parameters Fig 7 FOSC selection algorithm True MIN f OSC 10 MHz MAX fOSC 25 MHz True MIN fOSC 1 MHz MAX fOSC 50 MHz MIN fOSC 1 MHz MAX fOSC 30 MHz Figure 7 mode a and or b Figure 7 mode a Figure 7 mode b O...

Page 21: ...mportant whenever a change of external interrupt operating mode i e active level edge is performed including the initialization of an external interrupt the corresponding bit in the EXTINT register must be cleared For details see Section 3 5 4 External Interrupt Mode register EXTMODE 0xE01F C148 and Section 3 5 5 External Interrupt Polarity register EXTPOLAR 0xE01F C14C For example if a system wak...

Page 22: ... active state In edge sensitive mode this bit is set if the EINT1 function is selected for its pin and the selected edge occurs on the pin Up to two pins can be selected to perform the EINT1 function see P0 3 and P0 14 description in Pin Configuration chapter on page 66 This bit is cleared by writing a one to it except in level sensitive mode when the pin is in its active state e g if EINT1 is sel...

Page 23: ...it Symbol Description Reset value 0 EXTWAKE0 When one assertion of EINT0 will wake up the processor from Power down mode 0 1 EXTWAKE1 When one assertion of EINT1 will wake up the processor from Power down mode 0 2 EXTWAKE2 When one assertion of EINT2 will wake up the processor from Power down mode 0 3 EXTWAKE3 When one assertion of EINT3 will wake up the processor from Power down mode 0 4 Reserved...

Page 24: ...NT1 is edge sensitive 2 EXTMODE2 0 Level sensitivity is selected for EINT2 0 1 EINT2 is edge sensitive 3 EXTMODE3 0 Level sensitivity is selected for EINT3 0 1 EINT3 is edge sensitive 7 4 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA Table 11 External Interrupt Mode register EXTMODE address 0xE01F C148 bit description Bit Symbol ...

Page 25: ...e same EINTx functionality are digitally combined using a positive logic OR gate In Edge Sensitive mode regardless of polarity the pin with the lowest GPIO port number is used Selecting multiple pins for an EINTx in edge sensitive mode could be considered a programming error The signal derived by this logic processing multiple external interrupt pins is the EINTi signal in the following logic sche...

Page 26: ...n Table 3 ARM exception vector locations on page 12 The MEMMAP register determines the source of data that will fill this table Table 13 System Control and Status flags register SCS address 0xE01F C1A0 bit description Bit Symbol Value Description Reset value 0 GPIO0M GPIO port 0 mode selection 0 0 GPIO port 0 is accessed via VPB addresses in a fashion compatible with previous LCP2000 devices 1 Hig...

Page 27: ...e multiplier can be an integer value from 1 to 32 in practice the multiplier value cannot be higher than 6 on the LPC2141 2 4 6 8 due to the upper frequency limit of the CPU The CCO operates in the range of 156 MHz to 320 MHz so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency The output divider may be set...

Page 28: ...egisters Generic name Description Access Reset value 1 System clock PLL0 Address Name USB 48 MHz clock PLL1 Address Name PLLCON PLL Control Register Holding register for updating PLL control bits Values written to this register do not take effect until a valid PLL feed sequence has taken place R W 0 0xE01F C080 PLL0CON 0xE01F C0A0 PLL1CON PLLCFG PLL Configuration Register Holding register for upda...

Page 29: ...iplier and divider values Connecting the PLL causes the processor and all chip functions to run from the PLL output clock Changes to the PLLCON register do not take effect until a correct PLL feed sequence has been given see Section 3 8 7 PLL Feed register PLL0FEED 0xE01F C08C PLL1FEED 0xE01F C0AC and Section 3 8 3 PLL Configuration register PLL0CFG 0xE01F C084 PLL1CFG 0xE01F C0A4 on page 30 Fig 9...

Page 30: ...alculation section on page 33 Table 16 PLL Control register PLL0CON address 0xE01F C080 PLL1CON address 0xE01F C0A0 bit description Bit Symbol Description Reset value 0 PLLE PLL Enable When one and after a valid PLL feed this bit will activate the PLL and allow it to lock to the requested frequency See PLLSTAT register Table 18 0 1 PLLC PLL Connect When PLLC and PLLE are both set to one and after ...

Page 31: ...e only in PLL0 i e the PLL that generates the CCLK USB dedicated PLL1 does not have this capability 3 8 6 PLL Modes The combinations of PLLE and PLLC are shown in Table 19 Table 18 PLL Status register PLL0STAT address 0xE01F C088 PLL1STAT address 0xE01F C0A8 bit description Bit Symbol Description Reset value 4 0 MSEL Read back for the PLL Multiplier value This is the value currently used by the PL...

Page 32: ...on resumes after a wakeup from Power down mode This would enable and connect the PLL at the same time before PLL lock is established If activity on the USB data lines is not selected to wake up the microcontroller from Power down mode see Section 3 5 3 Interrupt Wakeup register INTWAKE 0xE01F C144 on page 22 both the system and the USB PLL will be automatically be turned off and disconnected when ...

Page 33: ...ng from a lower clock than the processor see Section 3 11 VPB divider on page 40 2 Choose an oscillator frequency FOSC CCLK must be the whole non fractional multiple of FOSC 3 Calculate the value of M to configure the MSEL bits M CCLK FOSC M must be in the range of 1 to 32 The value written to the MSEL bits in PLLCFG is M 1 see Table 23 4 Find a value for P to configure the PSEL bits such that FCC...

Page 34: ... 2 an application using the USB configuring the PLL1 System design asks for FOSC 12 MHz and requires the USB clock of 48 MHz Based on these specifications M 48 MHz Fosc 48 MHz 12 MHz 4 Consequently M 1 3 will be written as PLLCFG 4 0 Value for P can be derived from P FCCO 48 MHz x 2 using condition that FCCO must be in range of 156 MHz to 320 MHz Assuming the lowest allowed frequency for FCCO 156 ...

Page 35: ...oordinated with program execution Wakeup from Power down or Idle modes via an interrupt resumes program execution in such a way that no instructions are lost incomplete or repeated Wake up from Power down mode is discussed further in Section 3 12 Wakeup timer on page 41 A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application ...

Page 36: ...e will cause the processor to resume execution 0 1 PD Power down mode when 1 this bit causes the oscillator and all on chip clocks to be stopped A wakeup condition from an external interrupt can cause the oscillator to restart the PD bit to be cleared and the processor to resume execution IMPORTANT PD bit can be set to 1 at any time if USBWAKE 0 In case of USBWAKE 1 it is possible to set PD to 1 o...

Page 37: ...r Counter 0 power clock control bit 1 2 PCTIM1 Timer Counter 1 power clock control bit 1 3 PCUART0 UART0 power clock control bit 1 4 PCUART1 UART1 power clock control bit 1 5 PCPWM0 PWM0 power clock control bit 1 6 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA 7 PCI2C0 The I2C0 interface power clock control bit 1 8 PCSPI0 The SPI...

Page 38: ... determines the minimum duration of RESET that must be asserted in order to guarantee a chip reset Once asserted RESET pin can be deasserted only when crystal oscillator is fully running and an adequate signal is present on the X1 pin of the microcontroller Assuming that an external crystal is used in the crystal oscillator subsystem after power on the RESET pin should be asserted for 10 ms For al...

Page 39: ...atchdog reset External reset EINT0 Wakeup EINT1 Wakeup EINT2 Wakeup EINT3 Wakeup RTC Wakeup START COUNT 2 n Oscillator output FOSC Reset to the on chip circuitry Reset to PCON PD Write 1 from VPB Reset USB Wakeup BOD Wakeup Table 27 Reset Source identification Register RSIR address 0xE01F C180 bit description Bit Symbol Description Reset value 0 POR Power On Reset POR event sets this bit and clear...

Page 40: ...ing during Idle mode 3 11 1 Register description Only one register is used to control the VPB Divider 1 Reset value reflects the data stored in used bits only It does not include reserved bits content 3 11 2 VPBDIV register VPBDIV 0xE01F C100 The VPB Divider register contains two bits allowing three divider values as shown in Table 29 2 WDTR This bit is set when the Watchdog Timer times out and th...

Page 41: ...her external circuitry e g capacitors and the characteristics of the oscillator itself under the existing ambient conditions Once a clock is detected the Wakeup Timer counts 4096 clocks then enables the on chip circuitry to initialize When the onboard modules initialization is complete the processor is released to execute instructions if the external Reset has been deasserted In the case where an ...

Page 42: ...it should program low level sensitivity for that channel because only in level mode will the channel logically OR the signals to wake the device The only flaw in this scheme is that the time to restart the oscillator prevents the LPC2141 2 4 6 8 from capturing the bus or line activity that wakes it up Idle mode is more appropriate than power down mode for devices that must capture and respond to e...

Page 43: ... in the RISR being 0 Since all other wakeup conditions have latching flags see Section 3 5 2 External Interrupt Flag register EXTINT 0xE01F C140 and Section 19 4 3 Interrupt Location Register ILR 0xE002 4000 on page 277 a wakeup of this type without any apparent cause can be assumed to be a Brown Out that has gone away 3 14 Code security vs debugging Applications in development typically need the ...

Page 44: ...t Thumb instructions During sequential code execution typically the prefetch buffer contains the current instruction and the entire Flash line that contains it The MAM uses the LPROT 0 line to differentiate between instruction and data accesses Code and data accesses use separate 128 bit buffers 3 of every 4 sequential 32 bit code or data accesses hit in the buffer without requiring a Flash access...

Page 45: ... 128 bit Data Buffer and an associated Address latch and comparator Control logic Wait logic Figure 12 shows a simplified block diagram of the Memory Accelerator Module data paths In the following descriptions the term fetch applies to an explicit Flash read request from the ARM Pre fetch is used to denote a Flash read of instructions beyond the current processor fetch address 4 3 1 Flash memory b...

Page 46: ... and take steps to insure that an unwanted Watchdog reset does not cause a system failure while programming or erasing the Flash memory In order to preclude the possibility of stale data being read from the Flash memory the LPC2141 2 4 6 8 MAM holding latches are automatically invalidated at the beginning of any Flash programming or erase operation Any subsequent read from a Flash address will cau...

Page 47: ...ns can be run at a somewhat slower but more predictable rate if more precise timing is required 4 6 Register description All registers regardless of size are on word address boundaries Details of the registers appear in the description of each function Table 30 MAM Responses to program accesses of various types Program Memory Request Type MAM Mode 0 1 2 Sequential access data in latches Initiate F...

Page 48: ...of MAM registers Name Description Access Reset value 1 Address MAMCR Memory Accelerator Module Control Register Determines the MAM functional mode that is to what extent the MAM performance enhancements are enabled See Table 33 R W 0x0 0xE01F C000 MAMTIM Memory Accelerator Module Timing control Determines the number of clocks used for Flash memory fetches 1 to 7 processor clocks R W 0x07 0xE01F C0...

Page 49: ...MTIM can be 001 For system clock between 20 MHz and 40 MHz Flash access time is suggested to be 2 CCLKs while in systems with system clock faster than 40 MHz 3 CCLKs are proposed 110 6 MAM fetch cycles are 6 CCLKs in duration 111 7 MAM fetch cycles are 7 CCLKs in duration Warning These bits set the duration of MAM Flash fetch operations as listed here Improper setting of this value may result in i...

Page 50: ...es which FIQ source s is are requesting an interrupt Vectored IRQs have the middle priority but only 16 of the 32 requests can be assigned to this category Any of the 32 requests can be assigned to any of the 16 vectored IRQ slots among which slot 0 has the highest priority and slot 15 has the lowest Non vectored IRQs have the lowest priority The VIC ORs the requests from all the vectored and non ...

Page 51: ...ests from various peripheral functions R W 0 0xFFFF F018 VICSoftIntClear Software Interrupt Clear Register This register allows software to clear one or more bits in the Software Interrupt register WO 0 0xFFFF F01C VICProtection Protection enable register This register allows limiting access to the VIC registers by software running in privileged mode R W 0 0xFFFF F020 VICVectAddr Vector Address Re...

Page 52: ...sters 0 15 each control one of the 16 vectored IRQ slots Slot 0 has the highest priority and slot 15 the lowest R W 0 0xFFFF F200 VICVectCntl1 Vector control 1 register R W 0 0xFFFF F204 VICVectCntl2 Vector control 2 register R W 0 0xFFFF F208 VICVectCntl3 Vector control 3 register R W 0 0xFFFF F20C VICVectCntl4 Vector control 4 register R W 0 0xFFFF F210 VICVectCntl5 Vector control 5 register R W...

Page 53: ...force the interrupt request with this bit number Writing zeroes to bits in VICSoftInt has no effect see VICSoftIntClear Section 5 4 2 0 1 Force the interrupt request with this bit number Table 38 Software Interrupt Clear register VICSoftIntClear address 0xFFFF F01C bit allocation Reset value 0x0000 0000 Bit 31 30 29 28 27 26 25 24 Symbol Access WO WO WO WO WO WO WO WO Bit 23 22 21 20 19 18 17 16 S...

Page 54: ...15 14 13 12 11 10 9 8 Symbol EINT1 EINT0 RTC PLL SPI1 SSP SPI0 I2C0 PWM0 Access RO RO RO RO RO RO RO RO Bit 7 6 5 4 3 2 1 0 Symbol UART1 UART0 TIMER1 TIMER0 ARMCore1 ARMCore0 WDT Access RO RO RO RO RO RO RO RO Table 41 Raw Interrupt status register VICRawIntr address 0xFFFF F008 bit description Bit Symbol Value Description Reset value 31 0 See VICRawIntr bit allocation table 0 The interrupt reques...

Page 55: ...te to FIQ or IRQ zeroes have no effect See Section 5 4 5 Interrupt Enable Clear register VICIntEnClear 0xFFFF F014 on page 55 and Table 45 below for how to disable interrupts 0 Table 44 Software Interrupt Clear register VICIntEnClear address 0xFFFF F014 bit allocation Reset value 0x0000 0000 Bit 31 30 29 28 27 26 25 24 Symbol Access WO WO WO WO WO WO WO WO Bit 23 22 21 20 19 18 17 16 Symbol USB AD...

Page 56: ...00C bit description Bit Symbol Value Description Reset value 31 0 See VICIntSelect bit allocation table 0 The interrupt request with this bit number is assigned to the IRQ category 0 1 The interrupt request with this bit number is assigned to the FIQ category Table 48 IRQ Status register VICIRQStatus address 0xFFFF F000 bit allocation Reset value 0x0000 0000 Bit 31 30 29 28 27 26 25 24 Symbol Acce...

Page 57: ...RO RO Bit 15 14 13 12 11 10 9 8 Symbol EINT1 EINT0 RTC PLL SPI1 SSP SPI0 I2C0 PWM0 Access RO RO RO RO RO RO RO RO Bit 7 6 5 4 3 2 1 0 Symbol UART1 UART0 TIMER1 TIMER0 ARMCore1 ARMCore0 WDT Access RO RO RO RO RO RO RO RO Table 51 FIQ Status register VICFIQStatus address 0xFFFF F004 bit description Bit Symbol Description Reset value 31 0 See VICFIQStatus bit allocation table A bit read as 1 indicate...

Page 58: ...ority such slot will be provided when the IRQ service routine reads the Vector Address register VICVectAddr Section 5 4 10 0x0000 0000 Table 54 Default Vector Address register VICDefVectAddr address 0xFFFF F034 bit description Bit Symbol Description Reset value 31 0 IRQ_vector When an IRQ service routine reads the Vector Address register VICVectAddr and no IRQ slot responds as described above this...

Page 59: ...0 0010 TIMER1 Match 0 3 MR0 MR1 MR2 MR3 Capture 0 3 CR0 CR1 CR2 CR3 5 0x0000 0020 UART0 Rx Line Status RLS Transmit Holding Register Empty THRE Rx Data Available RDA Character Time out Indicator CTI 6 0x0000 0040 UART1 Rx Line Status RLS Transmit Holding Register Empty THRE Rx Data Available RDA Character Time out Indicator CTI Modem Status Interrupt MSI 1 7 0x0000 0080 PWM0 Match 0 6 MR0 MR1 MR2 ...

Page 60: ... HARDWARE PRIORITY LOGIC IRQSTATUS 31 0 nVICFIQ NonVectIRQ Non vectored IRQ interrupt logic Priority 0 nVICIRQ VECTADDR0 31 0 VECTIRQ1 VECTIRQ15 VECTADDR1 31 0 VECTADDR15 31 0 IRQ Address select for highest priority interrupt VECTORADDR 31 0 VICVECT ADDROUT 31 0 DEFAULT VECTORADDR 31 0 Priority14 Priority15 Priority2 Priority1 VECTORADDR 31 0 SOURCE VECTORCNTL 5 0 ENABLE Vector interrupt 0 Vector ...

Page 61: ...e to clearly identify the interrupt that generated the interrupt request and as a result the VIC will return the default interrupt VicDefVectAddr 0xFFFF F034 This potentially disastrous chain of events can be prevented in two ways 1 Application code should be set up in a way to prevent the spurious interrupts from occurring Simple guarding of changes to the VIC may not be enough since for example ...

Page 62: ... and therefore execution will continue with all interrupts disabled However this can cause problems in the following cases Problem 1 A particular routine maybe called as an IRQ handler or as a regular subroutine In the latter case the system guarantees that IRQs would have been disabled prior to the routine being called The routine exploits this restriction to determine how it was called by examin...

Page 63: ...ng of the IRQ handler As the required state of all bits in the c field of the CPSR are known this can be most efficiently be achieved by writing an immediate value to CPSR_C for example MSR cpsr_c I_Bit OR irq_MODE IRQ should be disabled FIQ enabled ARM state IRQ mode This requires only the IRQ handler to be modified and FIQs may be re enabled more quickly than by using workaround 1 However this s...

Page 64: ... 0000 must be assigned Therefore writing 1 to any bit in Clear register will have one time effect in the destination register If the watchdog is enabled for interrupt on underflow or invalid feed sequence only then there is no way of clearing the interrupt The only way you could perform return from interrupt is by disabling the interrupt at the VIC using VICIntEnClr Example Assuming that UART0 and...

Page 65: ...ume 1 Chapter 5 VIC In case UART0 request has been made VICVectAddr will be identical to VICVectAddr0 while in case SPI0 request has been made value from VICVectAddr1 will be found here If neither UART0 nor SPI0 have generated IRQ request but UART1 and or I2C were the reason content of VICVectAddr will be identical to VICDefVectAddr ...

Page 66: ...CAP0 2 MAT0 2 P1 23 PIPESTAT2 P0 29 AD0 2 CAP0 3 MAT0 3 P0 10 CAP1 0 P0 30 AD0 3 EINT3 CAP0 0 P0 9 RXD1 PWM6 EINT3 P1 16 TRACEPKT0 P0 8 TXD1 PWM4 P0 31 UP_LED CONNECT P1 27 TDO V SS V REF P0 0 TXD0 PWM1 XTAL1 P1 31 TRST XTAL2 P0 1 RXD0 PWM3 EINT0 P1 28 TDI P0 2 SCL0 CAP0 0 V SSA V DD P0 23 V BUS P1 26 RTCK RESET V SS P1 29 TCK P0 3 SDA0 MAT0 0 EINT1 P0 20 MAT1 3 SSEL1 EINT3 P0 4 SCK0 CAP0 1 AD0 6 ...

Page 67: ...3 PIPESTAT2 P0 29 AD0 2 CAP0 3 MAT0 3 P0 10 CAP1 0 P0 30 AD0 3 EINT3 CAP0 0 P0 9 RXD1 PWM6 EINT3 P1 16 TRACEPKT0 P0 8 TXD1 PWM4 P0 31 UP_LED CONNECT P1 27 TDO V SS V REF P0 0 TXD0 PWM1 XTAL1 P1 31 TRST XTAL2 P0 1 RXD0 PWM3 EINT0 P1 28 TDI P0 2 SCL0 CAP0 0 V SSA V DD P0 23 V BUS P1 26 RTCK RESET V SS P1 29 TCK P0 3 SDA0 MAT0 0 EINT1 P0 20 MAT1 3 SSEL1 EINT3 P0 4 SCK0 CAP0 1 AD0 6 P0 19 MAT1 2 MOSI1...

Page 68: ...1 AD1 4 D P0 12 DSR1 MAT1 0 AD1 3 P1 17 TRACEPKT1 P0 11 CTS1 CAP1 1 SCL1 P0 28 AD0 1 CAP0 2 MAT0 2 P1 23 PIPESTAT2 P0 29 AD0 2 CAP0 3 MAT0 3 P0 10 RTS1 CAP1 0 AD1 2 P0 30 AD0 3 EINT3 CAP0 0 P0 9 RXD1 PWM6 EINT3 P1 16 TRACEPKT0 P0 8 TXD1 PWM4 AD1 1 P0 31 UP_LED CONNECT P1 27 TDO V SS V REF P0 0 TXD0 PWM1 XTAL1 P1 31 TRST XTAL2 P0 1 RXD0 PWM3 EINT0 P1 28 TDI P0 2 SCL0 CAP0 0 V SSA V DD P0 23 V BUS P...

Page 69: ...EINT1 26 3 I O P0 3 General purpose digital input output pin I O SDA0 I2C0 data input output Open drain output for I2C compliance O MAT0 0 Match output for Timer 0 channel 0 I EINT1 External interrupt 1 input P0 4 SCK0 CAP0 1 AD0 6 27 4 I O P0 4 General purpose digital input output pin I O SCK0 Serial clock for SPI0 SPI clock output from master or input to slave I CAP0 1 Capture input for Timer 0 ...

Page 70: ...utput for I2C compliance P0 12 DSR1 MAT1 0 AD1 3 38 4 I O P0 12 General purpose digital input output pin I DSR1 Data Set Ready input for UART1 Available in LPC2144 6 8 only O MAT1 0 Match output for Timer 1 channel 0 I AD1 3 A D converter input 3 This analog input is always connected to its pin Available in LPC2144 6 8 only P0 13 DTR1 MAT1 1 AD1 4 39 4 I O P0 13 General purpose digital input outpu...

Page 71: ...ut from SSP master or data input to SSP slave I CAP1 2 Capture input for Timer 1 channel 2 P0 20 MAT1 3 SSEL1 EINT3 55 2 I O P0 20 General purpose digital input output pin O MAT1 3 Match output for Timer 1 channel 3 I SSEL1 Slave Select for SSP Selects the SSP interface as a slave I EINT3 External interrupt 3 input P0 21 PWM5 AD1 6 CAP1 3 1 4 I O P0 21 General purpose digital input output pin O PW...

Page 72: ...te for this signal is LOW Used with the Soft Connect USB feature Note This pin MUST NOT be externally pulled LOW when RESET pin is LOW or the JTAG port will be disabled P1 0 to P1 31 I O Port 1 Port 1 is a 32 bit bi directional I O port with individual direction controls for each bit The operation of port 1 pins depends upon the pin function selected via the pin connect block Pins 0 through 15 of ...

Page 73: ...put output pin O TDO Test Data out for JTAG interface P1 28 TDI 60 6 I O P1 28 General purpose digital input output pin I TDI Test Data in for JTAG interface P1 29 TCK 56 6 I O P1 29 General purpose digital input output pin I TCK Test Clock for JTAG interface P1 30 TMS 52 6 I O P1 30 General purpose digital input output pin I TMS Test Mode Select for JTAG interface P1 31 TRST 20 6 I O P1 31 Genera...

Page 74: ...tolerant pad providing digital I O with TTL levels and hysteresis and 10 ns slew rate control and analog output function When configured as the DAC output digital section of the pad is disabled 6 5 V tolerant pad with built in pull up resistor providing digital I O functions with TTL levels and hysteresis and 10 ns slew rate control The pull up resistor s value typically ranges from 60 kΩ to 300 k...

Page 75: ...verter Regardless of the function that is selected for the port pin that also hosts the A D input this A D input can be read at any time and variations of the voltage level on this pin will be reflected in the A D readings However valid analog reading s can be obtained if and only if the function of an analog input is selected Only in this case proper interface circuit is active in between the phy...

Page 76: ...0 PINSEL0 address 0xE002 C000 bit description Bit Symbol Value Function Reset value 1 0 P0 0 00 GPIO Port 0 0 0 01 TXD UART0 10 PWM1 11 Reserved 3 2 P0 1 00 GPIO Port 0 1 0 01 RxD UART0 10 PWM3 11 EINT0 5 4 P0 2 00 GPIO Port 0 2 0 01 SCL0 I2C0 10 Capture 0 0 Timer 0 11 Reserved 7 6 P0 3 00 GPIO Port 0 3 0 01 SDA0 I2C0 10 Match 0 0 Timer 0 11 EINT1 9 8 P0 4 00 GPIO Port 0 4 0 01 SCK0 SPI0 10 Captur...

Page 77: ... GPIO Port 0 9 0 01 RxD UART1 10 PWM6 11 EINT3 21 20 P0 10 00 GPIO Port 0 10 0 01 Reserved 1 2 or RTS UART1 3 10 Capture 1 0 Timer 1 11 Reserved 1 2 or AD1 2 3 23 22 P0 11 00 GPIO Port 0 11 0 01 Reserved 1 2 or CTS UART1 3 10 Capture 1 1 Timer 1 11 SCL1 I2C1 25 24 P0 12 00 GPIO Port 0 12 0 01 Reserved 1 2 or DSR UART1 3 10 Match 1 0 Timer 1 11 Reserved 1 2 or AD1 3 3 27 26 P0 13 00 GPIO Port 0 13 ...

Page 78: ...mer 1 5 4 P0 18 00 GPIO Port 0 18 0 01 Capture 1 3 Timer 1 10 MISO1 SSP 11 Match 1 3 Timer 1 7 6 P0 19 00 GPIO Port 0 19 0 01 Match 1 2 Timer 1 10 MOSI1 SSP 11 Capture 1 2 Timer 1 9 8 P0 20 00 GPIO Port 0 20 0 01 Match 1 3 Timer 1 10 SSEL1 SSP 11 EINT3 11 10 P0 21 00 GPIO Port 0 21 0 01 PWM5 10 Reserved 1 2 or AD1 6 3 11 Capture 1 3 Timer 1 13 12 P0 22 00 GPIO Port 0 22 0 01 Reserved 1 2 or AD1 7 ...

Page 79: ...ify write operation when accessing PINSEL2 register Accidental write of 0 to bit 2 and or bit 3 results in loss of debug and or trace functionality Changing of either bit 4 or bit 5 from 1 to 0 may cause an incorrect code execution 21 20 P0 26 00 Reserved 0 01 Reserved 10 Reserved 11 Reserved 23 22 P0 27 00 Reserved 0 01 Reserved 10 Reserved 11 Reserved 25 24 P0 28 00 GPIO Port 0 28 0 01 AD0 1 10 ...

Page 80: ... for a specific derivative may be found in the appropriate data sheet Table 62 Pin function Select register 2 PINSEL2 0xE002 C014 bit description Bit Symbol Value Function Reset value 1 0 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA 2 GPIO DEBUG 0 Pins P1 36 26 are used as GPIO pins P1 26 RTCK 1 Pins P1 36 26 are used as a Debug...

Page 81: ...es is maintained with legacy registers appearing at the original addresses on the VPB bus 8 2 Applications General purpose I O Driving LEDs or other indicators Controlling off chip devices Sensing digital inputs 8 3 Pin description 8 4 Register description LPC2141 2 4 6 8 has two 32 bit General Purpose I O ports Total of 30 input output and a single output only pin out of 32 pins are available on ...

Page 82: ...ing text will refer to the legacy GPIO as the slow GPIO while GPIO equipped with the enhanced features will be referred as the fast GPIO 1 Reset value reflects the data stored in used bits only It does not include reserved bits content Table 65 GPIO register map legacy VPB accessible registers Generic Name Description Access Reset value 1 PORT0 Address Name PORT1 Address Name IOPIN GPIO Port Pin v...

Page 83: ... by zeros in this register R W 0x0000 0000 0x3FFF C010 FIO0MASK 0x3FFF C030 FIO1MASK FIOPIN Fast Port Pin value register using FIOMASK The current state of digital port pins can be read from this register regardless of pin direction or alternate function selection as long as pins is not configured as an input to ADC The value read is masked by ANDing with FIOMASK Writing to this register places co...

Page 84: ...on register FIO1DIR address 0x3FFF C020 bit description Bit Symbol Value Description Reset value 31 0 FP1xDIR 0 Fast GPIO Direction control bits Bit 0 in FIO1DIR controls P1 0 Bit 30 in FIO1DIR controls P1 30 Controlled pin is input 0x0000 0000 1 Controlled pin is output Table 71 Fast GPIO port 0 Direction control byte and half word accessible register description Register name Register length bit...

Page 85: ...ntrol register 2 Bit 0 in FIO1DIR2 register corresponds to P1 16 bit 7 to P1 23 0x00 FIO1DIR3 8 byte 0x3FFF C023 Fast GPIO Port 1 Direction control register 3 Bit 0 in FIO1DIR3 register corresponds to P1 24 bit 7 to P1 31 0x00 FIO1DIRL 16 half word 0x3FFF C020 Fast GPIO Port 1 Direction control Lower half word register Bit 0 in FIO1DIRL register corresponds to P1 0 bit 15 to P1 15 0x0000 FIO1DIRU ...

Page 86: ... Fast GPIO Port 0 Mask register 1 Bit 0 in FIO0MASK1 register corresponds to P0 8 bit 7 to P0 15 0x00 FIO0MASK2 8 byte 0x3FFF C012 Fast GPIO Port 0 Mask register 2 Bit 0 in FIO0MASK2 register corresponds to P0 16 bit 7 to P0 23 0x00 FIO0MASK3 8 byte 0x3FFF C013 Fast GPIO Port 0 Mask register 3 Bit 0 in FIO0MASK3 register corresponds to P0 24 bit 7 to P0 31 0x00 FIO0MASKL 16 half word 0x3FFF C001 F...

Page 87: ...C030 will be correlated to the current content of the Fast GPIO port pin value register Aside from the 32 bit long and word only accessible FIOPIN register every fast GPIO port can also be controlled via several byte and half word accessible registers listed in Table 81 and Table 82 too Next to providing the same functions as the FIOPIN register these additional registers allow easier and faster a...

Page 88: ...lue register 2 Bit 0 in FIO0PIN2 register corresponds to P0 16 bit 7 to P0 23 0x00 FIO0PIN3 8 byte 0x3FFF C017 Fast GPIO Port 0 Pin value register 3 Bit 0 in FIO0PIN3 register corresponds to P0 24 bit 7 to P0 31 0x00 FIO0PINL 16 half word 0x3FFF C014 Fast GPIO Port 0 Pin value Lower half word register Bit 0 in FIO0PINL register corresponds to P0 0 bit 15 to P0 15 0x0000 FIO0PINU 16 half word 0x3FF...

Page 89: ... Table 85 Fast GPIO port 0 output Set register FIO0SET address 0x3FFF C018 bit description Bit Symbol Description Reset value 31 0 FP0xSET Fast GPIO output value Set bits Bit 0 in FIO0SET corresponds to P0 0 Bit 31 in FIO0SET corresponds to P0 31 0x0000 0000 Table 86 Fast GPIO port 1 output Set register FIO1SET address 0x3FFF C038 bit description Bit Symbol Description Reset value 31 0 FP1xSET Fas...

Page 90: ...SET1 8 byte 0x3FFF C039 Fast GPIO Port 1 output Set register 1 Bit 0 in FIO1SET1 register corresponds to P1 8 bit 7 to P1 15 0x00 FIO1SET2 8 byte 0x3FFF C03A Fast GPIO Port 1 output Set register 2 Bit 0 in FIO1SET2 register corresponds to P1 16 bit 7 to P1 23 0x00 FIO1SET3 8 byte 0x3FFF C03B Fast GPIO Port 1 output Set register 3 Bit 0 in FIO1SET3 register corresponds to P1 24 bit 7 to P1 31 0x00 ...

Page 91: ...P0 16 bit 7 to P0 23 0x00 FIO0CLR3 8 byte 0x3FFF C01F Fast GPIO Port 0 output Clear register 3 Bit 0 in FIO0CLR3 register corresponds to P0 24 bit 7 to P0 31 0x00 FIO0CLRL 16 half word 0x3FFF C01C Fast GPIO Port 0 output Clear Lower half word register Bit 0 in FIO0CLRL register corresponds to P0 0 bit 15 to P0 15 0x0000 FIO0CLRU 16 half word 0x3FFF C01E Fast GPIO Port 0 output Clear Upper half wor...

Page 92: ...ister sets pin P0 7 back to low level 8 5 2 Example 2 an immediate output of 0s and 1s on a GPIO port Write access to port s IOSET followed by write to the IOCLR register results with pins outputting 0s being slightly later then pins outputting 1s There are systems that can tolerate this delay of a valid output but for some applications simultaneous output of a binary content mixed 0s and 1s withi...

Page 93: ... GPIO registers The enhanced features of the fast GPIO ports available on this microcontroller make GPIO pins more responsive to the code that has task of controlling them In particular software access to a GPIO pin is 3 5 times faster via the fast GPIO registers than it is when the legacy set of registers is used As a result of the access speed increase the maximum output frequency of the digital...

Page 94: ...es on the slow port str r5 r3 str r5 r4 str r5 r3 str r5 r4 loop b loop Figure 17 illustrates the code from above executed from the LPC2148 Flash memory The PLL generated FCCLK 60 MHz out of external FOSC 12 MHz The MAM was fully enabled with MEMCR 2 and MEMTIM 3 and VPBDIV 1 PCLK CCLK Fig 17 Illustration of the fast and slow GPIO access and output showing 3 5 x increase of the pin output frequenc...

Page 95: ... Mechanism that enables software and hardware flow control implementation 9 2 Pin description 9 3 Register description UART0 contains registers organized as shown in Table 96 The Divisor Latch Access Bit DLAB is contained in U0LCR 7 and enables access to the Divisor Latches UM10139 Chapter 9 Universal Asynchronous Receiver Transmitter 0 UART0 Rev 01 15 August 2005 User manual Table 95 UART0 pin de...

Page 96: ... RO NA 0xE000 C000 DLAB 0 U0THR Transmit Holding Register 8 bit Write Data WO NA 0xE000 C000 DLAB 0 U0DLL Divisor Latch LSB 8 bit Data R W 0x01 0xE000 C000 DLAB 1 U0DLM Divisor Latch MSB 8 bit Data R W 0x00 0xE000 C004 DLAB 1 U0IER Interrupt Enable Register En ABTO En ABEO R W 0x00 0xE000 C004 DLAB 0 En RX Lin St Int Enable THRE Int En RX Dat Av Int U0IIR Interrupt ID Reg ABTO Int ABEO Int RO 0x01...

Page 97: ...U0LCR must be zero in order to access the U0THR The U0THR is always Write Only 9 3 3 UART0 Divisor Latch Registers U0DLL 0xE000 C000 and U0DLM 0xE000 C004 when DLAB 1 The UART0 Divisor Latch is part of the UART0 Fractional Baud Rate Generator and holds the value used to divide the clock supplied by the fractional prescaler in order to produce the baud rate clock which must be 16x the desired baud ...

Page 98: ...d comply to the following conditions 1 0 MULVAL 15 2 0 DIVADDVAL 15 Table 99 UART0 Divisor Latch LSB register U0DLL address 0xE000 C000 when DLAB 1 bit description Bit Symbol Description Reset value 7 0 DLL The UART0 Divisor Latch LSB Register along with the U0DLM register determines the baud rate of the UART0 0x01 Table 100 UART0 Divisor Latch MSB register U0DLM address 0xE000 C004 when DLAB 1 bi...

Page 99: ... system with PCLK 20 MHz U0DL 130 U0DLM 0x00 and U0DLL 0x82 DIVADDVAL 0 and MULVAL 1 will enable UART0 with UART0baudrate 9615 bauds Example 2 Using UART0baudrate formula from above it can be determined that system with PCLK 20 MHz U0DL 93 U0DLM 0x00 and U0DLL 0x5D DIVADDVAL 2 and MULVAL 5 will enable UART0 with UART0baudrate 9600 bauds UART0baudrate PCLK 16 16 U0DLM U0DLL MulVal MulVal DivAddVal ...

Page 100: ...rates available when using 20 MHz peripheral clock PCLK 20 MHz Desired baudrate MULVAL 0 DIVADDVAL 0 Optimal MULVAL DIVADDVAL U0DLM U0DLL error 3 U0DLM U0DLL dec 1 Fractional pre scaler value MULDIV MULDIV DIVADDVAL error 3 hex 2 dec 1 Table 103 UART0 Interrupt Enable Register U0IER address 0xE000 C004 when DLAB 0 bit description Bit Symbol Value Description Reset value 0 RBR Interrupt Enable 0 U0...

Page 101: ... read from a reserved bit is not defined NA Table 103 UART0 Interrupt Enable Register U0IER address 0xE000 C004 when DLAB 0 bit description Bit Symbol Value Description Reset value Table 104 UART0 Interrupt Identification Register UOIIR address 0xE000 C008 read only bit description Bit Symbol Value Description Reset value 0 Interrupt Pending 0 Note that U0IIR 0 is active low The pending interrupt ...

Page 102: ...nd 1 to 5 CTI interrupts depending on the service routine resulting in the transfer of the remaining 5 characters 1 Values 0000 0011 0101 0111 1000 1001 1010 1011 1101 1110 1111 are reserved 2 For details see Section 9 3 10 UART0 Line Status Register U0LSR 0xE000 C014 Read Only 3 For details see Section 9 3 1 UART0 Receiver Buffer Register U0RBR 0xE000 C000 when DLAB 0 Read Only 4 For details see ...

Page 103: ...Reset value 0 FIFO Enable 0 UART0 FIFOs are disabled Must not be used in the application 0 1 Active high enable for both UART0 Rx and TX FIFOs and U0FCR 7 1 access This bit must be set for proper UART0 operation Any transition on this bit will automatically clear the UART0 FIFOs 1 RX FIFO Reset 0 No impact on either of UART0 FIFOs 0 1 Writing a logic 1 to U0FCR 1 will clear all bytes in UART0 Rx F...

Page 104: ...ble access to Divisor Latches Table 107 UART0 Line Control Register U0LCR address 0xE000 C00C bit description Bit Symbol Value Description Reset value Table 108 UART0 Line Status Register U0LSR address 0xE000 C014 read only bit description Bit Symbol Value Description Reset value 0 Receiver Data Ready RDR 0 U0LSR0 is set when the U0RBR holds an unread character and is cleared when the UART0 RBR FI...

Page 105: ...Once the break condition has been detected the receiver goes idle until RXD0 goes to marking state all 1 s An U0LSR read clears this status bit The time of break detection is dependent on U0FCR 0 Note The break interrupt is associated with the character at the top of the UART0 RBR FIFO 0 Break interrupt status is inactive 1 Break interrupt status is active 5 Transmitter Holding Register Empty THRE...

Page 106: ...falling edge of the start bit and the falling edge of the least significant bit In mode 1 the baud rate is measured between the falling edge and the subsequent rising edge of the UART0 Rx pin the length of the start bit Table 110 Auto baud Control Register U0ACR 0xE000 C020 bit description Bit Symbol Value Description Reset value 0 Start This bit is automatically cleared after auto baud completion...

Page 107: ...efore U0ACR register write The minimum and the maximum baudrates supported by UART0 are function of PCLK number of data bits stop bits and parity bits 3 9 3 14 UART0 Transmit Enable Register U0TER 0xE000 C030 LPC2141 2 4 6 8 s U0TER enables implementation of software flow control When TXEn 1 UART0 transmitter will keep sending data as long as they are available As soon as TXEn becomes 0 UART0 tran...

Page 108: ...ge on UART0 Rx pin triggers the beginning of the start bit The rate measuring counter will start counting PCLK cycles optionally pre scaled by the fractional baud rate generator 3 During the receipt of the start bit 16 pulses are generated on the RSR baud input with the frequency of the fractional baud rate pre scaled UART0 input clock guaranteeing the start bit is stored in the U0RSR 4 During the...

Page 109: ...valid characters via RXD0 After a valid character is assembled in the U0RSR it is passed to the UART0 RX Buffer Register FIFO to await access by the CPU or host via the generic host interface Fig 18 Autobaud Mode 0 and Mode 1 waveform a Mode 0 Start bit and LSB are used for auto baud b Mode 1 only Start bit is used for auto baud UART1 Rx Start bit LSB of A or a U1ACR Start rate counter UART1 Rx St...

Page 110: ...e serial output pin TXD0 The UART0 Baud Rate Generator block U0BRG generates the timing enables used by the UART0 TX block The U0BRG clock input source is the VPB clock PCLK The main clock is divided down per the divisor specified in the U0DLL and U0DLM registers This divided down clock is a 16x oversample clock NBAUDOUT The interrupt interface contains registers U0IER and U0IIR The interrupt inte...

Page 111: ...005 111 Philips Semiconductors UM10139 Volume 1 Chapter 9 UART0 Fig 19 UART0 block diagram VPB INTERFACE U0LCR U0RX DDIS U0LSR U0FCR U0BRG U0TX INTERRUPT PA 2 0 PSEL PSTB PWRITE PD 7 0 AR MR PCLK U0INTR U0SCR NTXRDY TXD0 NBAUDOUT RCLK NRXRDY RXD0 U0RBR U0RSR U0DLM U0DLL U0THR U0TSR U0IIR U0IER ...

Page 112: ...Data Carrier Detect Active low signal indicates if the external modem has established a communication link with the UART1 and data may be exchanged In normal operation of the modem interface U1MCR 4 0 the complement value of this signal is stored in U1MSR 7 State change information is stored in U1MSR3 and is a source for a priority level 4 interrupt if enabled U1IER 3 1 DSR1 1 Input Data Set Ready...

Page 113: ...anual Rev 01 15 August 2005 113 Philips Semiconductors UM10139 Volume 1 Chapter 10 UART1 10 3 Register description UART1 contains registers organized as shown in Table 76 The Divisor Latch Access Bit DLAB is contained in U1LCR 7 and enables access to the Divisor Latches ...

Page 114: ... NA 0xE001 0000 DLAB 0 U1DLL Divisor Latch LSB 8 bit Data R W 0x01 0xE001 0000 DLAB 1 U1DLM Divisor Latch MSB 8 bit Data R W 0x00 0xE001 0004 DLAB 1 U1IER Interrupt Enable Register En ABTO En ABEO R W 0x00 0xE001 0004 DLAB 0 En CTS Int 2 E Modem St Int 2 En RX Lin St Int Enable THRE Int En RX Dat Av Int U1IIR Interrupt ID Reg ABTO Int ABEO Int RO 0x01 0xE001 0008 FIFOs Enabled IIR3 IIR2 IIR1 IIR0 ...

Page 115: ...R must be zero in order to access the U1THR The U1THR is always Write Only 10 3 3 UART1 Divisor Latch Registers 0 and 1 U1DLL 0xE001 0000 and U1DLM 0xE001 0004 when DLAB 1 The UART1 Divisor Latch is part of the UART1 Fractional Baud Rate Generator and holds the value used to divide the clock supplied by the fractional prescaler in order to produce the baud rate clock which must be 16x the desired ...

Page 116: ... comply to the following conditions 1 0 MULVAL 15 2 0 DIVADDVAL 15 Table 116 UART1 Divisor Latch LSB register U1DLL address 0xE001 0000 when DLAB 1 bit description Bit Symbol Description Reset value 7 0 DLLSB The UART1 Divisor Latch LSB Register along with the U1DLM register determines the baud rate of the UART1 0x01 Table 117 UART1 Divisor Latch MSB register U1DLM address 0xE001 0004 when DLAB 1 ...

Page 117: ...t system with PCLK 20 MHz U1DL 130 U1DLM 0x00 and U1DLL 0x82 DIVADDVAL 0 and MULVAL 1 will enable UART1 with UART1baudrate 9615 bauds Example 2 Using UART1baudrate formula from above it can be determined that system with PCLK 20 MHz U1DL 93 U1DLM 0x00 and U1DLL 0x5D DIVADDVAL 2 and MULVAL 5 will enable UART1 with UART1baudrate 9600 bauds UART1baudrate PCLK 16 16 U1DLM U1DLL MulVal MulVal DivAddVal...

Page 118: ...peripheral clock PCLK 20 MHz Desired baudrate MULVAL 0 DIVADDVAL 0 Optimal MULVAL DIVADDVAL U1DLM U1DLL error 3 U1DLM U1DLL dec 1 Fractional pre scaler value MULDIV MULDIV DIVADDVAL error 3 hex 2 dec 1 Table 120 UART1 Interrupt Enable Register U1IER address 0xE001 0004 when DLAB 0 bit description Bit Symbol Value Description Reset value 0 RBR Interrupt Enable 0 U1IER 0 enables the Receive Data Ava...

Page 119: ...l transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the U1IER 3 bit in the U1IER register In auto CTS mode a transition on the CTS1 bit will trigger an interrupt only if both the U1IER 3 and U1IER 7 bits are set 0 0 Disable the CTS interrupt 1 Enable the CTS interrupt 8 ABTOIntEn 0 U1IER8 enables the auto baud time out interrupt Disable Auto baud ...

Page 120: ...er and no UART1 Rx FIFO activity has occurred in 3 5 to 4 5 character times Any UART1 Rx FIFO activity read or write of UART1 RSR will clear the interrupt This interrupt is intended to flush the UART1 RBR after a message has been received that is not a multiple of the trigger level size For example if a peripheral wished to send a 105 character message and the trigger level was 10 characters the C...

Page 121: ...ART1 THR FIFO has held two or more characters at one time and currently the U1THR is empty The THRE interrupt is reset when a U1THR write occurs or a read of the U1IIR occurs and the THRE is the highest interrupt U1IIR 3 1 001 The modem interrupt U1IIR 3 1 000 is available in LPC2144 6 8 only It is the lowest priority interrupt and is activated whenever there is any state change on modem inputs pi...

Page 122: ...bytes in UART1 TX FIFO and reset the pointer logic This bit is self clearing 5 3 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA 7 6 RX Trigger Level 00 These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated 0 trigger level 0 1 character or 0x01 01 trigger level 1 4 charact...

Page 123: ...ack mode is active 0 1 RTS Control Source for modem output pin RTS This bit reads as 0 when modem loopback mode is active 0 3 2 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA 4 Loopback Mode Select 0 The modem loopback mode provides a mechanism to perform diagnostic loopback testing Serial data from the transmitter is connected in...

Page 124: ...be copied in the RTSen bit of the UART1 As long as auto RTS is enabled the value if the RTSen bit is read only for software Example Suppose the UART1 operating in type 550 has trigger level in U1FCR set to 0x2 then if auto RTS is enabled the UART1 will deassert the RTS1 output as soon as the receive FIFO contains 8 bytes Table 123 on page 122 The RTS1 output will be reasserted as soon as the recei...

Page 125: ...sumes and a start bit is sent followed by the data bits of the next character 10 3 11 UART1 Line Status Register U1LSR 0xE001 0014 Read Only The U1LSR is a read only register that provides status information on the UART1 TX and RX blocks Table 126 Modem status interrupt generation Enable Modem Status Interrupt U1IER 3 CTSen U1MCR 7 CTS Interrupt Enable U1IER 7 Delta CTS U1MSR 0 Delta DCD or Traili...

Page 126: ... is associated with the character at the top of the UART1 RBR FIFO 0 Framing error status is inactive 1 Framing error status is active 4 Break Interrupt BI 0 When RXD1 is held in the spacing state all 0 s for one full character transmission start data parity stop a break interrupt occurs Once the break condition has been detected the receiver goes idle until RXD1 goes to marking state all 1 s An U...

Page 127: ...y bit description Bit Symbol Value Description Reset value 0 Delta CTS 0 Set upon state change of input CTS Cleared on an U1MSR read 0 No change detected on modem input CTS 1 State change detected on modem input CTS 1 Delta DSR 0 Set upon state change of input DSR Cleared on an U1MSR read 0 No change detected on modem input DSR 1 State change detected on modem input DSR 2 Trailing Edge RI 0 Set up...

Page 128: ...urement counter overflows If this bit is set the rate measurement will restart at the next falling edge of the UART1 Rx pin The auto baud function can generate two interrupts The U1IIR ABTOInt interrupt will get set if the interrupt is enabled U1IER ABToIntEn is set and the auto baud rate measurement counter overflows Table 130 Auto baud Control Register U1ACR 0xE001 0020 bit description Bit Symbo...

Page 129: ... Rx pin sensed start bit and the LSB of the expected character are delimited by two falling edges When the U1ACR Start bit is set the auto baud protocol will execute the following phases 1 On U1ACR Start bit setting the baud rate measurement counter is reset and the UART1 U1RSR is reset The U1RSR baud rate is switch to the highest rate 2 A falling edge on UART1 Rx pin triggers the beginning of the...

Page 130: ... as TXEn becomes 0 UART1 transmission will stop Table 131 describes how to use TXEn bit in order to achieve software flow control Fig 22 Autobaud Mode 0 and Mode 1 waveform a Mode 0 Start bit and LSB are used for auto baud b Mode 1 only Start bit is used for auto baud UART1 Rx Start bit LSB of A or a U1ACR Start rate counter UART1 Rx Start bit LSB of A or a rate counter start bit0 bit1 bit2 bit3 b...

Page 131: ...ontains registers U1MCR and U1MSR This interface is responsible for handshaking between a modem peripheral and the UART1 The interrupt interface contains registers U1IER and U1IIR The interrupt interface receives several one clock wide enables from the U1TX and U1RX blocks Status information from the U1TX and U1RX is stored in the U1LSR Control information for the U1TX and U1RX is stored in the U1...

Page 132: ...onductors UM10139 Volume 1 Chapter 10 UART1 Fig 23 UART1 block diagram VPB INTERFACE U1LCR U1RX DDIS U1LSR U1FCR U1BRG U1TX INTERRUPT PA 2 0 PSEL PSTB PWRITE PD 7 0 AR MR PCLK U1INTR U1SCR NTXRDY TXD1 NBAUDOUT RCLK NRXRDY RXD1 U1RBR U1RSR U1DLM U1DLL U1THR U1TSR U1IIR U1IER MODEM RTS U1MCR U1MSR DTR DCD RI DSR CTS ...

Page 133: ...s The slave returns an acknowledge bit after each received byte Data transfer from a slave transmitter to a master receiver The first byte the slave address is transmitted by the master The slave then returns an acknowledge bit Next follows the data bytes transmitted by the slave to the master The master returns an acknowledge bit after all received bytes other than the last byte At the end of the...

Page 134: ...ted If the processor wishes to become the bus master the hardware waits until the bus is free before the master mode is entered so that a possible slave operation is not interrupted If bus arbitration is lost in the master mode the I2C block switches to the slave mode immediately and can detect its own slave address in the same serial transfer 11 5 1 Master Transmitter mode In this mode data is tr...

Page 135: ...ll load the slave address and Write bit to the I2DAT register and then clear the SI bit SI is cleared by writing a 1 to the SIC bit in the I2CONCLR register When the slave address and R W bit have been transmitted and an acknowledgment bit has been received the SI bit is set again and the possible status codes now are 0x18 0x20 or 0x38 for the master mode or 0x68 0x78 or 0xB0 if the slave mode was...

Page 136: ...ss register I2ADR and write the I2C Control Set register I2CONSET as shown in Table 134 I2EN must be set to 1 to enable the I2C function AA bit must be set to 1 to acknowledge its own slave address or the general call address The STA STO and SI bits are set to 0 Fig 26 Format of Master Receive mode Fig 27 A Master Receiver switches to Master Transmitter after sending Repeated START DATA A Acknowle...

Page 137: ...ing and end of a serial transfer In a given application I2C may operate as a master and as a slave In the slave mode the I2C hardware looks for its own slave address and the general call address If one of these addresses is detected an interrupt is requested When the microcontrollers wishes to become the bus master the hardware waits until the bus is free before the master mode is entered so that ...

Page 138: ...Implementation and operation Figure 30 shows how the on chip I2C bus interface is implemented and the following text describes the individual blocks 11 6 1 Input filters and output stages Input signals are synchronized with the internal clock and spikes shorter than three clocks are filtered out The output for I2C is a special pad designed to conform to the I2C specification ...

Page 139: ...rial interface block diagram APB BUS STATUS REGISTER CONTROL REGISTER SCL DUTY CYCLE REGISTERS ADDRESS REGISTER COMPARATOR SHIFT REGISTER 8 8 ACK I2ADR I2DAT 8 16 BIT COUNTER ARBITRATION SYNC LOGIC SERIAL CLOCK GENERATOR TIMING CONTROL LOGIC STATUS DECODER Staus bus I2CONSET I2SCLL I2SCLH I2CONCLR Interrupt PCLK INPUT FILTER OUTPUT STAGE SCL INPUT FILTER OUTPUT STAGE SDA I2STAT ...

Page 140: ...ster transmitter to slave receiver is made with the correct data in I2DAT 11 6 5 Arbitration and synchronization logic In the master transmitter mode the arbitration logic checks that every transmitted logic 1 actually appears as a logic 1 on the I2C bus If another device on the bus overrules a logic 1 and pulls the SDA line low arbitration is lost and the I2C block immediately changes from master...

Page 141: ...d duty cycle is programmable via the I2C Clock Control Registers See the description of the I2CSCLL and I2CSCLH registers for details The output clock pulses have a duty cycle as programmed unless the bus is synchronizing with other SCL clock sources as described above 11 6 7 Timing and control The timing and control logic generates the timing and control signals for serial byte handling This logi...

Page 142: ...2C register map Name Description Access Reset value 1 I2C0 Address and Name I2C1 Address and Name I2CONSET I2C Control Set Register When a one is written to a bit of this register the corresponding bit in the I2C control register is set Writing a zero has no effect on the corresponding bit in the I2C control register R W 0x00 0xE001 C000 I2C0CONSET 0xE005 C000 I2C1CONSET I2STAT I2C Status Register...

Page 143: ...us and generates a START condition if the bus is free If the bus is not free it waits for a STOP condition which will free the bus and generates a START condition after a delay of a half clock period of the internal clock generator If the I2C interface is already in master mode and data has been transmitted or received it transmits a repeated START condition STA may be set at any time including wh...

Page 144: ...he following situations 1 The address in the Slave Address Register has been received 2 The general call address has been received while the general call bit GC in I2ADR is set 3 A data byte has been received while the I2C is in the master receiver mode 4 A data byte has been received while the I2C is in the addressed slave receiver mode The AA bit can be cleared by writing 1 to the AAC bit in the...

Page 145: ...us codes refer to tables from Table 148 to Table 151 11 7 4 I2C Data register I2DAT I2C0 I2C0DAT 0xE001 C008 and I2C1 I2C1DAT 0xE005 C008 This register contains the data to be transmitted or the data just received The CPU can read and write to this register only while it is not in the process of shifting a byte when the SI bit is set Data in I2DAT remains stable as long as the SI bit is set Data i...

Page 146: ... the peripheral bus VPB 7 The values for I2SCLL and I2SCLH should not necessarily be the same Software can set different duty cycles on SCL by setting these two registers For example the I2C bus specification defines the SCL low time and high time at different values for a 400 kHz I2C rate The value of the register must ensure that the data rate is in the I2C data rate range of 0 through 400 kHz E...

Page 147: ...cal since the serial transfer is suspended until the serial interrupt flag is cleared by software When a serial interrupt routine is entered the status code in I2STAT is used to branch to the appropriate service routine For each status code the required software action and details of the following serial transfer are given in tables from Table 148 to Table 152 Table 143 Example I2C clock rates I2S...

Page 148: ...n bit have been transmitted and an acknowledgment bit has been received the serial interrupt flag SI is set again and a number of status codes in I2STAT are possible There are 0x18 0x20 or 0x38 for the master mode and also 0x68 0x78 or 0xB0 if the slave mode was enabled AA logic 1 The appropriate action to be taken for each of these status codes is detailed in Table 148 After a repeated start cond...

Page 149: ...ection bit which must be 0 W for the I2C block to operate in the slave receiver mode After its own slave address and the W bit have been received the serial interrupt flag SI is set and a valid status code can be read from I2STAT This status code is used to vector to a state service routine The appropriate action to be taken for each of these status codes is detailed in Table 104 The slave receive...

Page 150: ...Other Master continues A Other Master continues 20H 08H 18H 28H 30H 10H 68H 78H B0H 38H 38H Arbitration lost in Slave Address or Data byte Not Acknowledge received after a Data byte Not Acknowledge received after the Slave Address Next transfer started with a Repeated Start condition Arbitration lost and addressed as Slave Successful transmission to a Slave Receiver From Master to Slave From Slave...

Page 151: ...inues Other Master continues A Other Master continues 48H 08H 40H 58H 10H 68H 78H B0H 38H 38H Arbitration lost in Slave Address or Acknowledge bit Not Acknowledge received after the Slave Address Next transfer started with a Repeated Start condition Arbitration lost and addressed as Slave Successful transmission to a Slave Transmitter From Master to Slave From Slave to Master Any number of data by...

Page 152: ...t as Master and addressed as Slave Last data byte received is Not Acknowledged Arbitration lost as Master and addressed as Slave by General Call Reception of the own Slave Address and one or more Data bytes all are acknowledged From Master to Slave From Slave to Master Any number of data bytes and their associated Acknowledge bits n This number contained in I2STA corresponds to a defined state of ...

Page 153: ...ck is in the master mode see state 0xB0 If the AA bit is reset during a transfer the I2C block will transmit the last byte of the transfer and enter state 0xC0 or 0xC8 The I2C block is switched to the not addressed slave mode and will ignore the master receiver if it continues the transfer Thus the master receiver receives all 1s as serial data While AA is reset the I2C block does not respond to i...

Page 154: ... be transmitted ACK bit will be received No I2DAT action or 1 0 0 X Repeated START will be transmitted No I2DAT action or 0 1 0 X STOP condition will be transmitted STO flag will be reset No I2DAT action 1 1 0 X STOP condition followed by a START condition will be transmitted STO flag will be reset 0x28 Data byte in I2DAT has been transmitted ACK has been received Load data byte or 0 0 0 X Data by...

Page 155: ... R has been transmitted ACK has been received No I2DAT action or 0 0 0 0 Data byte will be received NOT ACK bit will be returned No I2DAT action 0 0 0 1 Data byte will be received ACK bit will be returned 0x48 SLA R has been transmitted NOT ACK has been received No I2DAT action or 1 0 0 X Repeated START condition will be transmitted No I2DAT action or 0 1 0 X STOP condition will be transmitted STO...

Page 156: ... 0 Data byte will be received and NOT ACK will be returned No I2DAT action X 0 0 1 Data byte will be received and ACK will be returned 0x80 Previously addressed with own SLV address DATA has been received ACK has been returned Read data byte or X 0 0 0 Data byte will be received and NOT ACK will be returned Read data byte X 0 0 1 Data byte will be received and ACK will be returned 0x88 Previously ...

Page 157: ...f I2ADR 0 logic 1 A START condition will be transmitted when the bus becomes free 0xA0 A STOP condition or repeated START condition has been received while still addressed as SLV REC or SLV TRX No STDAT action or 0 0 0 0 Switched to not addressed SLV mode no recognition of own SLA or General call address No STDAT action or 0 0 0 1 Switched to not addressed SLV mode Own SLA will be recognized Gener...

Page 158: ...ion or 0 0 0 0 Switched to not addressed SLV mode no recognition of own SLA or General call address No I2DAT action or 0 0 0 1 Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if I2ADR 0 logic 1 No I2DAT action or 1 0 0 0 Switched to not addressed SLV mode no recognition of own SLA or General call address A START condition will be transmitted wh...

Page 159: ... 11 8 7 I2STAT 0x00 This status code indicates that a bus error has occurred during an I2C serial transfer A bus error is caused when a START or STOP condition occurs at an illegal position in the format frame Examples of such illegal positions are during the serial transfer of an address byte a data byte or an acknowledge bit A bus error may also be caused when external interference disturbs the ...

Page 160: ...ster receiver modes see Figure 31 Loss of arbitration is indicated by the following states in I2STAT 0x38 0x68 0x78 and 0xB0 see Figure 33 and Figure 34 If the STA flag in I2CON is set by the routines which service these states then if the bus is free again a START condition state 0x08 is transmitted without intervention by the CPU and a retry of the total serial transfer can commence 11 8 11 Forc...

Page 161: ...itional clock pulses when the STA flag is set but no START condition can be generated because the SDA line is pulled LOW while the I2C bus is considered free The I2C hardware attempts to generate a START condition after every two additional clock pulses on the SCL line When the SDA line is eventually released a normal START condition is transmitted state 0x08 is entered and the serial transfer con...

Page 162: ...eset I2C Interrupt Service Fig 37 Simultaneous repeated START conditions from two masters Fig 38 Forced access to a busy I2C bus Fig 39 Recovering from a bus obstruction caused by a low level on SDA SLA A W SLA S 18H 08H A DATA 28H 08H OTHER MASTER CONTINUES Other Master sends Repeated Start earlier S Retry S P SDA Line SCL Line STA Flag STO Flag Time limit Start condition SDA Line SCL Line 1 2 1 ...

Page 163: ...tate information 11 8 16 I2C interrupt service When the I2C interrupt is entered I2STAT contains a status code which identifies one of the 26 state services to be executed 11 8 17 The State service routines Each state routine is part of the I2C interrupt routine and handles one of the 26 states 11 8 18 Adapting State services to an application The state service examples show the typical actions th...

Page 164: ... STA bit 4 Set up the Master Receive buffer 5 Initialize the Master data counter to match the length of the message to be received 6 Exit 11 9 4 I2C interrupt routine Determine the I2C state and which state routine will be used to handle it 1 Read the I2C status from I2STA 2 Use the status value to branch to one of 26 possible state routines 11 9 5 Non mode specific States 11 9 6 State 0x00 Bus Er...

Page 165: ...Transmitter States 11 9 11 State 0x18 Previous state was State 8 or State 10 Slave Address Write has been transmitted ACK has been received The first data byte will be transmitted an ACK bit will be received 1 Load I2DAT with first data byte from Master Transmit buffer 2 Write 0x04 to I2CONSET to set the AA bit 3 Write 0x08 to I2CONCLR to clear the SI flag 4 Increment Master Transmit buffer pointe...

Page 166: ... 15 State 0x38 Arbitration has been lost during Slave Address Write or data The bus has been released and not addressed Slave mode is entered A new Start condition will be transmitted when the bus is free again 1 Write 0x24 to I2CONSET to set the STA and AA bits 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Exit 11 9 16 Master Receive States 11 9 17 State 0x40 Previous state was State 08 or Stat...

Page 167: ...turned Data will be read from I2DAT A Stop condition will be transmitted 1 Read data byte from I2DAT into Master Receive buffer 2 Write 0x14 to I2CONSET to set the STO and AA bits 3 Write 0x08 to I2CONCLR to clear the SI flag 4 Exit 11 9 21 Slave Receiver States 11 9 22 State 0x60 Own Slave Address Write has been received ACK has been returned Data will be received and ACK returned 1 Write 0x04 to...

Page 168: ...NSET to set the STA and AA bits 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Set up Slave Receive mode data buffer 4 Initialize Slave data counter 5 Exit 11 9 26 State 0x80 Previously addressed with own Slave Address Data has been received and ACK has been returned Additional data will be read 1 Read data byte from I2DAT into the Slave Receive buffer 2 Decrement the Slave data counter skip to s...

Page 169: ...A Stop condition or repeated Start has been received while still addressed as a Slave Data will not be saved Not addressed Slave mode is entered 1 Write 0x04 to I2CONSET to set the AA bit 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Exit 11 9 31 Slave Transmitter States 11 9 32 State 0xA8 Own Slave Address Read has been received ACK has been returned Data will be transmitted ACK bit will be rec...

Page 170: ...eived 1 Load I2DAT from Slave Transmit buffer with data byte 2 Write 0x04 to I2CONSET to set the AA bit 3 Write 0x08 to I2CONCLR to clear the SI flag 4 Increment Slave Transmit buffer pointer 5 Exit 11 9 35 State 0xC0 Data has been transmitted NOT ACK has been received Not addressed Slave mode is entered 1 Write 0x04 to I2CONSET to set the AA bit 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Exi...

Page 171: ...of data to the master 12 2 2 SPI data transfers Figure 40 is a timing diagram that illustrates the four different data transfer formats that are available with the SPI This timing diagram illustrates a single 8 bit data transfer The first thing you should notice in this timing diagram is that it is divided into three horizontal parts The first part describes the SCK and SSEL signals The second par...

Page 172: ...e clock and begin the transfer The transfer ends when the last clock cycle of the transfer is complete Fig 40 SPI data transfer format CPHA 0 and CPHA 1 MISO CPHA 1 MOSI CPHA 1 Cycle CPHA 1 CPHA 1 MISO CPHA 0 MOSI CPHA 0 Cycle CPHA 0 CPHA 0 SSEL SCK CPOL 1 SCK CPOL 0 1 2 3 8 7 6 5 4 BIT 1 BIT 2 BIT 3 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 1 BIT 2 BIT 3 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 1 2 3 8 7 6 5 4 BIT ...

Page 173: ...ransmit case There is no buffer between the data register and the internal shift register A write to the data register goes directly into the internal shift register Therefore data should only be written to this register when a transmit is not currently in progress Read data is buffered When a transfer is complete the receive data is transferred to a single byte data buffer where it is later read ...

Page 174: ...is required to transmit Note that a read or write of the SPI data register is required in order to clear the SPIF status bit Therefore at least one of the optional reads or writes of the SPI data register must take place in order to clear the SPIF status bit 12 2 6 Exception conditions 12 2 7 Read Overrun A read overrun occurs when the SPI block internal read buffer contains data that has not been...

Page 175: ... either in its inactive state or tri stated SSEL0 Input Slave Select The SPI slave select signal is an active low signal that indicates which slave is currently selected to participate in a data transfer Each slave has its own unique slave select signal input The SSEL must be low before data transactions begin and normally stays low for the duration of the transaction If the SSEL signal goes high ...

Page 176: ... master s SCK0 R W 0x00 0xE002 000C S0SPINT SPI Interrupt Flag This register contains the interrupt flag for the SPI interface R W 0x00 0xE002 001C Table 156 SPI Control Register S0SPCR address 0xE002 0000 bit description Bit Symbol Value Description Reset value 1 0 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA 2 BitEnable 0 The ...

Page 177: ...its per transfer 1010 10 bits per transfer 1011 11 bits per transfer 1100 12 bits per transfer 1101 13 bits per transfer 1110 14 bits per transfer 1111 15 bits per transfer 0000 16 bits per transfer 15 12 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA Table 156 SPI Control Register S0SPCR address 0xE002 0000 bit description Bit Sy...

Page 178: ...ister contains the interrupt flag for the SPI0 interface 5 ROVR Read overrun When 1 this bit indicates that a read overrun has occurred This bit is cleared by reading this register 0 6 WCOL Write collision When 1 this bit indicates that a write collision has occurred This bit is cleared by reading this register then accessing the SPI data register 0 7 SPIF SPI transfer complete flag When 1 this bi...

Page 179: ...an interrupt Cleared by writing a 1 to this bit Note this bit will be set once when SPIE 1 and at least one of SPIF and WCOL bits is 1 However only when the SPI Interrupt bit is set and SPI0 Interrupt is enabled in the VIC SPI based interrupt can be processed by interrupt handling software 0 7 1 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not...

Page 180: ...inciple full duplex with frames of 4 to 16 bits of data flowing from the master to the slave and from the slave to the master In practice it is often the case that only one of these data flows carries meaningful data UM10139 Chapter 13 SSP Controller SPI1 Rev 01 15 August 2005 User manual Table 161 SSP pin descriptions Pin Name Type Interface pin name function Pin Description SPI SSI Microwire SCK...

Page 181: ...ct signal from the Master can be connected directly to the slave s corresponding input When there is more than one slave on the bus further qualification of their Frame Select Slave Select inputs will typically be necessary to prevent more than one slave from responding to a transfer MISO1 I O MISO DR M DX S SI M SO S Master In Slave Out The MISO signal transfers serial data from the slave to the ...

Page 182: ...the falling edge of each CLK The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of CLK after the LSB has been latched 13 3 2 SPI frame format The SPI interface is a four wire interface where the SSEL signal behaves as a slave select The main feature of the SPI format is that the inactive state and phase of the SCK signal are programmable through t...

Page 183: ...l is forced LOW SSEL is forced HIGH The transmit MOSI MISO pad is in high impedance If the SSP is enabled and there is valid data within the transmit FIFO the start of transmission is signified by the SSEL master signal being driven LOW This causes slave data to be enabled onto the MISO input line of the master Master s MOSI is enabled One half SCK period later valid master data is transferred to ...

Page 184: ... with CPOL 0 CPHA 1 is shown in Figure 44 which covers both single and continuous transfers In this configuration during idle periods The CLK signal is forced LOW SSEL is forced HIGH The transmit MOSI MISO pad is in high impedance If the SSP is enabled and there is valid data within the transmit FIFO the start of transmission is signified by the SSEL master signal being driven LOW Master s MOSI pi...

Page 185: ...lock pin becomes LOW after one further half SCK period This means that data is captured on the falling edges and be propagated on the rising edges of the SCK signal In the case of a single word transmission after all bits of the data word are transferred the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured However in the case of continuous back to ba...

Page 186: ...ave data are enabled onto their respective transmission lines At the same time the SCK is enabled with a falling edge transition Data is then captured on the rising edges and propagated on the falling edges of the SCK signal After all bits have been transferred in the case of a single word transmission the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been capt...

Page 187: ...or the duration of the frame transmission The SI pin remains tristated during this transmission The off chip serial slave device latches each control bit into its serial shifter on the rising edge of each SK After the last bit is latched by the slave device the control byte is decoded during a one clock wait state and the slave responds by transmitting data back to the SSP Each bit is driven onto ...

Page 188: ...rates these setup and hold time requirements With respect to the SK rising edge on which the first bit of receive data is to be sampled by the SSP slave CS must have a setup of at least two times the period of SK on which the SSP operates With respect to the SK rising edge previous to this edge CS must have a hold of at least one SK period 13 4 Register description The SSP contains 9 registers as ...

Page 189: ...0x03 0xE006 800C SSPCPSR Clock Prescale Register R W 0x00 0xE006 8010 SSPIMSC Interrupt Mask Set and Clear Register R W 0x00 0xE006 8014 SSPRIS Raw Interrupt Status Register R W 0x04 0xE006 8018 SSPMIS Masked Interrupt Status Register RO 0x00 0xE006 801C SSPICR SSPICR Interrupt Clear Register WO NA 0xE006 8020 Table 163 SSP Control Register 0 SSPCR0 address 0xE006 8000 bit description Bit Symbol V...

Page 190: ... 1 0x00 Table 163 SSP Control Register 0 SSPCR0 address 0xE006 8000 bit description Bit Symbol Value Description Reset value Table 164 SSP Control Register 1 SSPCR1 address 0xE006 8004 bit description Bit Symbol Value Description Reset value 0 LBM 0 Loop Back Mode During normal operation 0 1 Serial input is taken from the serial output MOSI or MISO rather than the serial input pin MISO or MOSI res...

Page 191: ... length is less than 16 bits software must right justify the data written to this register Read software can read data from this register whenever the RNE bit in the Status register is 1 indicating that the Rx FIFO is not empty When software reads this register the SSP controller returns data from the least recent frame in the Rx FIFO If the data length is less than 16 bits the data is right justi...

Page 192: ...e Rx FIFO is full and another frame is completely received The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs 0 1 RTIM Software should set this bit to enable interrupt when a Receive Timeout condition occurs A Receive Timeout occurs when the Rx FIFO is not empty and no new data has been received nor has data been read from the FIFO for 32 bit t...

Page 193: ...ss 0xE006 801C bit description Bit Symbol Description Reset value 0 RORMIS This bit is 1 if another frame was completely received while the RxFIFO was full and this interrupt is enabled 0 1 RTMIS This bit is 1 when there is a Receive Timeout condition and this interrupt is enabled Note that a Receive Timeout can be negated if further data is received 0 2 RXMIS This bit is 1 if the Rx FIFO is at le...

Page 194: ...e controller enables 12 Mb s data exchange with a USB host controller It consists of register interface serial interface engine endpoint buffer memory and DMA controller The serial interface engine decodes the USB data stream and writes data to the appropriate end point buffer memory The status of a completed USB transfer or error condition is indicated via status registers An interrupt is also ge...

Page 195: ...plex DMA channel serves all endpoints LPC2146 8 only Allows dynamic switching between CPU controlled and DMA modes available on LPC2146 8 only Double buffer implementation for Bulk Isochronous endpoints 14 3 Fixed Endpoint Configuration SRAM Synchronous RAM UDCA USB Device Communication Area USB Universal Serial Bus Table 172 USB related acronyms abbreviations and definitions used in this chapter ...

Page 196: ...21 Interrupt In 1 to 64 No 11 22 Bulk Out 8 16 32 64 Yes 11 23 Bulk In 8 16 32 64 Yes 12 24 Isochronous Out 1 to 1023 Yes 12 25 Isochronous In 1 to 1023 Yes 13 26 Interrupt Out 1 to 64 No 13 27 Interrupt In 1 to 64 No 14 28 Bulk Out 8 16 32 64 Yes 14 29 Bulk In 8 16 32 64 Yes 15 30 Bulk Out 8 16 32 64 Yes 15 31 Bulk In 8 16 32 64 Yes Table 173 Pre Fixed Endpoint Configuration Logical endpoint Phys...

Page 197: ...o the data transfer has to be synchronized to the USB frame rather than packet arrival So for every 1 ms there will be an interrupt to the system The data transfer follows the little endian format The first byte received from the USB bus will be available in the least significant byte of the receive data register 14 5 2 Data Flow from Device to the Host For data transfer from an endpoint to the ho...

Page 198: ...channel DMA acts as a AHB master on the bus The endpoint 0 of USB default control endpoint will receive the setup packet It will not be efficient to transfer this data to the USB RAM since the CPU has to decode this command and respond back to the host So this transfer will happen in the slave mode only For each Isochronous endpoint one packet transfer happens every frame Hence the DMA transfer ha...

Page 199: ... R W 0x0000 0008 0xE009 004C USB transfer registers USBRxData USB Receive Data RO 0x0000 0000 0xE009 0018 USBRxPLen USB Receive Packet Length RO 0x0000 0000 0xE009 0020 USBTxData USB Transmit Data WO 0x0000 0000 0xE009 001C USBTxPLen USB Transmit Packet Length WO 0x0000 0000 0xE009 0024 USBCtrl USB Control R W 0x0000 0000 0xE009 0028 Command registers USBCmdCode USB Command Code WO 0x0000 0000 0xE...

Page 200: ... status registers The usb_int_req_dma is raised when an end_of_transfer or a system error has occurred DMA data transfer is not dependent on this interrupt The three interrupt output lines are ORed together to reduce the number of interrupt channels required for the USB device in the vectored interrupt controller This register reflects the status of the each interrupt line The USBIntSt is a read w...

Page 201: ...A 31 EN_USB_INTS Enable all USB interrupts When this bit is cleared the ORed output of the USB interrupt lines is not seen by the Vectored Interrupt Controller 1 Table 175 USB Interrupt Status register USBIntSt address 0xE01F C1C0 bit description Bit Symbol Description Reset value Table 176 USB Device Interrupt Status register USBDevIntSt address 0xE009 0000 bit allocation Reset value 0x0000 0000 ...

Page 202: ...RLZED Endpoints realized Set when Realize endpoint register or Maxpacket size register is updated 0 9 ERR_INT Error Interrupt Any bus error interrupt from the USB device Refer to Section 14 9 9 Read Error Status Command 0xFB Data read 1 byte on page 227 0 31 10 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA Table 177 USB Device In...

Page 203: ... high priority interrupt line All enabled endpoint Bit 23 22 21 20 19 18 17 16 Symbol Bit 15 14 13 12 11 10 9 8 Symbol EPR_INT EP_RLZED Bit 7 6 5 4 3 2 1 0 Symbol TxENDPKT Rx ENDPKT CDFULL CCEMTY DEV_STAT EP_SLOW EP_FAST FRAME Table 181 USB Device Interrupt Clear register USBDevIntClr address 0xE009 0008 bit description Bit Symbol Value Description Reset value 31 0 See USBDevIntClr bit allocation ...

Page 204: ...ity interrupt line 1 EP_FAST 0 EP_FAST interrupt is routed to the low priority interrupt line 0 1 EP_FAST interrupt is routed to the high priority interrupt line 7 2 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA Table 185 USB Endpoint Interrupt Status register USBEpIntSt address 0xE009 0030 bit allocation Reset value 0x0000 0000 ...

Page 205: ...endpoint NA 20 EP10RX Endpoint 10 Data Received Interrupt bit 0 21 EP10TX Endpoint 10 Data Transmitted Interrupt bit or sent a NAK 0 22 EP11RX Endpoint 11 Data Received Interrupt bit 0 23 EP11TX Endpoint 11 Data Transmitted Interrupt bit or sent a NAK 0 24 EP12RX Endpoint 12 Isochronous endpoint NA 25 EP12TX Endpoint 12 Isochronous endpoint NA 26 EP13RX Endpoint 13 Data Received Interrupt bit 0 27...

Page 206: ...n Table 172 The USBEpIntClr is a write only register Software is allowed to issue clear operation on multiple endpoints as well Let us take an example Assume bits 5 and 10 of Endpoint Interrupt Status register are to be cleared The software can issue Clear operation by writing in Endpoint Interrupt Clear register with corresponding bit positions set to 1 Then hardware will do the following 1 Clear...

Page 207: ...FAST or to the slow interrupt line EP_SLOW If set 1 the interrupt will be routed to the fast interrupt bit of the device status register Otherwise it will be routed to the slow endpoint interrupt bit Note that routing of multiple endpoints to EP_FAST or EP_SLOW is possible The Device Interrupt Priority register may override this register setting Refer to Section 14 7 6 USB Device Interrupt Priorit...

Page 208: ...EP7TX EP7RX EP6TX EP6RX EP5TX EP5RX EP4TX EP4RX Bit 7 6 5 4 3 2 1 0 Symbol EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX EP0RX Table 194 USB Endpoint Interrupt Priority register USBEpIntPri address 0xE009 0040 bit description Bit Symbol Value Description Reset value 31 0 See USBEpIntPri bit allocation table above 0 The corresponding interrupt will be routed to the slow endpoint interrupt bit in the De...

Page 209: ... has a reserved space in the EP_RAM The EP_RAM size requirement for an endpoint depends on its Maxpacketsize and whether it is double buffered or not 32 words of EP_RAM are used by the device for storing the buffer pointers The EP_RAM is word aligned but the Maxpacketsize is defined in bytes hence the RAM depth has to be adjusted to the next word boundary Also each buffer has one word header showi...

Page 210: ...ister will set the array element pointed by the Endpoint Index register 14 8 2 USB MaxPacketSize register USBMaxPSize 0xE009 004C At power on control endpoint is assigned the Maxpacketsize of 8 bytes Other endpoints are assigned 0 Modifying MaxPacketSize register content will cause the buffer address of the internal RAM to be recalculated This is essentially a multi cycle process At the end of it ...

Page 211: ...e only register 14 8 6 USB Transmit Packet Length register USBTxPLen 0xE009 0024 The software should first write the packet length Maximum Packet Size in the Transmit Packet Length register followed by the data write s to the Transmit Data register This register counts the number of bytes transferred from the CPU to the EP_RAM The Table 199 USB Receive Data register USBRxData address 0xE009 0018 b...

Page 212: ...etch the packet length to the receive packet length register The PKT_RDY bit Table 200 in the Packet Length Register is set along with this Also the hardware fills the receive data register with the first word of the packet The software can now start reading the Receive Data register Section 14 8 3 When the end of packet is reached the Read Enable bit RD_EN in Table 203 will be disabled by the con...

Page 213: ... a register before the next read write can happen The AHB HREADY output from the USB device is driven appropriately to take care of the timing Both Read Enable and Write Enable bits can be high at the same time for the same logical endpoint The interleaved read and write operation is possible 14 8 9 USB Command Code register USBCmdCode 0xE009 0010 This register is used for writing the commands The...

Page 214: ...t Also after a packet transfer the hardware clears the particular bit in DMA Request Status register The USBDMARClr is a write only register The USBDMARClr bit allocation is identical to the USBDMARSt register Table 206 Table 205 USB Command Data register USBCmdData address 0xE009 0014 bit description Bit Symbol Description Reset value 7 0 CommandData Command Data 0x00 31 8 Reserved user software ...

Page 215: ...ormally used for the test purpose It is also useful in the normal operation mode to avoid a lock situation if the DMA is programmed after that the USB packets are already received Normally the arrival of a packet generates an interrupt when it is completely received This interrupt is used by the DMA to start working This works fine as long as the DMA is programmed before the arrival of the packet ...

Page 216: ...30 and Section 14 11 DMA operation on page 234 for more details on DMA descriptors The USBUDCAH is a read write register The DMA Request Set register is normally used for the test purpose It is also useful in the normal operation mode to avoid a lock situation if the DMA is programmed after that the USB packets are already received Normally the arrival of a packet generates an interrupt when it is...

Page 217: ...EpDMAEn 0xE009 0088 Writing 1 to this register will enable the DMA operation for the corresponding endpoint Writing 0 will not have any effect The USBEpDMAEn is a write only register 14 8 17 USB EP DMA Disable register USBEpDMADis 0xE009 008C Writing 1 to this register will disable the DMA operation for the corresponding endpoint Writing 0 will have the effect of resetting the DMA_PROCEED flag The...

Page 218: ...USB EP DMA Disable register USBEpDMADis address 0xE009 008C bit description Bit Symbol Value Description Reset value 0 EP0_DMA_DISABLE 0 Control endpoint OUT DMA cannot be enabled for this endpoint and the EP0_DMA_DISABLE bit value must be 0 0 1 EP1_DMA_DISABLE 0 Control endpoint IN DMA cannot be enabled for this endpoint and the EP1_DMA_DISABLE bit value must be 0 0 31 2 EPxx_DMA_DISABLE Endpoint...

Page 219: ...sfer Interrupt enable bit 0 0 The End of Transfer Interrupt is disabled 1 The End of Transfer Interrupt is enabled 1 New_DD_Request_Interrupt_En New DD Request Interrupt enable bit 0 0 The New DD Request Interrupt is disabled 1 The New DD Request Interrupt is enabled 2 System_Error_Interrupt_En System Error Interrupt enable bit 0 0 The System Error Interrupt is disabled 1 The System Error Interrup...

Page 220: ...egister 14 8 25 USB New DD Request Interrupt Set register USBNDDRIntSet 0xE009 00B4 Writing 1 into the register will set the corresponding interrupt from the New DD Request Interrupt Status register Writing 0 will not have any effect The USBNDDRIntSet is a write only register Table 218 USB End of Transfer Interrupt Set register USBEoTIntSet address 0xE009 00A8 bit description Bit Symbol Value Desc...

Page 221: ...pt from the System Error Interrupt Status register Writing 0 will not have any effect The USBSysErrIntSet is a write only register Table 221 USB New DD Request Interrupt Set register USBNDDRIntSet address 0xE009 00B4 bit description Bit Symbol Value Description Reset value 31 0 EPxx Set endpoint xx 0 xx 31 new DD interrupt request 0 0 Ne effect 1 Set the EPxx new DD interrupt request in the USBNDD...

Page 222: ...r cmd_code_empty interrupt bit USBCmdCode 0x00F50200 while USBDevIntSt 0x20 Wait for cmd_data_full Temp USBCmdData Read Frame number MSB byte CurFrameNum CurFrameNum Temp 8 Table 224 USB System Error Interrupt Set register USBSysErrIntSet address 0xE009 00C0 bit description Bit Symbol Value Description Reset value 31 0 EPxx Set endpoint xx 0 xx 31 System Error Interrupt request 0 0 Ne effect 1 Set...

Page 223: ...al 00 00 02 00 Endpoint 1 00 01 05 00 Read 1 byte optional 00 01 02 00 Endpoint 2 00 02 05 00 Read 1 byte optional 00 02 02 00 Endpoint xx 00 xx 05 00 Read 1 byte optional 00 xx 02 00 xx physical endpoint number Endpoint 31 00 1F 05 00 Read 1 byte optional 00 1F 02 00 Select Endpoint Clear Interrupt Endpoint 0 00 40 05 00 Read 1 byte 00 40 02 00 Endpoint 1 00 41 05 00 Read 1 byte 00 41 02 00 Endpo...

Page 224: ...1 48 Mhz clock cannot be stopped in case when the device enters suspend state 1 INAK_CI Interrupt on NAK for Control IN endpoint 0 0 Only successful transactions generate an interrupt 1 Both successful and NAKed IN transactions generate interrupts 2 INAK_CO Interrupt on NAK for Control OUT endpoint 0 0 Only successful transactions generate an interrupt 1 Both successful and NAKed OUT transactions ...

Page 225: ...us Command 0xFE Data write 1 byte The Set Device Status command sets bits in the Device Status Register Table 229 Set Device Status Register bit description Bit Symbol Value Description Reset value 0 CON The Connect bit indicates the current connect status of the device It controls the SoftConnect_N output pin used for SoftConnect Reading the connect bit returns the current connect status 0 0 Writ...

Page 226: ...vice goes into the suspended state The device is disconnected The device receives resume signalling on its upstream port The Suspend Change bit is reset after the register has been read 0 0 SUS bit not changed 1 SUS bit changed At the same time a DEV_STAT interrupt is generated 4 RST Bus Reset bit On a bus reset the device will automatically go to the default state In the default state Device is u...

Page 227: ...Token CRC 0101 Error in Data CRC 0110 Time Out Error 0111 Babble 1000 Error in End of Packet 1001 Sent Received NAK 1010 Sent Stall 1011 Buffer Overrun Error 1100 Sent Empty Packet ISO Endpoints only 1101 Bitstuff Error 1110 Error in Sync 1111 Wrong Toggle Bit in Data PID ignored data 4 EA The Error Active bit will be reset once this register is read 7 5 Reserved user software should not write one...

Page 228: ...he selected endpoint is stalled 2 STP Setup bit the value of this bit is updated after each successfully received packet i e an ACKed package on that particular physical endpoint 0 0 The STP bit is cleared by doing a Select Endpoint Clear Interrupt on this endpoint 1 The last received packet for the selected endpoint was a setup packet 3 PO Packet over written bit 0 0 The PO bit is cleared by the ...

Page 229: ...ndpoint should stay in its stalled state the CPU can un stall it When a stalled endpoint is unstalled either by the Set Endpoint Status command or by receiving a SETUP token it is also re initialized This flushes the buffer in case of an OUT buffer it waits for a DATA 0 PID in case of an IN buffer it writes a DATA 0 PID There is no change on the interrupt status of the endpoint Even when unstalled...

Page 230: ...lag by the Validate Buffer command This indicates that the data in the buffer is valid and can be sent to the host when the next IN token is received A control IN buffer cannot be validated when the Packet Over written bit of its corresponding OUT buffer is set or when the Set up packet is pending in the buffer For the control endpoint the validated buffer will be invalidated when a Setup packet i...

Page 231: ...iptor Word position Access H W Access S W Bit position Description 0 R R W 31 0 Next_DD_pointer USB RAM address 1 R R W 1 0 DMA_mode 00 Normal 01 ATLE R R W 2 Next_DD_valid 1 valid 0 invalid 3 Reserved R R W 4 Isochronous_endpoint 1 isochronous 0 non isochronous R R W 15 5 Max_packet_size R W 1 R W 31 16 DMA_buffer_length in bytes 2 R W R W 31 0 DMA_buffer_start_addr 3 R W R I 0 DD_retired To be i...

Page 232: ... non isochronous endpoints only The max_packet_size field should be the same as the value set in the MaxPacketSize register for the endpoint 14 10 6 DMA_buffer_length This indicates the depth of the DMA buffer allocated for transferring the data The DMA engine will stop using this descriptor when this limit is reached and will look for the next descriptor This will be set by the software in the no...

Page 233: ...red But for isochronous endpoints this information is useful See Section 14 14 Isochronous Endpoint Operation on page 240 for isochronous endpoint operation 14 10 11 LS_byte_extracted Applicable only in the ATLE mode This bit set indicates that the Least Significant Byte LSB of the transfer length has been already extracted The extracted size will be reflected in the dma_buffer_length field in the...

Page 234: ...sent in the USB RAM Also the start address of the first DD is programmed into the DDP location for the corresponding endpoint The software will then set the DMA_ENABLE bit for this endpoint in the EP DMA Status register Section 14 8 15 The dma_mode bits in the descriptor has to be set to 00 for normal mode operation It should also initialize all the bits in the DD as given in the table 14 12 2 Fin...

Page 235: ...criptor Fetch A DMA transfer normally involves multiple packet transfers If a DD once fetched is equipped to do multiple transfers the hardware will not fetch DD for all the succeeding packets It will do the fetching only if the previous packet transferred on this channel does not belong to this endpoint This is on the assumption that the current contents of the hardware resource and that of the d...

Page 236: ...ccurs The DD is written back with DD_status data over run and DD_retired bit is set The DMA engine will raise the end of transfer interrupt and resets the corresponding bit for this endpoint in the DMA_ENABLE register This packet will be retransmitted to the memory fully when DMA_ENABLE bit is set again 14 12 6 No_Packet DD For IN transfers it can happen that for a request the system does not have...

Page 237: ...is value is programmed in the field Message_length_position of the DD It is responsibility of the hardware to read the two byte wide DMA_buffer_length at the offset from start of transfer specified by Message_length_position from incoming data and write it in DMA_buffer_length field of the DD Once this information is extracted from the incoming data and updated in the DD the transfer continues as ...

Page 238: ...nd the next DD is not programmed i e next_DD_valid field in DD1 is 0 then the first DD is retired with the status data over run DD_status 1000 which has to be treated as an err or condition and the DMA channel for that particular endpoint is disabled by the hardware Otherwise the first DD is retired with status normal completion DD_status 0010 Please note that in this mode the last buffer length t...

Page 239: ...the normal mode operation 14 13 3 Transferring the Data For OUT end points if the LS_byte_extracted or MS_byte_extracted bit in the status field is not set the hardware will extract the transfer length from the data stream dma_buffer_length field is derived from this information which is 2 bytes long Once the extraction is complete both the LS_byte_extracted and MS_byte_extracted bits will be set ...

Page 240: ...gth has to be placed or fetched 14 14 3 Transferring the Data The data is transferred to or from the memory location pointed by the dma_buffer_start_addr After the end of the packet transfer the dma_count value is incremented by 1 For an OUT transfer a word is formed by combining the frame number and the packet length such that the packet length appears at the least significant 2 bytes 15 to 0 Bit...

Page 241: ...l frame number was 21 The_total_number_of_bytes_transferred 0x0A 0x0F 0x08 0x14 0x35 The sixteenth bit for all the words in the packet length memory will be set to 1 Fig 55 Isochronous OUT Endpoint operation example DMA_mode Next_DD_Valid Isochronous_endpoint Max_packet_size DMA_buffer_length 0 16 31 After 4 packets 15 0x60000010 0x80000035 0x000A0010 0x4 0x0 W1 W2 W3 W4 W0 Full Empty Data memory ...

Page 242: ...ptional interrupt generation Up to four external outputs corresponding to match registers with the following capabilities Set low on match Set high on match Toggle on match Do nothing on match 15 2 Applications Interval Timer for counting internal events Pulse Width Demodulator via Capture inputs Free running timer 15 3 Description The Timer Counter is designed to count cycles of the peripheral cl...

Page 243: ...ns P0 2 P0 22 and P0 30 CAP0 1 2 pins P0 4 and P0 27 CAP0 2 3 pin P0 6 P0 16 and P0 28 CAP0 3 1 pin P0 29 CAP1 0 1 pin P0 10 CAP1 1 1 pin P0 11 CAP1 2 2 pins P0 17 and P0 19 CAP1 3 2 pins P0 18 and P0 21 Timer Counter block can select a capture signal as a clock source instead of the PCLK derived clock For more details see Section 15 5 3 Count Control Register CTCR TIMER0 T0CTCR 0xE000 4070 and TI...

Page 244: ...ed the TC is incremented and the PC is cleared The PC is observable and controllable through the bus interface R W 0 0xE000 4010 T0PC 0xE000 8010 T1PC MCR Match Control Register The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs R W 0 0xE0004014 T0MCR 0xE000 8014 T1MCR MR0 Match Register 0 MR0 can be enabled through the MCR to reset the TC stop both ...

Page 245: ...0 8038 T1CR3 EMR External Match Register The EMR controls the external match pins MATn 0 3 MAT0 0 3 and MAT1 0 3 respectively R W 0 0xE000 403C T0EMR 0xE000 803C T1EMR CTCR Count Control Register The CTCR selects between Timer and Counter mode and in Counter mode selects the signal and edge s for counting R W 0 0xE000 4070 T0CTCR 0xE000 8070 T1CTCR Table 237 TIMER COUNTER0 and TIMER COUNTER1 regis...

Page 246: ...alf of the PCLK clock Consequently duration of the high low levels on the same CAP input in this case can not be shorter than 1 PCLK Table 239 Timer Control Register TCR TIMER0 T0TCR address 0xE000 4004 and TIMER1 T1TCR address 0xE000 8004 bit description Bit Symbol Description Reset value 0 Counter Enable When one the Timer Counter and Prescale Counter are enabled for counting When zero the count...

Page 247: ...Register the Timer Counter is incremented and the Prescale Counter is reset on the next PCLK This causes the TC to increment on every PCLK when PR 0 every 2 PCLKs when PR 1 etc 15 5 7 Match Registers MR0 MR3 The Match register values are continuously compared to the Timer Counter value When the two values are equal actions can be triggered automatically The action possibilities are to generate an ...

Page 248: ... 0 0 Feature disabled 3 MR1I 1 Interrupt on MR1 an interrupt is generated when MR1 matches the value in the TC 0 0 This interrupt is disabled 4 MR1R 1 Reset on MR1 the TC will be reset if MR1 matches it 0 0 Feature disabled 5 MR1S 1 Stop on MR1 the TC and PC will be stopped and TCR 0 will be set to 0 if MR1 matches the TC 0 0 Feature disabled 6 MR2I 1 Interrupt on MR2 an interrupt is generated whe...

Page 249: ...ure on CAPn 0 rising edge a sequence of 0 then 1 on CAPn 0 will cause CR0 to be loaded with the contents of TC 0 0 This feature is disabled 1 CAP0FE 1 Capture on CAPn 0 falling edge a sequence of 1 then 0 on CAPn 0 will cause CR0 to be loaded with the contents of TC 0 0 This feature is disabled 2 CAP0I 1 Interrupt on CAPn 0 event a CR0 load due to a CAPn 0 event will generate an interrupt 0 0 This...

Page 250: ...onality of this output 0 1 EM1 External Match 1 This bit reflects the state of output MAT0 1 MAT1 1 whether or not this output is connected to its pin When a match occurs between the TC and MR1 this output of the timer can either toggle go low go high or do nothing Bits EMR 7 6 control the functionality of this output 0 2 EM2 External Match 2 This bit reflects the state of output MAT0 2 MAT1 2 whe...

Page 251: ...set to 2 and the match register set to 6 In the next clock after the timer reaches the match value the timer enable bit in TCR is cleared and the interrupt indicating that a match occurred is generated Table 244 External match control EMR 11 10 EMR 9 8 EMR 7 6 or EMR 5 4 Function 00 Do Nothing 01 Clear the corresponding External Match bit output to 0 MATn m pin is LOW if pinned out 10 Set the corr...

Page 252: ...ck diagram RESET MAXVAL Note that the capture register 3 cannot be used on TIMER0 TIMER CONTROL REGISTER PRESCALE REGISTER PRESCALE COUNTER PCLK ENABLE CAPTURE REGISTER 3 CAPTURE REGISTER 2 CAPTURE REGISTER 1 CAPTURE REGISTER 0 MATCH REGISTER 3 MATCH REGISTER 2 MATCH REGISTER 1 MATCH REGISTER 0 CAPTURE CONTROL REGISTER CONTROL MAT 3 0 INTERRUPT CAP 3 0 STOP ON MATCH RESET ON MATCH LOAD 3 0 TIMER C...

Page 253: ...ows for both positive going and negative going pulses Pulse period and width can be any number of timer counts This allows complete flexibility in the trade off between resolution and repetition rate All PWM outputs will occur at the same repetition rate Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses Match register updates are synchronized...

Page 254: ...n Additional single edge controlled PWM outputs require only one match register each since the repetition rate is the same for all PWM outputs Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle when an PWMMR0 match occurs Three match registers can be used to provide a PWM output with both edges controlled Again the PWMMR0 match register contr...

Page 255: ... REGISTER 0 LOAD ENABLE CONTROL MATCH CONTROL REGISTER M 6 0 INTERRUPT STOP ON MATCH RESET ON MATCH TIMER COUNTER CSN TCI CE MATCH REGISTER 3 MATCH REGISTER 2 MATCH REGISTER 1 MATCH REGISTER 0 MATCH REGISTER 4 MATCH REGISTER 5 MATCH REGISTER 6 SHADOW REGISTER 4 LOAD ENABLE SHADOW REGISTER 5 LOAD ENABLE SHADOW REGISTER 6 LOAD ENABLE PWM CONTROL REGISTER PWMENA1 6 PWMSEL2 6 MATCH 0 R S Q EN R S Q EN...

Page 256: ...r of double edge PWM outputs that are possible Using PWM 2 PWM4 and PWM6 for double edge PWM outputs provides the most pairings 16 2 1 Rules for single edge controlled PWM outputs 1 All single edge controlled PWM outputs go high at the beginning of a PWM cycle unless their match value is equal to 0 Fig 60 Sample PWM waveforms Table 245 Set and reset inputs for PWM Flip Flops PWM Channel Single Edg...

Page 257: ...changing if one of the old match values is equal to the PWM rate it is used again once if the neither of the new match values are equal to 0 or the PWM rate and there was no old match value equal to 0 4 If both a set and a clear of a PWM output are requested at the same time clear takes precedence This can occur when the set and clear match values are the same as in or when the set or clear value ...

Page 258: ...it is in double edge mode R W 0 0xE001 4018 PWMMR1 PWM Match Register 1 PWMMR1 can be enabled through PWMMCR to reset the PWMTC stop both the PWMTC and PWMPC and or generate an interrupt when it matches the PWMTC In addition a match between PWMMR1 and the PWMTC clears PWM1 in either single edge mode or double edge mode and sets PWM2 if it is in double edge mode R W 0 0xE001 401C PWMMR2 PWM Match R...

Page 259: ... addition a match between PWMMR6 and the PWMTC clears PWM6 in either single edge mode or double edge mode R W 0 0xE001 4048 PWMPCR PWM Control Register Enables PWM outputs and selects PWM channel types as either single edge or double edge controlled R W 0 0xE001 404C PWMLER PWM Latch Enable Register Enables use of new PWM match values R W 0 0xE001 4050 Table 247 Pulse Width Modulator PWM register ...

Page 260: ... the PWM Prescale Counter is reset on the next PCLK This causes the PWM TC to increment on every PCLK when PWMPR 0 every 2 PCLKs when PWMPR 1 etc Table 249 PWM Timer Control Register PWMTCR address 0xE001 4004 bit description Bit Symbol Description Reset value 0 Counter Enable When one the PWM Timer Counter and PWM Prescale Counter are enabled for counting When zero the counters are disabled 0 1 C...

Page 261: ...disabled 1 PWMMR0R 1 Reset on PWMMR0 the PWMTC will be reset if PWMMR0 matches it 0 0 This feature is disabled 2 PWMMR0S 1 Stop on PWMMR0 the PWMTC and PWMPC will be stopped and PWMTCR 0 will be set to 0 if PWMMR0 matches the PWMTC 0 0 This feature is disabled 3 PWMMR1I 1 Interrupt on PWMMR1 an interrupt is generated when PWMMR1 matches the value in the PWMTC 0 0 This interrupt is disabled 1 PWMMR...

Page 262: ... is disabled 17 PWMMR5S 1 Stop on PWMMR5 the PWMTC and PWMPC will be stopped and PWMTCR 0 will be set to 0 if PWMMR5 matches the PWMTC 0 0 This feature is disabled 18 PWMMR6I 1 Interrupt on PWMMR6 an interrupt is generated when PWMMR6 matches the value in the PWMTC 0 0 This interrupt is disabled 19 PWMMR6R 1 Reset on PWMMR6 the PWMTC will be reset if PWMMR6 matches it 0 0 This feature is disabled ...

Page 263: ... timing would be Write a new value to the PWM Match1 register Write a new value to the PWM Match2 register Write to the PWMLER setting bits 1 and 2 at the same time The altered values will become effective at the next reset of the timer when a PWM Match 0 event occurs 4 PWMSEL4 1 Selects double edge controlled mode for the PWM4 output 0 0 Selects single edge controlled mode for PWM4 5 PWMSEL5 1 Se...

Page 264: ...ting a one to this bit allows the last value written to the PWM Match 2 register to be become effective when the timer is next reset by a PWM Match event See Section 16 4 7 PWM Match Control Register PWMMCR 0xE001 4014 0 3 Enable PWM Match 3 Latch Writing a one to this bit allows the last value written to the PWM Match 3 register to be become effective when the timer is next reset by a PWM Match e...

Page 265: ...ADC cell can measure the voltage on any of these input signals Note that these analog inputs are always connected to their pins even if the Pin function Select register assigns them to port pins A simple self test of the ADC can be done by driving these pins as port outputs Note if the ADC is used signal levels on analog input pins must not be above the level of V3A at any time Otherwise A D conve...

Page 266: ...l to be included or excluded from contributing to the generation of an A D interrupt R W 0x0000 0100 0xE003 400C AD0INTEN 0xE006 000C AD1INTEN ADDR0 A D Channel 0 Data Register This register contains the result of the most recent conversion completed on channel 0 RO NA 0xE003 4010 AD0DR0 0xE006 0010 AD1DR0 ADDR1 A D Channel 1 Data Register This register contains the result of the most recent conve...

Page 267: ...verter does repeated conversions at the rate selected by the CLKS field scanning if necessary through the pins selected by 1s in the SEL field The first conversion after the start corresponds to the least significant 1 in the SEL field then higher numbered 1 bits pins if applicable Repeated conversions can be terminated by clearing this bit but the conversion that s in progress when this bit is cl...

Page 268: ...description Bit Symbol Value Description Reset value Table 256 A D Global Data Register AD0GDR address 0xE003 4004 and AD1GDR address 0xE006 0004 bit description Bit Symbol Description Reset value 5 0 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA 15 6 RESULT When DONE is 1 this field contains a binary fraction representing the vo...

Page 269: ...ed 1 bits pins if applicable Repeated conversions can be terminated by clearing this bit but the conversion that s in progress when this bit is cleared will be completed Important START bits must be 000 when BURST 1 or conversions will not start 0 0 Conversions are software controlled and require 11 clocks 23 17 Reserved user software should not write ones to reserved bits The value read from a re...

Page 270: ... for A D channel 0 0 9 OVERRUN1 This bit mirrors the OVERRRUN status flag from the result register for A D channel 1 0 10 OVERRUN2 This bit mirrors the OVERRRUN status flag from the result register for A D channel 2 0 11 OVERRUN3 This bit mirrors the OVERRRUN status flag from the result register for A D channel 3 0 12 OVERRUN4 This bit mirrors the OVERRRUN status flag from the result register for ...

Page 271: ...al DONE flag in ADDR is enabled to generate an interrupt 31 17 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA Table 259 A D Status Register ADSTAT ADC0 AD0STAT address 0xE003 4004 and ADC1 AD1STAT address 0xE006 0004 bit description Bit Symbol Value Description Reset value Table 260 A D Data Registers ADDR0 to ADDR7 ADC0 AD0DR0 to...

Page 272: ...nal XORed with ADCR bit 27 is used in the edge detection logic 17 5 2 Interrupts An interrupt request is asserted to the Vectored Interrupt Controller VIC when the DONE bit is 1 Software can use the Interrupt Enable bit for the A D Converter in the VIC to control whether this assertion results in an interrupt DONE is negated when the ADDR is read 17 5 3 Accuracy vs digital receiver The AIN functio...

Page 273: ... is written with a new value the voltage on this pin with respect to VSSA is VALUE 1024 VREF VREF Reference Voltage Reference This pin provides a voltage reference level for the D A converter VDDA VSSA Power Analog Power and Ground These should be nominally the same voltages as V3 and VSSD but should be isolated to minimize noise and error Table 262 DAC Register DACR address 0xE006 C000 bit descri...

Page 274: ...n function Select register 1 PINSEL1 0xE002 C004 on page 77 control whether the DAC is enabled and controlling the state of pin P0 25 AD0 4 AOUT When these bits are 10 the DAC is powered on and active The settling times noted in the description of the BIAS bit are valid for a capacitance load on the AOUT pin not exceeding 100 pF A load impedance value greater than that value will cause settling ti...

Page 275: ...ring time when system power is on and optionally when it is off It uses little power in Power down mode On the LPC2141 2 4 6 8 the RTC can be clocked by a separate 32 768 KHz oscillator or by a programmable prescale divider based on the VPB clock Also the RTC is powered by its own power supply pin VBAT which can be connected to a battery or to the same 3 3 V supply used by the rest of the device 1...

Page 276: ...dress ILR 2 Interrupt Location Register R W 0xE002 4000 CTC 15 Clock Tick Counter RO 0xE002 4004 CCR 4 Clock Control Register R W 0xE002 4008 CIIR 8 Counter Increment Interrupt Register R W 0xE002 400C AMR 8 Alarm Mask Register R W 0xE002 4010 CTIME0 32 Consolidated Time Register 0 RO 0xE002 4014 CTIME1 32 Consolidated Time Register 1 RO 0xE002 4018 CTIME2 32 Consolidated Time Register 2 RO 0xE002...

Page 277: ...5 3 Interrupt Wakeup register INTWAKE 0xE01F C144 on page 22 and Section 3 12 Wakeup timer on page 41 19 4 2 Miscellaneous register group Table 264 summarizes the registers located from 0 to 7 of A 6 2 More detailed descriptions follow 19 4 3 Interrupt Location Register ILR 0xE002 4000 The Interrupt Location Register is a 2 bit register that specifies which blocks are generating an interrupt see T...

Page 278: ...o reserved bits The value read from a reserved bit is not defined NA Table 266 Clock Tick Counter Register CTCR address 0xE002 4004 bit description Bit Symbol Description Reset value 14 0 Clock Tick Counter Prior to the Seconds counter the CTC counts 32 768 clocks per second Due to the RTC Prescaler these 32 768 time increments may not all be of the same duration Refer to the Section 19 6 Referenc...

Page 279: ...xE002 4014 The Consolidated Time Register 0 contains the low order time values Seconds Minutes Hours and Day of Week Table 268 Counter Increment Interrupt Register CIIR address 0xE002 400C bit description Bit Symbol Description Reset value 0 IMSEC When 1 an increment of the Second value generates an interrupt NA 1 IMMIN When 1 an increment of the Minute value generates an interrupt NA 2 IMHOUR Whe...

Page 280: ...erved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA 26 24 Day Of Week Day of week value in the range of 0 to 6 NA 31 27 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA Table 271 Consolidated Time register 1 CTIME1 address 0xE002 4018 bit description Bit Symbol Description ...

Page 281: ...Alarm Mask Register AMR 0xE002 4010 on page 279 alarm registers match their corresponding time counters then an interrupt is generated The interrupt is cleared when a one is written to bit one of the Interrupt Location Register ILR 1 Table 273 Time counter relationships and values Counter Size Enabled by Minimum value Maximum value Second 6 Clk1 see Figure 61 0 59 Minute 6 Second 0 59 Hour 5 Minut...

Page 282: ...tween the PCLK to the RTCX pins too Once the 32 kHz signal from RTCX1 2 pins is selected as a clock source the RTC can operate completely without the presence of the VPB clock PCLK Therefore power sensitive applications i e battery powered application utilizing the RTC will reduce the power consumption by using the signal from RTCX1 2 pins and writing a 0 into the PCRTC bit in the PCONP power cont...

Page 283: ...ed as PREFRAC PCLK PREINT 1 32768 19 6 3 Example of prescaler usage In a simplistic case the PCLK frequency is 65 537 kHz So PREINT int PCLK 32768 1 1 and PREFRAC PCLK PREINT 1 32768 1 With this prescaler setting exactly 32 768 clocks per second will be provided to the RTC by counting 2 PCLKs 32 767 times and 3 PCLKs once In a more realistic case the PCLK frequency is 10 MHz Then Table 276 Referen...

Page 284: ...ong the remaining pulses this jitter could possibly be of concern in an application that wishes to observe the contents of the Clock Tick Counter CTC directly Section 19 4 4 Clock Tick Counter Register CTCR 0xE002 4004 on page 278 19 6 4 Prescaler operation The Prescaler block labelled Combination Logic in Figure 62 determines when the decrement of the 13 bit PREINT counter is extended by one PCLK...

Page 285: ...ting the fraction 1 4 will cause every fourth cycle whenever the two LSBs of the Fraction Counter 10 counted by the 13 bit counter to be longer 19 7 RTC external 32 kHz oscillator component selection The RTC external oscillator circuit is shown in Figure 63 Since the feedback resistance is integrated on chip only a crystal the capacitances CX1 and CX2 need to be connected externally to the microco...

Page 286: ...f the crystal compared to the specified one Therefore for an accurate time reference it is advised to use the load capacitors as specified in Table 280 that belong to a specific CL The value of external capacitances CX1 and CX2 specified in this table are calculated from the internal parasitic capacitances and the CL Parasitics from PCB and package are not taken into account Fig 63 RTC 32kHz cryst...

Page 287: ...on 3 10 Reset on page 38 of this document 20 3 Description The watchdog consists of a divide by 4 fixed pre scaler and a 32 bit counter The clock is fed to the timer via a pre scaler The timer decrements when clocked The minimum value from which the counter decrements is 0xFF Setting a value lower than 0xFF causes 0xFF to be loaded in the counter Hence the minimum watchdog interval is TPCLK x 256 ...

Page 288: ...dog register map Name Description Access Reset value 1 Address WDMOD Watchdog Mode register This register contains the basic mode and status of the Watchdog Timer R W 0 0xE000 0000 WDTC Watchdog Timer Constant register This register determines the time out value R W 0xFF 0xE000 0004 WDFEED Watchdog Feed sequence register Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer to ...

Page 289: ...herwise the watchdog is triggered The interrupt reset will be generated during the second PCLK following an incorrect access to a watchdog timer register during a feed sequence 20 4 4 Watchdog Timer Value register WDTV 0xE000 000C The WDTV register is used to read the current value of watchdog timer 20 5 Block diagram The block diagram of the Watchdog is shown below in the Figure 64 Table 283 Watc...

Page 290: ...ster Under flow 1 Counter is enabled only when the WDEN bit is set and a valid feed sequence is done 2 WDEN and WDRESET are sticky bits Once set they can t be cleared until the watchdog underflows or an external reset occurs WDRESET 2 WDINT WDTOF WDEN 2 WDMOD Register Reset Interrupt SHADOW BIT Enable count 1 32 BIT DOWN COUNTER CURRENT WD TIMER COUNT 4 WDFEED WDTC Feed OK Feed error Feed sequence...

Page 291: ...to start the ISP command handler Assuming that proper signal is present on X1 pin when the rising edge on RESET pin is generated it may take up to 3 ms before P0 14 is sampled and the decision on whether to continue with user code or ISP handler is made If P0 14 is sampled low and the watchdog overflow flag is set the external hardware request to start the ISP command handler is ignored If there i...

Page 292: ... of the flash If the signatures match then the execution control is transferred to the user code by loading the program counter with 0x0000 0000 Hence the user flash reset vector should contain a jump instruction to the entry point of the user application code If the signature is not valid the auto baud routine synchronizes with the host via serial port 0 The host should send a 0x3F as a synchroni...

Page 293: ...and or Line Feed LF control characters Extra CR and LF characters are ignored All ISP responses are sent as CR LF terminated ASCII strings Data is sent and received in UU encoded format 21 4 4 ISP command format Command Parameter_0 Parameter_1 Parameter_n CR LF Data Data only for Write commands 21 4 5 ISP response format Return_Code CR LF Response_0 CR LF Response_1 CR LF Response_n CR LF Data Dat...

Page 294: ...isable interrupts or ensure that user interrupt vectors are active in RAM and that the interrupt handlers reside in RAM before making a flash erase write IAP call The IAP code does not use or disable interrupts 21 4 11 RAM used by ISP command handler ISP commands use on chip RAM from 0x4000 0120 to 0x4000 01FF The user could use this area but the contents may be lost upon reset Flash programming c...

Page 295: ...the correspondence between sector numbers and memory addresses for LPC2141 2 4 6 8 devices containing 32 64 128 256 and 512K bytes of Flash respectively IAP ISP and RealMonitor routines are located in the boot block The Fig 66 Boot process flowchart RUN AUTO BAUD RUN ISP COMMAND HANDLER RECEIVE CRYSTAL FREQUENCY No EXECUTE INTERNAL USER CODE Yes AUTO BAUD SUCCESSFUL Yes USER CODE VALID No WATCHDOG...

Page 296: ...sists of single bit error correction with Hamming code Table 287 Flash sectors in LPC2141 LPC2142 LPC2144 LPC2146 and LPC2148 Sector Number Sector Size kB Address Range LPC2141 32kB LPC2142 64kB LPC2144 128kB LPC2146 256kB LPC2148 512kB 0 4 0X0000 0000 0X0000 0FFF 1 4 0X0000 1000 0X0000 1FFF 2 4 0X0000 2000 0X0000 2FFF 3 4 0X0000 3000 0X0000 3FFF 4 4 0X0000 4000 0X0000 4FFF 5 4 0X0000 5000 0X0000 ...

Page 297: ...mechanism to perform properly data must be written into the Flash memory in groups of 4 bytes or multiples of 4 aligned as described above 21 7 Code Read Protection CRP Code read protection is enabled by programming the flash address location 0x1FC User flash sector 0 with value 0x8765 4321 2271560481 Decimal Address 0x1FC is used to allow some room for the FIQ exception handler When the code read...

Page 298: ...start sector number end sector number Table 298 Blank check sector s I start sector number end sector number Table 299 Read Part ID J Table 300 Read Boot code version K Table 302 Compare M address1 address2 number of bytes Table 303 Table 289 ISP Unlock command Command U Input Unlock code 2313010 Return Code CMD_SUCCESS INVALID_CODE PARAM_ERROR Description This command is used to unlock flash Writ...

Page 299: ...eck sum should be of the actual number of bytes sent The ISP command handler compares it with the check sum of the received bytes If the check sum matches the ISP command handler responds with OK CR LF to continue further transmission If the check sum does not match the ISP command handler responds with RESEND CR LF In response the host should retransmit the bytes Table 291 Correlation between pos...

Page 300: ...eration a two step process Table 293 ISP Write to RAM command Command W Input Start Address RAM address where data bytes are to be written This address should be a word boundary Number of Bytes Number of bytes to be written Count should be a multiple of 4 Return Code CMD_SUCCESS ADDR_ERROR Address not on word boundary ADDR_NOT_MAPPED COUNT_ERROR Byte count is not multiple of 4 PARAM_ERROR CODE_REA...

Page 301: ... command Command C Input Flash Address DST Destination Flash address where data bytes are to be written The destination address should be a 256 byte boundary RAM Address SRC Source RAM address from where data bytes are to be read Number of Bytes Number of bytes to be written Should be 256 512 1024 4096 Return Code CMD_SUCCESS SRC_ADDR_ERROR Address not on word boundary DST_ADDR_ERROR Address not o...

Page 302: ...am residing in RAM or Flash memory It may not be possible to return to the ISP command handler once this command is successfully executed This command is blocked when code read protection is enabled Example G 0 A CR LF branches to address 0x0000 0000 in ARM mode Table 298 ISP Erase sector command Command E Input Start Sector Number End Sector Number Should be greater than or equal to start sector ...

Page 303: ... Flash memory Blank check on sector 0 always fails as first 64 bytes are re mapped to flash boot block Example I 2 3 CR LF blank checks the flash sectors 2 and 3 Table 300 ISP Read Part Identification number command Command J Input None Return Code CMD_SUCCESS followed by part identification number in ASCII see Table 301 Description This command is used to read the part identification number Table...

Page 304: ...mapped to flash boot sector Example M 8192 1073741824 4 CR LF compares 4 bytes from the RAM address 0x4000 0000 to the 4 bytes from the flash address 0x2000 Table 304 ISP Return codes Summary Return Code Mnemonic Description 0 CMD_SUCCESS Command is executed successfully Sent by ISP handler only when command given by the host has been completely and successfully executed 1 INVALID_COMMAND Invalid ...

Page 305: ...resides at 0x7FFF FFF0 location and it is thumb code The IAP function could be called in the following way using C Define the IAP location entry point Since the 0th bit of the IAP location is set there will be a change to Thumb instruction set when the program counter branches to this address define IAP_LOCATION 0x7ffffff1 Define data structure or pointers to pass IAP command table and result tabl...

Page 306: ... 0002 A 05 up to 4 parameters can be passed in the r0 r1 r2 and r3 registers respectively Additional parameters are passed on the stack Up to 4 parameters can be returned in the r0 r1 r2 and r3 registers respectively Additional parameters are returned indirectly via memory Some of the IAP calls require more than 4 parameters If the ARM suggested scheme is used for the parameter passing returning t...

Page 307: ...r0 ARM REGISTER r1 Table 306 IAP Prepare sector s for write operation command Command Prepare sector s for write operation Input Command code 5010 Param0 Start Sector Number Param1 End Sector Number should be greater than or equal to start sector number Return Code CMD_SUCCESS BUSY INVALID_SECTOR Result None Description This command must be executed before executing Copy RAM to Flash or Erase Sect...

Page 308: ...R_NOT_MAPPED COUNT_ERROR Byte count is not 256 512 1024 4096 SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION BUSY Result None Description This command is used to program the flash memory The affected sectors should be prepared first by calling Prepare Sector for Write Operation command The affected sectors are automatically protected again once the copy command is successfully executed The boot sector can...

Page 309: ...d location Description This command is used to blank check a sector or multiple sectors of on chip Flash memory To blank check a single sector use the same Start and End sector numbers Table 310 IAP Read Part Identification command Command Read part identification number Input Command code 5410 Parameters None Return Code CMD_SUCCESS Result Result0 Part Identification Number see Table 301 LPC214x ...

Page 310: ...st 64 bytes starting from address zero The first 64 bytes can be re mapped to RAM Table 313 Reinvoke ISP Command Compare Input Command code 5710 Return Code None Result None Description This command is used to invoke the bootloader in ISP mode This command maps boot vectors configures P0 1 as an input and sets the VPB divider register to 0 before entering the ISP mode This command may be used when...

Page 311: ...ue is taken in to consideration where applicable 5 DST_ADDR_NOT_MAPPED Destination address is not mapped in the memory map Count value is taken in to consideration where applicable 6 COUNT_ERROR Byte count is not multiple of 4 or is not a permitted value 7 INVALID_SECTOR Sector number is invalid 8 SECTOR_NOT_BLANK Sector is not blank 9 SECTOR_NOT_PREPARED_ FOR_WRITE_OPERATION Command to prepare se...

Page 312: ...e are two JTAG style scan chains within the ARM7TDMI S A JTAG style Test Access Port Controller controls the scan chains In addition to the scan chains the debug architecture uses EmbeddedICE logic which resides on chip with the ARM7TDMI S core The EmbeddedICE has its own scan chain that is used to insert watchpoints and breakpoints for the ARM7TDMI S core The EmbeddedICE logic consists of two rea...

Page 313: ...E logic 22 4 Pin description 22 5 Reset state of multiplexed pins On the LPC2141 2 4 6 8 the pins above are multiplexed with P1 31 26 To have them come up as a Debug port connect a weak bias resistor 4 7 10 kΩ depending on the external JTAG circuitry between VSS and the P1 26 RTCK pin To have them come up as GPIO pins do not connect a bias resistor and ensure that any external driver connected to ...

Page 314: ...ebug communication data register 00101 Watchpoint 0 Address Value 32 Holds watchpoint 0 address value 01000 Watchpoint 0 Address Mask 32 Holds watchpoint 0 address mask 01001 Watchpoint 0 Data Value 32 Holds watchpoint 0 data value 01010 Watchpoint 0 Data Mask 32 Holds watchpoint 0 data mask 01011 Watchpoint 0 Control Value 9 Holds watchpoint 0 control value 01100 Watchpoint 0 Control Mask 8 Holds...

Page 315: ... exports it through a narrow trace port An external Trace Port Analyzer captures the trace information under software debugger control Trace port can broadcast the Instruction trace information Instruction trace or PC trace shows the flow of execution of the processor and provides a list of all the instructions that were executed Instruction trace is significantly compressed by only broadcasting b...

Page 316: ...ace clock This clock is not generated by the ETM block It is to be derived from the system clock The clock should be balanced to provide sufficient hold time for the trace data signals Half rate clocking mode is supported Trace data signals should be shifted by a clock phase from TRACECLK Refer to Figure 3 14 page 3 26 and figure 3 15 page 3 27 in ETM7 Technical Reference Manual ARM DDI 0158B for ...

Page 317: ...f the comparison WO 000 0111 Trace Enable Event Holds the enabling event WO 000 1000 Trace Enable Control 1 Holds the include and exclude regions WO 000 1001 FIFOFULL Region Holds the include and exclude regions WO 000 1010 FIFOFULL Level Holds the level below which the FIFO is considered full WO 000 1011 ViewData event Holds the enabling event WO 000 1100 ViewData Control 1 Holds the include excl...

Page 318: ...e 1 Chapter 23 Embedded Trace 23 7 Block diagram The block diagram of the ETM debug environment is shown below in Figure 69 Fig 69 ETM debug environment block diagram PERIPHERAL TRACE PORT ANALYZER TRACE 10 Host running debugger LAN JTAG INTERFACE UNIT CONNECTOR TRIGGER ETM PERIPHERAL RAM ROM EMBEDDEDICE ARM 5 CONNECTOR APPLICATION PCB ...

Page 319: ... which is present in the EmbeddedICE logic RealMonitor provides advantages over the traditional methods for debugging applications in ARM systems The traditional methods include Angel a target based debug monitor Multi ICE or other JTAG unit and EmbeddedICE logic a hardware based debug solution Although both of these methods provide robust debugging environments neither is suitable as a lightweigh...

Page 320: ...hown in Figure 70 RealMonitor is split in to two functional components 24 3 2 RMHost This is located between a debugger and a JTAG unit The RMHost controller RealMonitor dll converts generic Remote Debug Interface RDI requests from the debugger into DCC only RDI messages for the JTAG unit For complete details on debugging a RealMonitor integrated application from the host see the ARM RMHost User G...

Page 321: ...the host component RMHost using the Debug Communications Channel DCC which is a reliable link whose data is carried over the JTAG connection While user application is running RMTarget typically uses IRQs generated by the DCC This means that if user application also wants to use IRQs it must pass any DCC generated interrupts to RealMonitor To allow nonstop debugging the EmbeddedICE RT logic in the ...

Page 322: ...tion Both IRQs and FIQs continue to be serviced if they were enabled by the application at the time the foreground application was stopped 24 4 How to enable Realmonitor The following steps must be performed to enable RealMonitor A code example which implements all the steps can be found at the end of this section 24 4 1 Adding stacks User must ensure that stacks are set up within application for ...

Page 323: ... interrupts and exceptions Figure 72 illustrates how exceptions can be claimed by RealMonitor itself or shared between RealMonitor and application If user application requires the exception sharing they must provide function such as app_IRQDispatch Depending on the nature of the exception this handler can either Pass control to the RealMonitor processing routine such as rm_irqhandler2 Claim the ex...

Page 324: ...efetchabort_handler IMPORT rm_dataabort_handler IMPORT rm_irqhandler2 IMPORT rm_undef_handler IMPORT User_Entry Entry point of user application CODE32 ENTRY Define exception table Instruct linker to place code at address 0x0000 0000 AREA exception_table CODE LDR pc Reset_Address LDR pc Undefined_Address LDR pc SWI_Address LDR pc Prefetch_Address LDR pc Abort_Address NOP Insert User code valid sign...

Page 325: ...000xxxx Top of on chip RAM __init Set up the stack pointers for various processor modes Stack grows downwards LDR r2 ram_end Get top of RAM MRS r0 CPSR Save current processor mode Initialize the Undef mode stack for RealMonitor use BIC r1 r0 0x1f ORR r1 r1 0x1b MSR CPSR_c r1 Keep top 32 bytes for flash programming routines Refer to Flash Memory System and Programming chapter SUB sp r2 0x1F Initial...

Page 326: ... 0xC0 enable IRQs and FIQs MSR CPSR_c r1 update the CPSR Get the address of the User entry point LDR lr User_Entry MOV pc lr Non vectored irq handler app_irqDispatch AREA app_irqDispatch CODE VICVectAddrOffset EQU 0x30 app_irqDispatch enable interrupt nesting STMFD sp r12 r14 MRS r12 spsr Save SPSR in to r12 MSR cpsr_c 0x1F Re enable IRQ go to system mode User should insert code here if non vector...

Page 327: ..._STOPSTART TRUE This option enables or disables support for all stop and start debugging features RM_OPT_SOFTBREAKPOINT TRUE This option enables or disables support for software breakpoints RM_OPT_HARDBREAKPOINT TRUE Enabled for cores with EmbeddedICE RT This device uses ARM 7TDMI S Rev 4 with EmbeddedICE RT RM_OPT_HARDWATCHPOINT TRUE Enabled for cores with EmbeddedICE RT This device uses ARM 7TDM...

Page 328: ... the code for gathering statistics about the internal operation of RealMonitor RM_DEBUG FALSE This option enables or disables additional debugging and error checking code in RealMonitor RM_OPT_BUILDIDENTIFIER FALSE This option determines whether a build identifier is built into the capabilities table of RMTarget Capabilities table is stored in ROM RM_OPT_SDM_INFO FALSE SDM gives additional informa...

Page 329: ...tal Converter BOD Brown Out Detection CPU Central Processing Unit DAC Digital to Analog Converter DCC Debug Communications Channel FIFO First In First Out GPIO General Purpose Input Output NA Not Applicable PLL Phase Locked Loop POR Power On Reset PWM Pulse Width Modulator RAM Random Access Memory SRAM Static Random Access Memory UART Universal Asynchronous Receiver Transmitter USB Universal Seria...

Page 330: ...roduction relevant changes will be communicated via a Customer Product Process Change Notification CPCN Philips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no licence or title under any patent copyright or mask work right to these products and makes no representations or warranties that these products are free from patent copyright or mask wor...

Page 331: ...fication Register RSIR address 0xE01F C180 bit description 39 Table 28 VPB divider register map 40 Table 29 VPB Divider register VPBDIV address 0xE01F C100 bit description 41 Table 30 MAM Responses to program accesses of various types 47 Table 31 MAM responses to data and DMA accesses of various types 47 Table 32 Summary of MAM registers 48 Table 33 MAM Control Register MAMCR address 0xE01F C000 b...

Page 332: ... Table 79 Fast GPIO port 0 Pin value register FIO0PIN address 0x3FFF C014 bit description 87 Table 80 Fast GPIO port 1 Pin value register FIO1PIN address 0x3FFF C034 bit description 87 Table 81 Fast GPIO port 0 Pin value byte and half word accessible register description 88 Table 82 Fast GPIO port 1 Pin value byte and half word accessible register description 88 Table 83 GPIO port 0 output Set reg...

Page 333: ...0 LPC2144 6 8 only bit description 123 Table 126 Modem status interrupt generation 125 Table 127 UART1 Line Status Register U1LSR address 0xE001 0014 read only bit description 125 Table 128 UART1 Modem Status Register U1MSR address 0xE001 0018 LPC2144 6 8 only bit description 127 Table 129 UART1 Scratch pad register U1SCR address 0xE001 0014 bit description 127 Table 130 Auto baud Control Register...

Page 334: ...ocation 201 Table 177 USB Device Interrupt Status register USBDevIntSt address 0xE009 0000 bit description 201 Table 178 USB Device Interrupt Enable register USBDevIntEn address 0xE009 0004 bit allocation 202 Table 179 USB Device Interrupt Enable register USBDevIntEn address 0xE009 0004 bit description 202 Table 180 USB Device Interrupt Clear register USBDevIntClr address 0xE009 0008 bit allocatio...

Page 335: ...rrupt Status register USBNDDRIntSt address 0xE009 00AC bit description 220 Table 220 USB New DD Request Interrupt Clear register USBNDDRIntClr address 0xE009 00B0 bit description 220 Table 221 USB New DD Request Interrupt Set register USBNDDRIntSet address 0xE009 00B4 bit description 221 Table 222 USB System Error Interrupt Status register USBSysErrIntSt address 0xE009 00B8 bit description 221 Tab...

Page 336: ... 0 CTIME0 address 0xE002 4014 bit description 280 Table 271 Consolidated Time register 1 CTIME1 address 0xE002 4018 bit description 280 Table 272 Consolidated Time register 2 CTIME2 address 0xE002 401C bit description 280 Table 273 Time counter relationships and values 281 Table 274 Time counter registers 281 Table 275 Alarm registers 282 Table 276 Reference clock divider registers 283 Table 277 P...

Page 337: ...tion command 309 Table 311 IAP Read Boot code version number command 309 Table 312 IAP Compare command 310 Table 313 Reinvoke ISP 310 Table 314 IAP Status codes Summary 310 Table 315 EmbeddedICE pin description 313 Table 316 EmbeddedICE logic registers 314 Table 317 ETM configuration 315 Table 318 ETM pin description 316 Table 319 ETM registers 317 Table 320 RealMonitor stack requirement 322 Table...

Page 338: ...g 34 Format and States in the Master Receiver mode 151 Fig 35 Format and States in the Slave Receiver mode 152 Fig 36 Format and States in the Slave Transmitter mode 153 Fig 37 Simultaneous repeated START conditions from two masters 162 Fig 38 Forced access to a busy I2C bus 162 Fig 39 Recovering from a bus obstruction caused by a low level on SDA 162 Fig 40 SPI data transfer format CPHA 0 and CPH...

Page 339: ...pt Polarity register EXTPOLAR 0xE01F C14C 24 3 5 6 Multiple external interrupt pins 25 3 6 Other system controls 26 3 6 1 System Control and Status flags register SCS 0xE01F C1A0 26 3 7 Memory mapping control 26 3 7 1 Memory Mapping control register MEMMAP 0xE01F C040 26 3 7 2 Memory mapping control usage notes 27 3 8 Phase Locked Loop PLL 27 3 8 1 Register description 28 3 8 2 PLL Control registe...

Page 340: ...0xFFFF F00C 55 5 4 7 IRQ Status register VICIRQStatus 0xFFFF F000 56 5 4 8 FIQ Status register VICFIQStatus 0xFFFF F004 57 5 4 9 Vector Control registers 0 15 VICVectCntl0 15 0xFFFF F200 23C 57 5 4 10 Vector Address registers 0 15 VICVectAddr0 15 0xFFFF F100 13C 58 5 4 11 Default Vector Address register VICDefVectAddr 0xFFFF F034 58 5 4 12 Vector Address register VICVectAddr 0xFFFF F030 58 5 4 13 ...

Page 341: ...frequency considerations when using the legacy and enhanced GPIO registers 93 Chapter 9 Universal Asynchronous Receiver Transmitter 0 UART0 9 1 Features 95 9 2 Pin description 95 9 3 Register description 95 9 3 1 UART0 Receiver Buffer Register U0RBR 0xE000 C000 when DLAB 0 Read Only 97 9 3 2 UART0 Transmit Holding Register U0THR 0xE000 C000 when DLAB 0 Write Only 97 9 3 3 UART0 Divisor Latch Regis...

Page 342: ...6 6 Serial clock generator 141 11 6 7 Timing and control 141 11 6 8 Control register I2CONSET and I2CONCLR 141 11 6 9 Status decoder and Status register 142 11 7 Register description 142 11 7 1 I2C Control Set register I2CONSET I2C0 I2C0CONSET 0xE001 C000 and I2C1 I2C1CONSET 0xE005 C000 143 11 7 2 I2C Control Clear register I2CONCLR I2C0 I2C0CONCLR 0xE001 C018 and I2C1 I2C1CONCLR 0xE005 C018 144 1...

Page 343: ...formation 173 12 2 4 Master operation 173 12 2 5 Slave operation 174 12 2 6 Exception conditions 174 12 2 7 Read Overrun 174 12 2 8 Write Collision 174 12 2 9 Mode Fault 175 12 2 10 Slave Abort 175 12 3 Pin description 175 12 4 Register description 175 12 4 1 SPI Control Register S0SPCR 0xE002 0000 176 12 4 2 SPI Status Register S0SPSR 0xE002 0004 177 12 4 3 SPI Data Register S0SPDR 0xE002 0008 17...

Page 344: ...B Endpoint Interrupt Priority register USBEpIntPri 0xE009 0040 207 14 7 12 USB Realize Endpoint register USBReEp 0xE009 0044 208 14 8 EP_RAM requirements 209 14 8 1 USB Endpoint Index register USBEpIn 0xE009 0048 210 14 8 2 USB MaxPacketSize register USBMaxPSize 0xE009 004C 210 14 8 3 USB Receive Data register USBRxData 0xE009 0018 211 14 8 4 USB Receive Packet Length register USBRxPLen 0xE009 002...

Page 345: ... 232 14 10 3 Next_DD_valid 232 14 10 4 Isochronous_endpoint 232 14 10 5 Max_packet_size 232 14 10 6 DMA_buffer_length 232 14 10 7 DMA_buffer_start_addr 232 14 10 8 DD_retired 232 14 10 9 DD_status 232 14 10 10 Packet_valid 233 14 10 11 LS_byte_extracted 233 14 10 12 MS_byte_extracted 233 14 10 13 Present_DMA_count 233 14 10 14 Message_length_position 233 14 10 15 Isochronous_packetsize_memory_addr...

Page 346: ...WM Timer Counter PWMTC 0xE001 4008 260 16 4 4 PWM Prescale Register PWMPR 0xE001 400C 260 16 4 5 PWM Prescale Counter register PWMPC 0xE001 4010 260 16 4 6 PWM Match Registers PWMMR0 PWMMR6 261 16 4 7 PWM Match Control Register PWMMCR 0xE001 4014 261 16 4 8 PWM Control Register PWMPCR 0xE001 404C 262 16 4 9 PWM Latch Enable Register PWMLER 0xE001 4050 263 Chapter 17 Analog to Digital Converter ADC...

Page 347: ...atchdog Mode register WDMOD 0xE000 0000 288 20 4 2 Watchdog Timer Constant register WDTC 0xE000 0004 289 20 4 3 Watchdog Feed register WDFEED 0xE000 0008 289 20 4 4 Watchdog Timer Value register WDTV 0xE000 000C 289 20 5 Block diagram 289 Chapter 21 Flash Memory System and Programming 21 1 Flash Boot Loader 291 21 2 Features 291 21 3 Applications 291 21 4 Description 291 21 4 1 Memory map after an...

Page 348: ...0 21 9 8 Reinvoke ISP 310 21 9 9 IAP Status codes 310 21 10 JTAG Flash programming interface 311 Chapter 22 EmbeddedICE logic 22 1 Features 312 22 2 Applications 312 22 3 Description 312 22 4 Pin description 313 22 5 Reset state of multiplexed pins 313 22 6 Register description 314 22 7 Block diagram 314 Chapter 23 Embedded Trace Macrocell ETM 23 1 Features 315 23 2 Applications 315 23 3 Descripti...

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