13
11) HML0 + 4E: Input hold / Input change interruption / Occurrence condition for input
change interruption / Error interruption
bit
7
6
5
4
3
2
1
0
Assignment
Input hold (1: Hold, 0: Hold cancel)
Input change interruption (1: Effective, 0: Ineffective)
Occurrence condition for input change interruption (1: ON → OFF, 0: OFF → ON)
Error interruption (1: Effective, 0: Ineffective)
Unused
(= 0)
bit 0: If the input signal is changed, “Input hold” selects whether the changed condition is main-
tained or not. (Usable for
S-LINK V
address 0 to 7 only. However, if hold is used at one
address, then all 0 to 7 are held.) If bit 0 is “1,” even when the input signal is changed, the
condition is maintained until “0” is written in bit 0. After “0” has been written in bit 0, normal
transmission is resumed.
bit 1: “Input change interruption” sets whether an interruption occurs or not when the input signal
changes. In case bit 1 is “1” an interruption occurs, and in case it is “0,” an interruption does
not occur. If the input change interruption is effective, an interruption occurs when the input
signal of
S-LINK V
input address set as “1” at “
Bank change-over response register =
07H
” changes.
bit 2: “Occurrence condition for input change interruption” sets whether the interruption occurs
with “1: ON → OFF” or “0: OFF → ON,” when bit 1 is “1.”
ON
OFF
1
0
Occurrence
Input signal of
input unit
Interruption
bit 2
Occurrence
In order to clear the interruption,
6) Command execution request register
7) Command completion response register
are used.
Note: Occurrence condition for input change interruption is applied to all input interruptions.
(However, it cannot be selected in units of one channel.)
ON
OFF
1
0
1
0
1
0
Hold
Read out
Read out
Read out
This cannot be read out because the timing of
the input signal and reading out do not match.
The timing of input
read out on user’s
computer
Input signal to
the input unit
Process of internal
circuit
Input read out data
on user’s
computer
bit 0
