11
5) HML0 + 48: Error No. / Error state
bit 0 to 3 : Occurred error No. is displayed. (0H to 6H)
bit 7
: The error state is indicated.
Notes: 1) Error 0 is not automatically restored. (In case bit 7 is “1” and bit 0 to 3 is “0H,” Error “0” occurs.)
2) If Error 1, 2, and 3 to 6 occur at the same time, Error 1 and 2 are given priority in error indication.
3) For Error 1 to 6, in case the cause of the error is eliminated, although bit “7” becomes “0,” the error
No. indication of bit 0 to 3 is maintained.
bit
7
6
5
4
3
2
1
0
Error No.
Description
0
0
0
0
0
System (control board) abnormality
0
0
0
1
1
Short-circuit b24V and D
0
0
1
0
2
Short-circuit between D and G
0
0
1
1
3
Abnormality or disconnection of I/O unit
0
1
0
0
4
Unrecognized unit added
0
1
0
1
5
Output short-circuit of the output unit · I/O device driver power supply shut down
0
1
1
0
6
System set is not carried out properly
Error states
(1: Error occurrence, 0: Normal operation, error rectified)
Unused
(= 0)
bit 0: “Communication frame confirmation indication”
It is used for checking if the output data is sent to
S-LINK V
output unit.
In case data is sent to the same address at an interval shorter than the
S-LINK V
system
response delay time, the data may not be transmitted. After the output data is written, if “1”
is written into HML0 + 49 bit 0, and the next output data is written in after confirming that
HML0 + 4A bit 0 has turned to “1,” then output data transmission error can be avoided.
bit 1: “Error No. clear”
It clears the error No. in case the cause of error has been eliminated at “
5) HML0 + 48: Er-
ror No. / Error state
” in “
4. Assignment on Computer
” and when HML0 + 48 bit 7 is “0.”
If “1” is written into HML0 + 49 bit 1, HML0 + 4A bit 1 turns to “1” after the error No. is
cleared.
6) HML0 + 49: Command execution request register
7) HML0 + 4A: Command completion response register (read out only)
These are used to indicate Communication frame confirmation, Error No. clearance, Default, Sys
-
tem set, Interruption, Busy, On Hold and command under execution.
bit
7
6
5
4
3
2
1
0
Command execution request register
(HML0 + 49)
Command completion response register
(HML0 + 4A)
Communication frame confirmation request Communication frame completion confirmation indication
Error No. clear request
Error No. clear completion indication
Default request
Default completion indication
System set request
System set completion indication
Interruption request
Interruption indication
-
Busy indication
-
On Hold indication
-
Command under execution indication
