14
bit 3: “Error interruption” sets whether an interruption occurs or not when an error occurs.
When bit 3 is “1” an interruption occurs, and when bit 3 is “0” the interruption does not occur.
In case the error interruption is set to effective, the interruption occurs with OR operation
applied to all error occurrences.
For contents of error, check by “
5) HML0 + 48: Error No. / Error state
.”
Occurrence
Interruption
Error
In order to clear the interruption,
6) Command execution request register
7) Command completion response register
are used.
Error occurrence
Note: In case bit 2 (Input change interruption) and bit 3 (Error interruption) are both “1,” bit 3 (Error
interruption) has priority. Input change interruption does not occur.
12) HML0 + 50: Board No. setting (BSN)
BSN that is set at “
2) Board No. setting switch (SW5)
” under “
3. Functional Description
” can
be read out.
