Orban OPTIMOD 6200, Operating Manual

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6-16
TECHNICAL DATA Orban Model 6200
The balanced audio output signal is applied to the RF filter network made up of
L412, L413, L402, and L403, and then to XLR connector J400.
The corresponding right channel circuitry is functionally identical to that just de-
scribed.
3. Digital Sample Rate Converter (SRC) and Output Transmitter
An output sample rate converter (SRC) chip is used to convert the 48kHz 6200 system
sample rate to any of the standard 32kHz, 44.1kHz or 48kHz rates. A digital audio inter-
face transmitter chip is used to encode digital audio signals using the AES/EBU interface
format (AES3-1992). A synchronous serial interface is used for all inter-chip communi-
cation between the DSP, SRC, and AES transmitter chips.
Component-Level Description:
The processed digital output (DIG_OUT) provided at the SAI output port SDO0
(pin 47) of DSP IC707 is received by asynchronous sample rate converter (SRC)
IC602 pin 3. A 6.144MHz bit clock is provided from the system clock circuitry to
both the final DSP and the SRC chips. DSP chip IC707 receives a 48kHz frame
clock at its WST input (pin 50) that sets the word transfer rate to two words per
48kHz period. The SRC receives a 48kHz clock at its
R L/
_I input (pin 6).
R L/
_I
delineates the samples of the two channels used by the SRC. The DSP output
samples are formatted to ensure that the SRC uses samples that represent the si-
multaneously sampled analog input.
Crystal oscillator Y601 provides the output SRC a master clock of 17.000MHz on
pin 2. This MCLK frequency allows the output SRC to operate with an output
sample rate in the range between 30kHz and 59kHz. OSRC_RST is an active low
reset signal tied to pin 13 of the SRC. This signal comes from multiplexer chip
IC609 and is controlled by the Z-180 via either pin 2 of latch IC604 or pin 8 of
IC605-D.
The MSBDLY_I, BKPOL_I, and TRGLR_I pins of the SRC chip configure the
chip to interface with the last DSP chip (IC707). Pin 1 of the SRC (GPDLYS) is
tied high to minimize the chip's group delay to approximately 700
µ
s as opposed
to approximately 3ms, giving up some tolerance to variations in sample rates. Pin
28 (SETLSLW) is tied high to cause the SRC to settle slowly to changes in sam-
ple rates, resulting in the best rejection of sample rate jitter.
The output side of the sample rate converter is tied directly to IC603, an
AES/EBU digital audio transmitter integrated circuit. This interface uses the AES
transmitter chip as master unless external sync has been selected and a valid sync
signal is present at the input or sync input AES receiver chips, in which case the
chip with the valid sync signal becomes master (see external sync available
clocks). Two free running clocks provide the standard sample rates of 32kHz,
44.1kHz and 48kHz when an internal sync is requested. These clocks run at a fre-
quency that is 384 or 256 times the sample rate they represent. They have a fre-
quency stability of
±
100PPM. The third clock is the clock that is recovered from
the appropriate AES/EBU receiver chip. This clock has a frequency of 256 times
the input sample rate of the received signal. This is used to drive the output