Orban OPTIMOD 6200, Operating Manual

Page: 148 / 195

6-6
TECHNICAL DATA Orban Model 6200
Circuit Description
This section provides a detailed description of circuits used in the 6200. It starts with an
overview of the 6200 system, identifying circuit sections and describing their purpose.
Then each section is treated in detail by first giving an overview of the circuits followed
by a component-by-component description. Keywords are highlighted throughout the
circuit descriptions to help you quickly locate the information you need.
Overview
The block diagram on page 6-32 illustrates the following overview of 6200 circuit sec-
tions.
The 12.288MHz Oscillator and System Clocking section provides the various clocks
needed by the control, I/O and DSP circuits to carry out their functions.
The Control Circuits administrate control of the 6200 system.
The User Control Interface and LED Display Circuits section includes the connector,
RF-filtering, and circuitry for the remote control inputs and RS-232 interface. It also in-
cludes circuitry for the front panel pushbutton switches, LED control status indicators,
and LED Meters. The LED Meters measure various 6200 signal levels and display the
results on ten front panel 10-segment LED meters.
The Input Circuits include the connectors and RF-filtering for the analog and digital au-
dio inputs, the digital sync input, and the circuitry to interface these inputs to the digital
processing.
The Output Circuits include the connectors and RF-filtering for the analog and digital
audio outputs, and the circuitry to interface the digital processing to these outputs.
The DSP Circuits implement the bypass, test tone, and audio processing using digital
signal processing.
The Power Supply provides power for all 6200 circuit sections.
12.288MHz Oscillator and System Clocking
A synchronous clocking scheme is used on the 6200 to eliminate any asynchronous
clocks operating in the sensitive regions of the input A/D converter. A single
12.288MHz crystal oscillator provides the timing reference for all system digital clock
signals. The only clocks that run asynchronous to this clock are the AES/EBU digital
audio input related clocks, the 11.2896MHz free running crystal clock oscillator provid-
ing the 44.1kHz AES/EBU output sample rate, and the 17.000MHz free running crystal
clock oscillator used as the master clock for the sample rate converters. These do not fall
within a sensitive region of the A/D. Synchronous counters are used to divide the
12.288MHz clock to produce the various clock signals for the system. A PLL circuit is