LTDVE8CH– INSTRUCTIONS MANUAL
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GEN_WDT_CNT7
: pulse width setting for generator 8
GEN_WDT_CNT8
: pulse width setting for generator 9
GEN_WDT_CNT9
: pulse width setting for generator 10
GEN_WDT_CNT10
: pulse width setting for generator 11
GEN_WDT_CNT11
: pulse width setting for generator 12
GEN_WDT_CNT12
: pulse width setting for generator 13
GEN_WDT_CNT13
: pulse width setting for generator 14
GEN_WDT_CNT14
: pulse width setting for generator 15
GEN_WDT_CNT15
: pulse width setting for generator 16
Allowed values are in the range from 1 (default value) to 1023 (maximum value). Avoid operation
with non-allowed values.
According to the time base selected in register
GEN_WDT_BASE
[x] and the count set in
GEN_WDT_CNT
[x], the pulse width may be calculated using the following formula:
Width[x] [µs] = value(GEN_WDT_BASE[x]) * value(GEN_WDT_CNT[x])
The pulse width may range from 1 µs to 1,023,000 µs with variable absolute resolution.
Bit fields [15:10] of these registers are unused. When writing these bits, they must be set to zero.
14.2.13. Registers OUTPUT_SEL_HI[0:15]
The output multiplexers are used to route the internal signals to the light outputs and synchronization
outputs. Each output multiplexer has an independent selector.
The selector of a specific output multiplexer is a 25 bits binary number, split on a pair of contiguous
Modbus registers named
OUTPUT_SEL_HI
[x] and
OUTPUT_SEL_LO
[x].
Registers
OUTPUT_SEL_HI
[x] hold in bit fields [8:0] the nine high order bits of the selectors, while
registers
OUTPUT_SEL_LO
[x] hold the remaining sixteen low order bits of the selectors.
OUT_SEL_HI0
: upper nine bits of output multiplexer 1 selector (light LD1)
OUT_SEL_HI1
: upper nine bits of output multiplexer 2 selector (light LD2)
OUT_SEL_HI2
: upper nine bits of output multiplexer 3 selector (light LD3)
OUT_SEL_HI3
: upper nine bits of output multiplexer 4 selector (light LD4)
OUT_SEL_HI4
: upper nine bits of output multiplexer 5 selector (light LD5)
OUT_SEL_HI5
: upper nine bits of output multiplexer 6 selector (light LD6)
OUT_SEL_HI6
: upper nine bits of output multiplexer 7 selector (light LD7)
OUT_SEL_HI7
: upper nine bits of output multiplexer 8 selector (light LD8)
OUT_SEL_HI8
: upper nine bits of output multiplexer 9 selector (sync. output SH1)
OUT_SEL_HI9
: upper nine bits of output multiplexer 10 selector (sync. output SH2)
OUT_SEL_HI10
: upper nine bits of output multiplexer 11 selector (sync. output SH3)
OUT_SEL_HI11
: upper nine bits of output multiplexer 12 selector (sync. output SH4)
