96
Completion Flag
CNT 13
Count input, CP
(0000)
0000
0001
0002
0003
0000
0101
Present value
Reset input, R
(2003)
Start input, SI
(0002)
0149
ON for 1 scan
3-7-22
SHIFT REGISTER - SFT(33)
Wd: Shift word
Output bits, work bits, DR, LR
Operand Data Areas
Ladder Symbol
I
P
SFT(33)
Wd
R
A maximum of 16 SFT(33) instructions can be used in any one program.
SFT(33) is controlled by three execution conditions, I, P, and R. If SFT(33) is
executed and 1) execution condition P is ON and was OFF the last execution
and 2) R is OFF, then execution condition I is shifted into the rightmost bit of
a shift register defined between St and E, i.e., if I is ON, a 1 is shifted into the
register; if I is OFF, a 0 is shifted in. When I is shifted into the register, all bits
previously in the register are shifted to the left and the leftmost bit of the reg-
ister is lost.
Execution
condition I
Lost
data
Wd
The execution condition on P functions like a differentiated instruction, i.e., I
will be shifted into the register only when P is ON and was OFF the last time
SFT(33) was executed. If execution condition P has not changed or has gone
from ON to OFF, the shift register will remain unaffected.
When execution condition R goes ON, all bits in the shift register will be
turned OFF (i.e., reset to 0) and the shift register will not operate until R goes
OFF again.
The following example uses the 1-second clock pulse bit (0308) so that the
execution condition produced by 0005 is shifted into register DR 10 every
second.
Limitations
Description
Example 1:
Basic Application
Instruction Set
Section 3-7