Appendix E
Memory Map
129
Devices
Address
R/W
Contents
System
Default Value
Remarks
$9800
R
0
None
W
Control registers #1 and #3
$82
Writes to #3
$9801
R
Status register
None
W
Control register #2
$00
$9802
R
Higher byte of timer #1 counter
None
W
Higher byte (MSB) of buffer register
None
$9803
R
Lower byte (LSB) of buffer register
None
W
Lower byte of timer 1 latch
None
$980
4
R
Higher byte of timer #2 counter
None
W
Higher byte (MSB) of buffer register
None
$9805
R
Lower byte (LSB) of buffer register
None
W
Lower byte of timer #2 latch
None
$9806
R
Higher byte of timer #3 counter
None
W
Higher byte (MSB) of buffer register
None
Changes depend on
transfer rate
$9807
R
Lower byte (LSB) of buffer register
None
W
Lower byte of timer #3 latch
None
Address
R/W
Contents
System Default Value
$9000
R/W
1-second digit : 0 through 9
None
$9001
R/W
10-second digit : 0 through 5
None
$9002
R/W
1-minute digit : 0 through 9
None
$9003
R/W
10-minute digit : 0 through 5
None
$900
4
R/W
1-hour digit : 0 through 9
None
$9005
R/W
10-hour digit : 0 through 2
None
$9006
R/W
1-day digit : 0 through 9
None
$9007
R/W
10-day digit : 0 through 3
None
$9008
R/W
1-month digit : 0 through 9
None
$9009
R/W
10-month digit : 0 and 1
None
$900A
R/W
1-year digit : 0 through 9
None
$900B
R/W
10-year digit : 0 through 9
None
$900C
R/W
Week digit : 0 through 6
None
$900D
R/W
Control register D
0 is set in D0.
$900E
R/W
Control register E
None
$900F
R/W
Control register F
0 is set in D0, 1, and 3.
Note A 4.9152-MHz clock is supplied to the MPU and a 1.2288-MHz clock is supplied to the ACIA and PTM.
Summary of Contents for C500-ASC04
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