79
Timing Between PC and ASCII Unit Instructions
1 cycle
1 cycle
1 cycle
1 cycle
UM
Execution
End
Refresh
UM
Execution
End
Refresh
UM
Execution
End
Refresh
B
C
D
E
F
G
H
READ(88/190)
READ(88/190) READ(88/190)
WRIT(87/191) WRIT(87/191)
WRIT(87/191) WRIT(87/191)
EQ=1
EQ=1
EQ=1
EQ=1
EQ=1
EQ=1
EQ=0
PC
ASCII
UNIT
EXECUTABLE
YES
YES
YES
YES
YES
YES
NO
NO
Common Memory
is full
READ(88/190)
←
PC WRITE, WRIT(87/191)
→
PC READ
1
2
3
5
6
7
PC WRITE
PC WRITE
PC WRITE
PC READ
PC READ
PC READ
3. Waits until data previously written to the
common memory is written to the PC.
wait
wait
6. Waits until the data being read is transferred to
the common memory
No data in
common memory
A
READ(88/190)
End
Refresh
UM
Execution
X
X
1 cycle
1 cycle
1 cycle
1 cycle
UM
Execution
End
Refresh
UM
Execution
End
Refresh
UM
Execution
End
Refresh
UM
Execution
End
Refresh
K
L
M
N
O
PC
ASCII
UNIT
MOV(21/030)
(or OUT)
bit 08 to 15
MOV(21/030)
(or OUT)
bit 08 to 15
(Previous Data)
Same
Same
13 Data
PC GET
(previous
data)
PC
GET
K data
PC
GET
K data
PC PUT
13
MOV(21/030)
←
PC GET, MOV(21/030)
→
PC PUT
(Previous Data)
Same
13 Data
Timing Considerations
Summary of Contents for C500-ASC04
Page 1: ...C500 ASC04 ASCII Unit Operation Manual Revised February 2001 ...
Page 5: ...iv ...
Page 7: ...vi ...