62
PLS/PWM frequency setting
This setting determines the frequency of PLS/PWM pulses.
In this example, enter
「
K1000 (H3E8)
」
into shared memory addresses
148h and 149h, because pulse output starts at R2.8 and R2.9 (PLS0) at
10kHz. After pulse output starts by Start signal, enter
「
K0 (H0)
」
to
prepare for stopping pulse.
Shared memory 148h, 149h settings (before pulse starts)
Shared memory 148h, 149h settings (after pulse starts)
PLS0/PWM0 frequency setting
0
0
0
0
0
3
E
8
K 10000
Setting item
(bit) 32
Set value
16 15
0
Settings
PLS0/PWM0 frequency setting
0
0
0
0
0
0
0
0
K 0
Setting item
(bit) 32
Set value
16 15
0
Settings
When pulse frequency (speed) is changed when counter
current value coincides with set value via internal connection
of pulse output and counter, CMP output for PLSx, PWMx
should be set to same CH.
ATTENTION
