101
Shared Memory Area Setting Example
Setting
item
Shared
memory
address
Setting example
Setting range
PLS/
PWM
setting
140h to 141h
For each output (PLS0, PWM0 to PLS3,
PWM3) 4 bits are allocated.
PLS/PWM Setting range
PWM output
H00: Data change on rising edge of start
H1: Data change on rising edge of start,
or comparison output
H2: Data change on rising edge of start,
or data refresh
Pulse output (direction control mode)
H4: Data change on rising edge of start
H6: Data change on rising edge of start,
or comparison output
H8: Data change on rising edge of start,
or data refresh
Pulse output (individual output mode)
H5: Data change on rising edge of start
H7: Data change on rising edge of start,
or comparison output
H9: Data change on rising edge of start,
or data refresh
HF: Unused
32 16 15 0
F
F
F
F
F
F
0
0
PLS3
PWM3
PLS2
PWM2
PLS1
PWM1
PLS0
PWM0
H4: Pulse output (direction control mode)