70
Step 4. PWM control signal
●
After shared memory setting, Enable and Start signals are needed
to be controlled with PWM control signal.
Enable signal
→
Enable signal determines valid/stop of PWM output.
ON: PWM output valid
OFF: PWM output stop
Start signal
→
Start signal starts PWM output, and changes pulse frequency and
Duty.
Frequency can also be changed at the time of comparison
coincidence or data refresh, by Pulse output setting.
This signal is valid only when Enable signal is ON. It is invalid when
Enable signal is OFF.
When both Enable and Start signals are ON, pulse output is
permitted.
First ON of Start signal: PWM output start
Later OFF
→
ON edge: Change of output pulse frequency and Duty
●
Output allocation for each control signal is shown in the table
below.
Control signal allocation table
Output
Functions
Allocation
Pulse output CH
Control events
Remarks
R3.8
PWM0
Enable control
OFF: PWM output stop
ON: PWM output valid
R3.9
PWM1
R3.10
PWM2
R3.11
PWM3
R3.12
PWM0
Start control
First ON: PWM output start
OFF
→
ON edge: Output pulse frequency, Duty changed
R3.13
PWM1
R3.14
PWM2
R3.15
PWM3
• Same function is allocated to same location for pulse and
PWM control signal.
• On shared memory, PLS/PWM setting, PLS/PWM
frequency setting, and PWM Duty setting should be
arranged in the above order.
• If not, it may not work properly.
• When frequency or Duty is changed during PWM output,
new setting applies from the next waveform.
ATTENTION
PLS/PWM flag is prepared at shared memory addresses 142h and 143h. Pulse
output can be monitored by reading the flag in these addresses. See
"PLS/PWM
Flag" in Appendix B
for details.
NOTE
