2.3 Peripheral domains
Peripheral Domains
is an in-depth diagram of MPC5746R modules. Where
Tree
leaves off at the clock domain level,
Peripheral
Domains
picks up and progresses to the module level, shown below.
Figure 9. Peripheral domains
The clock domains are color-coded. Black lines are reserved for clock domains that only a few modules use. For example, the
FlexCAN module takes both
PBRIDGE_x_CLK
and
CAN_CLK
.
CAN_CLK
is black because only the FlexCAN uses that clock. As
a rule of thumb, clock domains are represented with black lines if all modules using it can fit within a single window without having
to scroll. The frequencies on this tab are not meant to be modified and are dependent on frequency values in the
Tree
tab.
2.4 LFAST clocking
The LFAST is a versatile, but intricate module. It supports its own PLL which generates multiple phases and generates a signal
within specification only if its inputs are certain frequencies. These intricacies make it necessary to give LFAST its own dedicated
tab.
Peripheral Domains
still hosts an LFAST clock that shows its input clocks and is hyperlinked to
LFAST Clocking
, as shown
in the following figure.
NXP Semiconductors
Clock calculator design
MPC574xR Clock Calculator Guide, Rev. 5, October 2018
Application Note
7 / 28
