Figure 6. Clock calculator tree
The flow of the diagram generally goes from left to right. On the left are the MPC5746R clock sources and on the right are the
clock domains. MCU modules run on one or more of these clock domains.
Clock domain frequency values are displayed in the outlined cells next to their labels. Most cells are not meant to be written to;
their values are dependent on the frequencies of preceding steps in the clock tree. Take
PER_CLK
, for example: its value is
sourced from either the IRCOSC, XOSC, or
PLL0_PHI
. Now look at the IRCOSC block. IRCOSC is at 16 MHz, but the frequency
that propagates depends on the next block,
IRCOSC
Source Controller
. Therefore, the actual input frequency received by blocks
that take IRCOSC as a source is the IRCOSC frequency of 16 MHz, filtered by the IRCOSC controller block. The same goes for
XOSC.
PLL0_PHI
is configured in the
PLL0
tab.
PER_CLK
selects from these three clock sources by selecting the value of the
AUX Clock Selector 0
block. Then finally the selected signal is divided by the
PER_CLK
prescaler value.
It is important to note, though, that the user input for the divider field is not the desired divider, but the bitfield value that one would
have to enter to achieve the desired divider. That is why the divider block says “/(1+(0…63))” rather than simply “/1…64”. The user
provides a value between 0 and 63, to which the hardware automatically adds 1 to calculate a divider that is between 1 and 64.
Each auxiliary clock and the system clock can feed into multiple domains that each have their own dividers. The number to the
left of the prescaler shows the number of the divider that is associated with that clock. In the case of
PER_CLK
, the number “0”
is shown next to the
PER_CLK
enable. This means that
PER_CLK
is configured by Divider 0 of Auxiliary Clock 0.
NXP Semiconductors
Clock calculator design
MPC574xR Clock Calculator Guide, Rev. 5, October 2018
Application Note
5 / 28
