Figure 36. CAN_CLK in Tree
XOSC and
PLL0_PHI
are already configured from the previous section, so there is no need to repeat those steps.
CAN_CLK
traces back to
AUX Clock Selector 8
, which currently follows the IRCOSC. Change
AUX Clock Selector 8
to follow XOSC.
Figure 37. CAN_CLK changed to follow XOSC
Next, enable
CAN_CLK
block and set the
PBRIDGEx_CLK
divider. Set the associated
Clk En
block to 1 and the
CAN_CLK
divider
to 0: 40 MHz/(0+1) = 40 MHz. So, in closing, this example has achieved its goal: a 40 MHz XOSC driving a PLL that produces
an output of 200 MHz, and from there the PLL running
PBRIDGE_x_CLK
at 50 MHz and the
CAN_CLK
at 40 MHz, sourced from
the XOSC. Finally, the
PBRIDGE_x_CLK
and
CAN_CLK
drive the FlexCAN module.
NXP Semiconductors
Clock tool example use sase: Configure FlexCAN to XOSC at 40 MHz protocol clock and PLL0 50 MHz BIU/Module clock
MPC574xR Clock Calculator Guide, Rev. 5, October 2018
Application Note
24 / 28
