Figure 19. FlexCAN clocks.
PBRIDGE_x_CLK
and
CAN_CLK
are currently 16 MHz and 0 MHz, respectively. Configuring the clock calculator can be done in
any order; this example will start with
PBRIDGE_x_CLK
.
3.1 Configure PBRIDGE_x_CLK
Click on
PBRIDGE_x_CLK
to forward to the
PBRIDGE_x_CLK
cell of
Tree
, as shown in the figure below.
Figure 20. PBRIDGE_x_CLK, Tree tab
Trace
PBRIDGE_x_CLK
all the way back to its point of origin. As shown in the above figure,
PBRIDGE_x_CLK
is enabled and
sourced from
System Clock Selector
, whose current value is 0. The cell is a drop-down menu and the textbox explains what each
available value represents. As shown in the figure,
PBRIDGE_x_CLK
is currently enabled and sourced from the 16 MHz IRCOSC,
divided by 1, for a final frequency of 16 MHz.
Since the only way to achieve 50 MHz is through the PLL, one of the PLLs must be configured. This example will choose PLL0.
Trace
PLL0_PHI
back to its own sources. PLL0 selects from either IRCOSC or XOSC via
AUX Clock Selector 3
. These oscillators
are the point of origin for all clock domains. The figure below shows the
PBRIDGE_x_CLK
being traced back to PLL0 and then
finally to the oscillators.
NXP Semiconductors
Clock tool example use sase: Configure FlexCAN to XOSC at 40 MHz protocol clock and PLL0 50 MHz BIU/Module clock
MPC574xR Clock Calculator Guide, Rev. 5, October 2018
Application Note
15 / 28
