Figure 30. When PLL0_PHI exceeds VCO and PLL spec
Now let’s configure the PLL correctly. Turn on the PLL in the
PLL0
tab by setting the
PLL0 Mode Control
block to 1, set
Prediv
to
2,
Multiplier
to 20, and
RFDPHI
to 2. As shown in the next figure, the output
PLL0_PHI
is 200 MHz and the cell remains unshaded,
meaning the configuration fits within spec.
Figure 31. PLL0_PHI configured to 200 MHz
Go back to
Tree
to observe that the
PLL0_PHI
frequency is now 200 MHz.
NXP Semiconductors
Clock tool example use sase: Configure FlexCAN to XOSC at 40 MHz protocol clock and PLL0 50 MHz BIU/Module clock
MPC574xR Clock Calculator Guide, Rev. 5, October 2018
Application Note
21 / 28
