Figure 28. PLL0_PHI reference table
The
PLL0 reference
field is the frequency of the PLL0 input, in this case the 40 MHz XOSC. Set the target frequency and PREDIV
values. This example will target 200 MHz and change PREDIV to 2. The values and shading in the lookup table will automatically
change to fit these new settings. In the figure below, the table has changed and circled are the modified settings.
Figure 29. PLL0_PHI table with new settings
The cells shaded green means there are two divider combinations that can achieve exactly 200 MHz given an input frequency of
40 MHz and a PREDIV of 2. This example will use a MFD of 20 and a RFD of 2, but before configuring the
PLL0
tab, it is worth
noting what happens if the output PLL frequency is out of range.
In the following figure, the PLL has been configured so that the output frequency is 5.08 GHz. This obviously exceeds the maximum
hardware spec of 400 MHz. The associated voltage controlled oscillator (VCO) frequency, which can be back-calculated from
PLL0_PHI
also exceeds the maximum VCO spec of 1250 MHz. Therefore, the output is crosshatched and shaded red.
NXP Semiconductors
Clock tool example use sase: Configure FlexCAN to XOSC at 40 MHz protocol clock and PLL0 50 MHz BIU/Module clock
MPC574xR Clock Calculator Guide, Rev. 5, October 2018
Application Note
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