USB, PCIe, and UFS
Jetson AGX Xavier Series Product
DG-09840-001_v2.5 | 47
Table 7-9.
USB 2.0 Signal Connections
Module Pin Name Type
Termination
Description
USB[3:0]_N/P
DIFF I/O
90Ω common-mode chokes close
to connector. ESD Protection
between choke and connector on
each line to GND
USB Differential Data Pair: Connect to USB
connector, Mini-Card Socket, Hub or
another device on the PCB.
Table 7-10.
USB 3.1 Signal Connections
Module Pin Name
Type
Termination
Description
UPHY_TX6_N/P (USB 3.1 Port #0)
UPHY_TX1_N/P (USB 3.1 Port #2)
UPHY_TX11_N/P (USB 3.1 Port #3)
DIFF Out
Series 0.1uF caps. Common-
mode chokes and ESD
protection if these are used.
USB 3.1 Differential Transmit
Data Pairs: Connect to USB 3.1
connectors, hubs or other devices
on the PCB.
UPHY_RX6_N/P (USB 3.1 Port #0)
UPHY_RX1_N/P (USB 3.1 Port #2)
UPHY_RX11_N/P (USB 3.1 Port #3)
DIFF In
If routed directly to a peripheral
on the board, AC caps are
needed for the peripheral TX
lines. Common-mode chokes
and ESD protection, if these are
used.
USB 3.1 Differential Receive Data
Pairs: Connect to USB 3.1
connectors, hubs or other devices
on the PCB.
Table 7-11.
Recommended USB Observation Test Points for Initial Boards
Test Points Recommended
Location
One for each of the USB 2.0 data lines (USBx_N/P)
Near Jetson AGX Xavier connector and USB device. USB
connector pins can serve as test points.
One for each of the USB 3.1 output lines used
(TXn_N/P)
Near USB device. USB connector pins can serve as test points
One for each of the USB 3.1 input lines (RXn_N/P)
Near Jetson AGX Xavier connector.
7.2
PCI Express
Jetson AGX Xavier provides 16 lanes that can be used for PCIe, USB 3.1, and UFS. See the
Jetson AGX Xavier USB 3.1, PCIe and UFS Lane Mapping Configurations table for details on
which are available for PCIe use. Root port is supported on all PCIe interfaces. Endpoint mode
is supported on Interface C5 only. Figure 7-4 shows all the PCIe interfaces configured as Root
Ports. Figure 7-5 shows C5 configured as an Endpoint.
