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Power

Jetson AGX Xavier Series Product

DG-09840-001_v2.5 | 31

Figure 5-13. VIN Loss Detection Circuit

TPS3808G01

SENSE

VCC

RST*

TP
GND

CT

MR*

5V_AO

VDDIN_PWR_BAD_N

RB521S30T1G

VDD_SRC

47.5k

Ω,1%

1nF

0.1uF

10nF

47.

5k

Ω

,1%

2.

49

k

Ω

,1%

10

0k

Ω

,1%

5.6.2

Power Monitor

Power monitors are provided on Jetson AGX Xavier. These monitor the

VDD_GPU, VDD_CPU

,

VDD_SOC

(Core),

VDD_CV, VDD_DDRQ,

and

SYS_VIN_MV

Supplies. The monitors will toggle a WARN

(Warning) or CRIT (Critical) output, depending on the power “seen” at the sense resistors and
the thresholds set for each supply. This output is connected to the SOC_GPIO7 pin. The I2C
address for the top power monitor (GPU/CPU/SOC) is 7’H40, and for the bottom power monitor
(CV, VDDRQ, SYS_VIN_MV) is 7’H41).

Figure 5-14. Power Monitor

Sense

Resistors

I2C_GP2_DAT

I2C_GP2_CLK

INA3221AQRGVRQ1

Power Monitor

GPU_INA_P

0.005Ω, 1%

0805

0.1uF

GPU_INA_M

VIN_SYS_5V0

GPU Supply Monitor

CPU Supply Monitor

SOC Supply Monitor

CPU_INA_P

0.005Ω, 1%

0805

CPU_INA_M

SOC_INA_P

0.005Ω, 1%

0805

SOC_INA_M

20

Ω

20

Ω

20

Ω

20

Ω

20

Ω

20

Ω

VIN1P

VIN1N

WARN
CRIT

VS

AO
PV

TC

VPU
GND

SCL

SDA

PAD

VIN2P

VIN2N

VIN3P

VIN3N

SoC

SOC_GPIO7

SYS_VIN_HV

SYS_VIN_HV

VDD_SYS_CPU_IN

(CPU supply input)

VDD_SYS_GPU_IN

(GPU supply input)

VDD_SYS_SOC_IN

(SOC supply input)

SYS_VIN_HV

1uF

1uF

1uF

Sense

Resistors

INA3221AQRGVRQ1

Power Monitor

CV_INA_P

0.005Ω, 1%

0805

0.1uF

CV_INA_M

VIN_SYS_5V0

CV Supply Monitor

VDDRQ Supply Monitor

System 5V Supply Monitor

VDDRQ_INA_P

0.005Ω, 1%

0805

VDDRQ_INA_N

SYS5V_P

0.005Ω, 1%

0805

SYS5V_N

20

Ω

20

Ω

20

Ω

20

Ω

20

Ω

20

Ω

VIN1P

VIN1N

VS

AO
PV

TC

VPU
GND

SCL

SDA

PAD

VIN2P

VIN2N

VIN3P

VIN3N

SYS_VIN_HV

SYS_VIN_HV

VIN_SYS_DDRQ_IN

(DDRQ supply input)

VDD_SYS_CV_IN

(CV supply input)

VDD_SYS_5V0

(SYS_VIN_MV input)

SYS_VIN_MV

1uF

1uF

1uF

100k

Ω

VDDIO_AO_1V8

VMON

Level

Shifter

10k

Ω

10k

Ω

665k

Ω

665k

Ω

665k

Ω

665k

Ω

665k

Ω

665k

Ω

WARN
CRIT

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Summary of Contents for Jetson AGX Xavier Series

Page 1: ...DG 09840 001_v2 5 December 2021 Jetson AGX Xavier Series Product Design Guide...

Page 2: ...nector option for carrier board Power Updated Power and System Pin Desc table and full table Updated Usage columns Updated pin type column Corrected title of Table 8 Added SYS_VIN_HV Input and simplif...

Page 3: ...klist Added pull up on OVERTEMP_N Updated terminations for GPIO30 Added power jack option to Carrier Board Supplies section Removed AC caps for UFS Updated pin types for UPHY 9 8 February 20 2019 Powe...

Page 4: ...sistors on I2C for M 2 sockets 2 1 July 27 2020 Update Table 2 1 to C5 only supports EP Added Chapter 4 on reference design considerations Added DV Dt section Section 5 5 1 including optional disable...

Page 5: ...Figure 7 3 Added note to clarify PCIe clock output and RFCLK input signaling type to Figure 7 4 Added insertion loss S parameter plot figure Figure 7 6 Updated Table 10 5 based on new guidelines from...

Page 6: ...tion to connect ID pin to generic GPIO and added related note Added note under USB Micro AGB connection recommending load switch with current protection be used Updated pin description types for 3 3V...

Page 7: ...put 22 5 4 Power On 22 5 4 1 Power On No MCU 22 5 4 1 1 Auto Power On Option No MCU 23 5 4 2 Power Button Supervisor MCU Power On 24 5 4 2 1 Defined behaviors 25 5 4 2 2 Power OFF Power ON Power Butto...

Page 8: ...9 2 HDMI 69 Chapter 10 Video Input 77 10 1 MIPI CSI 77 10 1 1 CSI D PHY Design Guidelines 87 10 1 2 CSI C PHY Mode Design Guidelines 88 10 2 SLVS Camera Interface 89 10 2 1 SLVS Design Guidelines 92...

Page 9: ...delines 127 19 1 1 Via Count and Trace Width 127 19 1 2 Via Placement 127 19 1 3 Via Placement and Power and Ground Corridors 127 19 2 Connecting Vias 129 19 3 Trace Guidelines 129 19 3 1 Layer Stack...

Page 10: ...Jetson AGX Xavier Series Product DG 09840 001_v2 5 x Chapter 23 USB SS and Wireless Coexistence 139 23 1 Mitigation Techniques 139 Chapter 24 Jetson AGX Xavier Pin Description 141...

Page 11: ...ence Auto Power On Case 27 Figure 5 11 Power On to OFF Power Button Held Low 10 Seconds 28 Figure 5 12 Power Discharge 30 Figure 5 13 VIN Loss Detection Circuit 31 Figure 5 14 Power Monitor 31 Figure...

Page 12: ...ebug UART Header Connections 117 Figure 15 3 Example Buffer Between Pin Associated with SoC Strap and Connected Device 120 Figure 15 4 Boundary Scan Connections 120 Figure 15 5 Safety MCU Connections...

Page 13: ...UFS 37 Table 7 3 NVHS for PCIe x8 Data Lan Pin Descriptions 38 Table 7 4 PCIe Clock and Control Pin Descriptions 39 Table 7 5 UFS and Miscellaneous USB Control Pin Descriptions 40 Table 7 6 USB 3 1 PC...

Page 14: ...e 10 9 Miscellaneous MIPI Camera Connections 89 Table 10 10 Recommended CSI Observation Test Points for Initial Boards 89 Table 10 11 Jetson AGX Xavier SLVS EC Camera Pin Description 89 Table 10 12 SL...

Page 15: ...UART4_RX Routing Requirements 112 Table 13 13 Jetson AGX Xavier CAN Pin Description 112 Table 13 14 CAN Interface Signal Routing Requirements 113 Table 13 15 CAN Signal Connections 113 Table 14 1 Jets...

Page 16: ...pplies to any of the Jetson AGX Xavier series of modules including Jetson AGX Xavier Industrial JAXi except where explicitly noted Refer to the following documents or models listed for more informatio...

Page 17: ...erface I2C Inter IC I2S Inter IC Sound Interface LDO Low Dropout voltage regulator LPDDR4x Low Power Double Data Rate DRAM Fourth generation PCIe PEX Peripheral Component Interconnect Express interfac...

Page 18: ...tegory Function USB USB 2 0 x4 USB 3 1 Up to x3 PCIe x5 x1 Root Port or Endpoint and x4 Root Port only Camera CSI 6x2 or 4x4 D PHY and C PHY Display HDMI DP up to x3 see note HPD x3 CEC x1 DP_AUX DDC...

Page 19: ...LK 2x GPIOs1 Xavier SoC Thermal Sensor DP_AUX 3x Power Subsystem PMIC Regulators Power Voltage Monitors DMIC x4 DSPK x2 CAN 2x UFS x1 PCIe 2 x1 1x2 1 x4 1 x82 SPI 3x1 PWM 4x AUD_MCLK UFS CLK RST SYS_V...

Page 20: ...RSVD GND 19 UPHY_RX4_N GND UPHY_RX5_P GND RSVD GND 20 GND UPHY_RX2_N GND UPHY_RX3_P GND PEX_CLK3_P 21 GND UPHY_RX2_P GND UPHY_RX3_N GND PEX_CLK3_N 22 UPHY_RX0_P GND UPHY_RX1_N GND PEX_CLK4_N GND 23 UP...

Page 21: ..._ALERT_N 62 GPIO10 GPIO08 GND SPI2_MISO GND GND 63 GND SYS_VIN_HV SYS_VIN_HV GND SYS_VIN_HV SYS_VIN_HV 64 SYS_VIN_HV SYS_VIN_HV SYS_VIN_HV SYS_VIN_HV 65 SYS_VIN_HV SYS_VIN_HV SYS_VIN_HV SYS_VIN_HV Leg...

Page 22: ...CSI6_CLK_N GND VM_I2C_DAT 46 GND CSI6_D1_P GND HDMI_DP0_TX3_P GND 47 CSI4_D0_N GND HDMI_DP0_TX2_P HDMI_DP0_TX3_N VM_INT_N 48 CSI4_D0_P HDMI_DP0_TX0_N HDMI_DP0_TX2_N GND UART4_RX RSVD 49 GND HDMI_DP0_T...

Page 23: ...nter Line 22 00 8 00 22 00 64 70 7 91 7 65 Molex 2034560003 5 5mm 2048430001 2 5mm Mirrored Pinout Pin A3 in Carrier Board Symbol See 699 Pin Connector Pin Orientations figure Pin A3 in Molex Specific...

Page 24: ...is mirrored such that the pin numbers match when the module and carrier board connectors are mated See the following figure The orientation shown matches the carrier board in the upright position as w...

Page 25: ...er board and the bottom plate Figure 3 3 5 5 mm Height on Carrier Board Molex Part 2034560003 Connector Module TTM Module Bottom Plate Module PCB Carrier Board PCB Standoffs 8 00 0 15mm See Note 4 00...

Page 26: ...03 5 5 mm height 8 00 0 15 mm board to board spacing case For this case a standoff height of 4 5 mm is recommended This is based on a standoff with 0 13 mm height tolerance The tolerance for the botto...

Page 27: ...7 0 32 4 85 3 8 1 05 1 63 0 58 4 85 4 2 0 65 1 37 0 72 4 85 4 2 0 65 1 63 0 98 5 15 3 8 1 35 1 37 0 02 5 15 3 8 1 35 1 63 0 28 5 15 4 2 0 95 1 37 0 42 5 15 4 2 0 95 1 63 0 68 Connector sweep range Fro...

Page 28: ...ome parallel as the mating process progresses To remove the Jetson AGX Xavier Series module correctly follow the following sequence and mounting hardware instructions 1 The PCB design needs to have en...

Page 29: ...ign must be followed exactly and the firmware provided must be used to ensure correct functionality USB Type C PD Controller Designs that intend to follow the NVIDIA carrier board design and include t...

Page 30: ...seful on a custom design A similar function may be desired for a custom design but the NVIDIA software will not interact with these devices and the I2C address used by the developer kit carrier board...

Page 31: ...Input Voltage Range 1 65V 5 5V Output Voltage Range See Note 4 L62 CARRIER_ POWER_ON Carrier Power On Used as part of the power up sequence When asserted it is safe for the carrier board to power up 1...

Page 32: ...ule that the VDD_IN power is not valid Carrier board should de assert this drive high only when SYS_VIN_HV MV have reached the required voltage levels and are stable This prevents SoC from powering up...

Page 33: ...PU 5 0V PU 1 8V PU 1 8V PU 1 8V L63 A3 PU 3 3V PU Always ON 3 3V Multiple Multiple Voltage Monitors L44 Safety MCU VM_I2C L45 Mux VM_INT_N L47 JAXi Only PWR_I2C K40 H40 Module ID pins 5 1 Supply Allo...

Page 34: ...D1 Temp Sensor VDD 5 Enable RUN2 pin for VDD_DDRQ supply and Enable for discharge of DDR_VDD2_1 1V VDDIO_SYS_1V8HS SYS_1V8LS AO_1V8 rails 5 2 Power Sequencing The following list describes the basic po...

Page 35: ...board is required to power off the supplies associated with the module Once the carrier board power supplies are adequately powered off the MODULE_POWER_ON signal can be de asserted which starts the...

Page 36: ...le Power SYS_RESET_N MODULE_POWER_ON SYS_VIN_MV VIN_PWR_ON Note SYS_VIN_MV must go below 100 mV before system can be powered on again Figure 5 4 Power Down Sequence Uncontrolled Case CARRIER_POWER_ON...

Page 37: ...from Cypress Figure 5 5 Simplified DC Jack Power Connections DC Jack G S D PWR FET 100k 1 LB 30 LB 30 LB 30 10k 1 G S D PWR FET VCC_SRC_FET 10k 1 10k 1 G D S FET 221 1 G D S FET 10k 1 100k 1 10k 1 VC...

Page 38: ...KR SC70 SN74LVC1G17 SC70_BUFF SN74LVC1G07 GW DCKRE4 SC70_5 RB521S30T1G RB521S30T1G 1uF 20k 1 100k 1 To Module Pin L54 To Module Pin L61 100k VDD_5V Optional ACOK circuit See note Notes 1 To support au...

Page 39: ...perform this function is the EFM8SB10F8G A QFN20 from Silicon Labs Note Designs that intend to follow the NVIDIA carrier board design and include the EFM8SB10F8G A QFN20 MPU for Button Power Button c...

Page 40: ...odule Pin L61 To Module Pin L60 Used tooptinally enable Auto Power On 5 4 2 1 Defined behaviors For all actions triggered by BUTTON_POWER_ON there will be a de bounce time before triggering any output...

Page 41: ...ng edge 80 ms T_CPO Maximum allocated delay to CARRIER_POWER_ON assertion 10 ms 5 4 2 3 Power OFF Power ON Auto Power On Case When the user connects the main power source the MCU sends the power enabl...

Page 42: ...Delay from ACOK detected high with main power source applied to first rail ON de bounce only 20 ms T_MPO_AC MODULE_POWER_ON active delay from VIN_PWR_ON rising edge 80 ms T_CPO_AC Maximum allocated d...

Page 43: ...discharge circuitry is required Figure 5 12 shows a simplified version of what is in the P2822 Jetson AGX Xavier carrier board The DISCHARGE signal is generated based on a transition of the CARRIER_PO...

Page 44: ...ill be lowest when the input voltage is near the maximum Modifications to the DV Dt circuit include two options shown in Figure 5 12 Remove the resistor in series with VDDIN_PWR_BAD_N which would disa...

Page 45: ...needs to be discharged NTS4001 NT1G G S D NTS4001 NT1G VDD_5V VIN_PWR_ON 0 0 05 Tol DV Dt Droop Allowance Tuning Disables DV Dt circuit if removed Note The resistor values in the discharge circuit for...

Page 46: ...QRGVRQ1 Power Monitor GPU_INA_P 0 005 1 0805 0 1uF GPU_INA_M VIN_SYS_5V0 GPU Supply Monitor CPU Supply Monitor SOC Supply Monitor CPU_INA_P 0 005 1 0805 CPU_INA_M SOC_INA_P 0 005 1 0805 SOC_INA_M 20 2...

Page 47: ...N Wake26 Ethernet RX Control RGMII_RX_CTL RGMII_RX_CTL Wake28 Power On POWER_ON POWER_BTN_N Wake29 GPU Fault GPU_FAULT GPIO01 Wake30 I2C General Purpose 1 Data I2C_GP1_DAT I2C1_DAT Wake31 PCIe L5 Cloc...

Page 48: ...g Detect DP0_HPD DP0_HPD Wake60 USB VBUS Enable 0 USB_VBUS_EN0 GPIO22 Wake61 USB VBUS Enable 1 USB_VBUS_EN1 GPIO23 Wake62 DP 1 Hot Plug Detect DP1_HPD DP1_HPD Wake63 PCIe L3 Clock Request PEX_L3_CLKRE...

Page 49: ...have the underscore N _N after the signal names For example SDCARD_CMD indicates an active high signal Differential signals are identified as a pair with the same names that end with _P and _N just P...

Page 50: ...entions Throughout this design guide the following signal routing conventions are used SE Impedance Diff Impedance at x Dielectric Height Spacing Single ended SE impedance of trace along with differen...

Page 51: ...f one signal is routed 254 mm on outer layer and second signal is routed 254 mm in inner layer difference in flight time between two signals will be 300 ps That is a big difference if required matchin...

Page 52: ...from Jetson AGX Xavier Input is to Jetson AGX Xavier Bidir is for Bidirectional signals Table 7 2 UPHY Data Lane Pin Descriptions USB 3 1 PCIe and UFS Pin Module Pin Name SoC Signal Usage Description...

Page 53: ...y E Connector H16 UPHY_TX7_P PEX_TX7_P J15 UPHY_TX8_N PEX_TX8_N UPHY Transmit 8 PCIe x2 controller 4 lane 0 Unused J14 UPHY_TX8_P PEX_TX8_P G14 UPHY_TX9_N PEX_TX9_N UPHY Transmit 9 PCIe x2 controller...

Page 54: ...r Output PCIe Diff Pair E15 PEX_CLK0_P PEX_CLK0P E11 PEX_L0_ CLKREQ_N PEX_L0_ CLKREQ_N PCIe 0 Clock Request for controller 0 Pulled to 3 3V through 47k resistor on module Input Open Drain 3 3V D10 PEX...

Page 55: ...esistor on module PCIe x16 Connector and M 2 Key E and Connector Input Open Drain 3 3V Notes 1 In the Type Dir column Output is from Jetson AGX Xavier Input is to Jetson AGX Xavier Bidir is for Bidire...

Page 56: ...overy mode Figure 7 1 Simple USB Type A Connection Example Jetson AGX Xavier SoC USB 2 0 USB 3 1 PCIe UFS USB1_DP USB1_DN C11 C10 PEX_TX6_P PEX_TX6_N PEX_RX6_P PEX_RX6_N K17 K16 B16 B17 GPIO22 USB1_P...

Page 57: ...100k 100k SWD_CLK SWD_IO XRES 5V_AO Test Points for Firmware Programming Figure 7 3 USB 3 1 USB Micro AB Connection Example Jetson AGX Xavier SoC USB 2 0 USB0_DP USB0_DN F12 F13 GPIOx GPIO10 GPIO22 U...

Page 58: ...ce impedance is recommended 2 Up to 4 signal Vias can share a single GND return Via 3 CMC Common Mode Choke SW Analog Switch 4 Adjustments to the USB drive strength slew rate termination value setting...

Page 59: ...eakout Region Max length 11 mm Minimum trace width and spacing Max Trace Length GEN1 Host GEN1 Device GEN2 Host or Device 152 1014 50 8 234 127 850 mm ps Stripline 6 7ps mm assumed Max Intra Pair Skew...

Page 60: ...uppression It can also reduce the limit of the pair pair distance Review needed NEXT FEXT check if via placement does not use Y pattern GND via Place GND via as symmetrically as possible to data pair...

Page 61: ...of Flexible Printed Circuit Board The FPC routing should be included for PCB trace calculations max length etc Characteristic Impedance Same as PCB Loss characteristic Strongly recommend to be same a...

Page 62: ...d AC caps are needed for the peripheral TX lines Common mode chokes and ESD protection if these are used USB 3 1 Differential Receive Data Pairs Connect to USB 3 1 connectors hubs or other devices on...

Page 63: ...0 1uF 0 1uF 0 1uF 0 1uF PCIe x4 I F C0 Used for M 2 Key M Connector on Carrier Board PCIe x1 I F C3 Used for M 2 Key Eon Carrier Board PCIe x8 I F C5 or SLVS Used for PCIe x16 connector on Carrier Bo...

Page 64: ...Control for PCIe I F C5 PCIe x16Connector on Carrier Board NVHS0_RX0_N P NVHS0_TX0_N P NVHS0_RX3_N P _ NVHS0_TX3_N P NVHS0_RX5_N P NVHS0_TX5_N P NVHS0_RX4_N P NVHS0_TX4_N P NVHS0_RX1_N P NVHS0_TX1_N...

Page 65: ...budget for carrier board routing Routing direct to device Routing to PCIe M 2 connector 14 5 10 5 dB in 4GHz See TBD Loss GEN3 budget module end device 22dB 3 5 dB 4dB Loss GEN3 budget module end dev...

Page 66: ...ended Keep critical PCIe traces such as PEX_TX RX TERMP etc away from other signal traces or unrelated power traces areas or power supply components Notes 1 The PCIe spec has 40 60 absolute min max tr...

Page 67: ...USB PCIe and UFS Jetson AGX Xavier Series Product DG 09840 001_v2 5 52 Figure 7 6 Insertion Loss S Parameter Plot SDD21...

Page 68: ...gnals 4x 4x 4x Dielectric TX and RX should not be routed on the same layer If this is required in a design they should not be interleaved and the spacing between the closest RX and TX lanes must be 9x...

Page 69: ...3 1 Guidelines Miscellaneous GND fill rule Remove unwanted GND fill that is either floating or act like antenna Connector Voiding Void all layers of golden finger area under the pad 5 7 mils larger t...

Page 70: ...M 2 connector Stripline Microstrip 357 2463 328 1939 254 1750 233 1378 in ps Mid loss PCB of 1 47dB in Microstrip or 1 35dB in Stripline is used Also 6 9ps mm for Stripline routing and 5 9ps mm for Mi...

Page 71: ...gh AC caps PEX_CLK5_P N DIFF OUT Differential Reference Clock Output Unused when interface C5 is used as Endpoint PEX_L5_CLKREQ_N I O 47K pullup on module to VDDIO_AO_3V3 PEX Clock Request for PEX_CLK...

Page 72: ...7 UFS Interface Signal Routing Requirements Parameter Requirement Units Notes Specification Max Rate HS GEAR1 A Series B Series HS GEAR2 A Series B Series HS GEAR3 A Series B Series 1248 1457 6 2496 2...

Page 73: ...m Longer via stubs would require review Discontinuity Voiding Voiding the plane directly under the pad 5 7 mils larger than the pad size is recommended General Keep critical PCIe traces such as PEX_TX...

Page 74: ...S_RD3 Ethernet Receive data bit 3 Ethernet PHY Input CMOS 1 8V D5 RGMII_RX_CTL EQOS_RX_CTL Ethernet Receive Control Ethernet PHY Input CMOS 1 8V C5 RGMII_RXC EQOS_RXC Ethernet Receive Clock Ethernet P...

Page 75: ...1V8LS E7 E6 J5 H5 VDD_1V8 10k 1 5k 2 2k TX_CLK TXD0 TXD1 TXD2 TXD3 TX_CTRL RX_CLK RXD0 RXD1 RXD2 RXD3 RX_CTRL MDC MDIO RESET INT MDI_0P MDI_0N MDI_1P MDI_1N MDI_2P MDI_2N MDI_3P MDI_3N GBE_MDI0 GBE_MD...

Page 76: ...er signal Isolation of TX and RX groups One of the following options for TX signal and RX signal groups 1 GND shielding from each other or 2 5x spacing from each other or 3 Routed on separate layers f...

Page 77: ...iver RGMII_RX_CTL I RGMI Receive Control Connect to RXDV pin on GbE Transceiver RGMII_MDC O MDC Connect to MDC pin on GbE Transceiver RGMII_MDIO I O 2 2k pull up to VDD_1V8 MDIO Connect to MDIO pin on...

Page 78: ...Drain 1 8V 3 3V tolerant DDC I2C F52 DP0_AUX_CH_P DP_AUX_CH0_P DisplayPort 0 Aux or HDMI DDC SCL K52 DP0_HPD DP_AUX_CH0_HPD DisplayPort HDMI 0 Hot Plug Detect Input CMOS 1 8V A48 HDMI_DP1_TX0_N HDMI_...

Page 79: ...22 reference design 2 In the Type Dir column Output is from Jetson AGX Xavier Input is to Jetson AGX Xavier Bidir is for Bidirectional signals 3 The direction shown in this table for DPx_HPD is true w...

Page 80: ...XDN2 HDMI_DPx_TXDP3 HDMI_DPx_TXDN3 DP_AUX_CHx_P DP_AUX_CHx_N EDP HDMI_DPx DP_AUX_CHx_HPD eDP DP Connector LN2 LN2 HPD 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF LN1 LN1 LN0 LN0 LN3 LN3 AUX AUX 2 lane 4 lane Level...

Page 81: ...UI HBR2 HBR RBR 5 4 185 2 7 370 1 62 617 Gbps ps Per data lane Number of Loads Topology 1 load Point Point Differential Unidirectional Termination 100 On die at TX RX Electrical Specification Inserti...

Page 82: ...pline Microstrip 3x 5x dielectric Max Intra pair within pair Skew 0 15 1 mm ps Do not perform length matching within breakout region Do trace length matching before hitting discontinuity i e matching...

Page 83: ...tandard DP Connector Voiding requirement is stack up dependent For typical stack ups voiding on the layer under the connector pad is required to be 5 7mil larger than the connector pad General Keep cr...

Page 84: ...annels Connect to AUX_CH on display connector DPx_HPD I DP eDP Hot Plug Detect Connect to HPD pin on display connector Table 9 5 Recommended DP and eDP Observation Test Points for Initial Boards Test...

Page 85: ...IN OUT AUDIO_HV DAP6_FS A58 4 7k 5V0_HDMI_EN 100k See Note 1 Notes 1 The load switch circuit shown is intended to remove power to the HDMI connector and related circuitry to avoid backdrive on signals...

Page 86: ...0 MHz between pull downs and FET are required for Standard Technology through hole designs and recommended for HDI designs 3 The trace after the main route via should be routed on the top or bottom la...

Page 87: ...ased on this characteristic The length constraint must be re defined if the loss characteristic is changed Trace spacing Pair Pair Stripline Microstrip pre 1 4b Microstrip 1 4b 2 0 3x 4x 5x to 7x diel...

Page 88: ...n the BOTTOM in order to avoid via stub effect Equal spacing 0 8mm between adjacent signal vias The x axis distance between signal and GND via should be 0 6mm Max of Vias PTH vias Micro Vias 4 if all...

Page 89: ...id size SMT area 1x dielectric height keepout distance Pull down Resistor RPD choke FET Value 500 Location Must be placed after AC cap Layer of placement Same layer as AC cap The FET and choke can be...

Page 90: ...MI connector Void GND PWR void under above the RS device is needed Void size SMT area 1x dielectric height keepout distance Connector Connector Voiding Voiding the ground below the signal lanes 0 1448...

Page 91: ...eference schematics for details HDMI Consumer Electronics Control Connect to CEC on HDMI Connector through circuitry DPx_AUX_CH_N P I OD From Jetson AGX Xavier to Connector 10k PU to 3 3V level shifte...

Page 92: ...Trio supports up to 1 7 Gsps Note Maximum data rate may be limited by use case and memory bandwidth Table 10 1 Jetson AGX Xavier CSI Pin Description Pin Module Pin Name SoC Signal Usage Description U...

Page 93: ...F46 CSI3_CLK_P CSI_D_CLK_P Camera CSI 3 DPHY Clock CPHY 30 C E44 CSI3_D0_N CSI_D_D0_N Camera CSI 3 DPHY Data 0 CPHY 30 B E45 CSI3_D0_P CSI_D_D0_P Camera CSI 3 DPHY Data 0 CPHY 30 A G45 CSI3_D1_N CSI_...

Page 94: ...a 1 CPHY 61 B H46 CSI6_D1_P CSI_G_D1_P Camera CSI 6 DPHY Data 1 CPHY 61 A B46 CSI7_CLK_N CSI_H_CLK_N Camera CSI 7 DPHY Clock CPHY 71 C B45 CSI7_CLK_P CSI_H_CLK_P Camera CSI 7 DPHY Clock CPHY 70 C A45...

Page 95: ...16 DAP5_DOUT GPIO Digital Speaker Output Data Camera Connector Camera 1 Reset K49 GPIO25 SOC_GPIO50 GPIO Camera Connector VDD_SYS Enable F56 GPIO36 SOC_GPIO53 GPIO Camera AVDD Enable L49 UART4_CTS UAR...

Page 96: ...I_7_D1_P N CSI_0_CLK_P N Clk Clk CSI_1_CLK_P N Clk CSI_2_CLK_P N Clk Clk CSI_3_CLK_P N Clk CSI_4_CLK_P N Clk Clk CSI_5_CLK_P N CSI_6_CLK_P N1 Clk Clk CSI_7_CLK_P N1 Notes 1 Each 2 lane option shown in...

Page 97: ...CSI_2_CLK_N CSI_2_D1_P N 2 1 CSI_3_CLK_P CSI_3_D0_P N 3 0 CSI_3_CLK_N CSI_3_D1_P N 3 1 CSI_4_CLK_P CSI_4_D0_P N 2 4 0 CSI_4_CLK_N CSI_4_D1_P N 4 1 CSI_5_CLK_P CSI_5_D0_P N 5 0 CSI_5_CLK_N CSI_5_D1_P N...

Page 98: ...N CSI_1_D1_P N 1 1 CSI_2_CLK_P CSI_2_D0_P N 1 2 0 CSI_2_CLK_N CSI_2_D1_P N 2 1 CSI_3_CLK_P CSI_3_D0_P N 3 0 CSI_3_CLK_N CSI_3_D1_P N 3 1 CSI_4_CLK_P CSI_4_D0_P N 2 4 0 CSI_4_CLK_N CSI_4_D1_P N 4 1 CSI...

Page 99: ...T SOC_GPIO41 EXTPERIPH2_CLK AUDIO UART4_CTS SOC_GPIO50 DAP5_SCLK Camera2 Clock UART4_TX CONN E53 J54 L49 H53 F10 H55 L5 F9 EDP K49 CameraAVDD Enable CAM1 MCLK CAM2_MCLK04 CAM0 Powerdown CAM0 Reset CAM...

Page 100: ...CSI3_D0_P CSI3_D1_N CSI3_D1_P CSI4_CLK_N CSI4_CLK_P CSI4_D0_N CSI4_D0_P CSI4_D1_N CSI4_D1_P CSI5_CLK_N CSI5_CLK_P CSI5_D0_N CSI5_D0_P CSI5_D1_N CSI5_D1_P CSI6_CLK_N CSI6_CLK_P CSI6_D0_N CSI6_D0_P CSI6...

Page 101: ...CSI_D_CLK_N CSI_E_D0_P CSI_E_D0_N CSI_E_CLK_P CSI_E_D1_P CSI_E_D1_N CSI_E_CLK_N CSI_F_D0_P CSI_F_D0_N CSI_F_CLK_P CSI_F_D1_P CSI_F_D1_N CSI_F_CLK_N CPHY_00_A CPHY_00_B CPHY_00_C CPHY_01_A CPHY_01_B CP...

Page 102: ...d 90 100 45 50 Via proximity Signal to reference 3 8 24 mm ps See Note 1 Trace spacing Microstrip Stripline 2x 2x dielectric Max Insertion loss 1 Gbps 1 5 Gbps 2 5 Gbps 3 10 2 96 2 17 dB Max trace del...

Page 103: ...250 150 mm Max Intra Trio Skew Within Trios 3 ps A or B pin to C pin skew Max Inter Trio Skew between Trios 55 ps Routing Layer Restrictions A trio must route completely on the same layer This means t...

Page 104: ...Enable Connect to appropriate analog camera supply Table 10 10 Recommended CSI Observation Test Points for Initial Boards Test Points Recommended Location One per signal line Near Jetson AGX Xavier pi...

Page 105: ...7_N PCIe SLVS Receive Lane 7 A30 NVHS0_SLVS_RX7_ P NVHS0_RX7_P C55 GPIO18 SOC_GPIO40 SLVS Horizontal sync PCIe x16 Connector Output CMOS 1 8V 3 3V tolerant K56 GPIO19 SOC_GPIO43 SLVS Vertical Sync Out...

Page 106: ...CAM SOC_GPIO40 SPI2_SCK SPI2_MOSI SPI2_MISO SPI2_CS0_N SOC_GPIO43 CAM_I2C_SCL CAM_I2C_SDA C55 K56 E61 F60 D62 F53 E53 AO SLVS Imager Connector SLVS_DX0_N SLVS_DX0_P SLVS_DX1_N SLVS_DX1_P SLVS_DX2_N SL...

Page 107: ...eturn Loss SDD11 0GHz 1 25GHz 2 5GHz 5 0GHz 25 18 15 10 dB Max Crosstalk PSFEXT 0GHz 1 25GHz 2 5GHz 5 0GHz 50 50 45 45 dB Reference plane GND Trace Impedance Diff pair Single Ended 85 15 Trace spacing...

Page 108: ...LVS device connector CLK to CLK MOSI to MOSI and MISO to MISO I2C3_CLK I2C3_DAT I OD I OD I2C 3 Optional alternative control interface Connect to matching pins of SLVS device connector instead of SPI...

Page 109: ...MMC1_CMD SD Card or SDIO Command Bidir E8 SDCARD_D0 SDMMC1_DAT0 SD Card or SDIO Data 0 F8 SDCARD_D1 SDMMC1_DAT1 SD Card or SDIO Data 1 A4 SDCARD_D2 SDMMC1_DAT2 SD Card or SDIO Data 2 D6 SDCARD_D3 SDMM...

Page 110: ...the receiver and maintain signal quality and meet requirements for the frequencies supported by the design 2 Supply load switch etc used to provide power to the SD Card must be current limited if the...

Page 111: ...se value Drive Type A 33 UHS50 Card optional UHS104 Card mandatory B 50 UHS50 Card mandatory UHS104 Card mandatory C 66 UHS50 Card optional UHS104 Card mandatory D 100 UHS50 Card optional UHS104 Card...

Page 112: ...ECT pin on socket if required GPIO21 SDCARD_VDD_EN O SDIO Supply Load Switch Enable Connect to enable of supply load switch supplying VDD on SD Card socket Note EMI ESD may be required for SDIO when u...

Page 113: ...T Audio Bidir F6 I2S2_DIN DAP2_DIN I2S Audio Port 2 Data In BT Audio Input F5 I2S2_DOUT DAP2_DOUT I2S Audio Port 2 Data Out BT Audio Output E4 I2S2_FS DAP2_FS I2S Audio Port 2 Left Right Clock BT Audi...

Page 114: ...r Bidir is for Bidirectional signals 2 The direction indicated for MCLKx I2Sx and GPIOx are associated with their use as I2S or MCLK signals The pins support GPIO functionality so support both input a...

Page 115: ...I2S2_SDOUT I2S2_SDIN DMIC 5 3 _DAT DMIC 5 3 _CLK I2C8_CLK I2C8_DAT SoC Function DAP4_SCLK DAP4_FS DAP4_DOUT DAP4_DIN 120 M 2 Key E L14 D8 C7 H8 B8 C59 C60 K59 J59 G4 E4 F5 F6 CAN1_STB DMIC CAN1_EN GEN...

Page 116: ...ps Note Up to 4 signal Vias can share a single GND return Via Table 12 4 I2S and Miscellaneous Codec Signal Connections Module Pin Name Xavier Function Type Termination Description I2S1_SCLK I2S1_CLK...

Page 117: ...Signal Routing Requirements Parameter Requirement Units Notes Clock Frequency Period 12 83 33 MHz ns Data Bit rate Period DDR24 24 41 66 Mbps ns Configuration Device Organization 1 load Topology Poin...

Page 118: ...C_SDA General I2C 3 Data D61 I2C4_CLK GEN8_I2C_SCL General I2C 4 Clock Audio Codec and Camera Connector E60 I2C4_DAT GEN8_I2C_SDA General I2C 4 Data A53 I2C5_CLK DP_AUX_CH3_P General I2C 5 Clock Expan...

Page 119: ...7H41 AO 1K to 1 8V I2C3 I2C3_CLK DAT CAM 1K to 1 8V I2C4 DP1_AUX_CH_N P EDP 1K to 1 8V I2C5 PWR_I2C_SCL SDA On module only System control On JAXi only routed to mux with VM_I2C Output of mux controls...

Page 120: ...board for misc I2C usage E53 F53 J61 K61 D61 E60 F51 F52 J53 J52 GEN1_I2C_SCL GEN1_I2C_SDA 1k 1k 1 8V Used on module for ID EEPROM available on carrier board for misc I2C usage K5 I2C1 L8 DP_AUX_CH3_N...

Page 121: ...ces I2C4_CLK DAT I OD 1k pull ups to 1 8V on module General I2C 4 Clock Data Connect to CLK Data pins of 1 8V devices I2C5_CLK DAT I OD 1k pull ups to 1 8V on module General I2C 5 Clock Data Connect t...

Page 122: ..._N SPI1_CS0 SPI 1 Chip Select 0 B56 SPI1_CS1_N SPI1_CS1 SPI 1 Chip Select 1 A56 SPI1_MISO SPI1_MISO SPI 1 Master In Slave Out D55 SPI1_MOSI SPI1_MOSI SPI 1 Master Out Slave In E61 SPI2_CLK SPI2_SCK SP...

Page 123: ...sage AO A56 D55 E55 E61 D62 F60 D60 F55 D56 G56 C57 E56 B56 Routed on carrier board to Expansion Connector through selectablevoltage levelshifter 1 8V or 3 3V The following figure shows the basic SPI...

Page 124: ...S SPI1 SPI2 SPI3 134 787 109 685 129 815 mm ps Max Branch delay 75ps Max Trace Length Delay Skew from MOSI MISO and CS to SCK 16 100 mm ps At any point Note Up to 4 signal vias can share a single GND...

Page 125: ...st to Send Output K60 UART3_RX_DEBUG UART3_RX Debug UART Receive Input H62 UART3_TX_DEBUG UART3_TX Debug UART Transmit Output H58 UART5_RX UART5_RX UART 5 Receive M 2 Key E Connector Input J58 UART5_T...

Page 126: ...PIO on carrier board Unused on carrier board Available to use as GPIO 10k SPI2_SCK SPI2_MISO SPI2_MOSI SPI2_CS0 Routed to PCIe x16 connector on carrier board Alternately availablefor general SPI usage...

Page 127: ...AN1_DIN CAN1_DIN CAN 1 Receive Input H61 CAN1_DOUT CAN1_DOUT CAN 1 Transmit Output B62 GPIO08 CAN1_STB GPIO Digital Mic Input Data Input C61 GPIO09 CAN1_EN GPIO Digital Mic Input Clock Output E59 GPIO...

Page 128: ...ip Stripline 4x 3x dielectric Max Trace Length for RX and TX only 310 1950 mm ps Max Trace Length Delay Skew from RX to TX 8 50 mm ps Table 13 15 CAN Signal Connections Module Pin Name Function Type T...

Page 129: ...r Developer Kit Carrier Board Specification The document contains the maximum current capability of the VDD_5V supply in the Interface Power chapter The fan is powered by this supply on the Jetson AGX...

Page 130: ...5V VDD_1V8 G S D 10pF 4 3 2 1 10nF 100k 100k 10k 10uF 0 1uF Fan Header 100 G S D 5V_AO 4 7k Table 14 2 Fan Signal Connections Module Pin Name Type Termination Description FAN_PWM O 100k pulldown to GN...

Page 131: ...VBUS or ID detection is needed As long as the force recovery strap is held low coming out of reset Jetson Xavier NX will configure USB0 as a device and enter recovery mode For USB 3 1 recovery mode th...

Page 132: ...y Scan Mode NVDBG is left unconnected pulled down on module for normal operation and pulled to 1 8V for alternate debug modes debug over USB etc for Boundary Scan test mode JTAG_TRST_N must be driven...

Page 133: ...lled to GND through 100k resistor on module Input Notes 1 In the Type Dir column Output is from Jetson AGX Xavier Input is to Jetson AGX Xavier Bidir is for Bidirectional signals Table 15 2 JTAG Signa...

Page 134: ...pply on the non Jetson AGX Xavier side of the device UART Receive Connect to TX pin of serial device 15 3 Strapping Pins Jetson AGX Xavier has one strap FORCE_RECOVERY_N that is intended to be used on...

Page 135: ...ed high and The SoC must be held in reset without resetting the PMIC This is done using the PERIPHERAL_RESET_N pin on the module The following figure illustrates this Other requirements related to sup...

Page 136: ...AXi only Connects to safety MCU on carrier board if implemented Routed on module to mux with PWR_I2C Mux select connected to SoC reset Output of mux controls on module voltage monitors VM_I2C controls...

Page 137: ...SI SPI2_CS0 GPIO31 VM_I2C_SCK VM_I2C_DAT VM_INT_N SYS_RESET_N Mux L44 L45 SEL SYS_RESET_N LVL On Module Control Safety MCU G59 SPI2_SCK SPI2_MISO SPI2_MOSI SPI2_CS0_N AO E61 D62 F60 D60 Level Shifter...

Page 138: ...en by the SoC inputs Input clocks include the I2S and SPI clocks when SoC is in slave mode The FAN_TACH pin is another input that could be affected by noise on the signal edges The SDCARD_CLK pin whil...

Page 139: ...y be affected The buffer and shifter should be disabled until the device power is enabled 16 4 Pad Drive Strength The following table provides the maximum MPIO pad output drive current when the pad is...

Page 140: ...s Pin Groups I2Sx AUD_MCLK DSPKx DMICx SLVSx GPIO_AO_RET SDMMCx IQCx WDT_RESET_x MIPI_TRC_x UFSx TOUCH_x EQOSx PEx PEX_CLKx EXTPERIPHx QSPIx DP_AUXx IGPUx Ux3_x GP_PWMx SATA_LED_ACTIVE I2Cx CCLAx NV_T...

Page 141: ...the design matches the check item description is different or is not applicable to the design The bring up checklist is intended to provide basic items to check during bring up for power delivery and...

Page 142: ...ine can greatly affect the performance of the trace Via placement can make differences in current carrying capability signal integrity due to reflections and attenuation and noise generation all of wh...

Page 143: ...ided The diminished spacing creates a blockage and forces the current to find another path due to lack of copper as shown in Figure 19 2 and Figure 19 3 This leads to power delivery issues and impedan...

Page 144: ...uire four memory signal routing layers with at least two GND planes for reference This comes to six layers add another two for power which gives eight layers minimum Reduction from eight to six layers...

Page 145: ...Stack Up Impact on Signal Quality Both layer count and layer order impact signal integrity Proper inter signal spacing must be achievable Via count for critical signals must be minimized Current comm...

Page 146: ...er stack up affect the characteristic trace impedance of a transmission line Z0 L C 1 2 Signal rise time is proportional to the transmission line impedance and load capacitance CLoad R is eTime Z0 R T...

Page 147: ...e 21 2 describes the microstrip transmission line Figure 21 2 Microstrip Transmission Line Dielectric W T H Z0 ln 87 Er 1 414 5 98H 0 8W T Z0 Impedance W Trace width inches T Trace thickness inches Er...

Page 148: ...S ZS also acts as the source termination which helps dampen reflection Source reflection coefficient R 1 ZS Z0 ZS Z0 21 4 Receiver Characteristics Receiver characteristics are important to the integri...

Page 149: ...of least inductance The lowest inductance path for a transmission line is right underneath the transmission line i D is proportional to Figure 21 4 Transmission Line Height Transmission line return cu...

Page 150: ...d receiver Reference plane cuts and layer changes need to be avoided Power plane cut example Figure 21 6 Power plane cuts will cause EMI issues Power plane cuts also induce crosstalk to adjacent signa...

Page 151: ...eference plane if possible When a reference plane switches to different power rail a stitching capacitor is required Figure 21 8 When the same ground and power reference plane changes to a different l...

Page 152: ...le connector to the final connector and device Intra and Inter Pair Skews Intra Pair Skew within Pair Difference in delay between two traces in differential pair Shorter routes may require indirect pa...

Page 153: ...o right Signal to return via ratio Number of Ground Return vias per Signal vias For critical IFs ratio is usually 1 1 For less critical IFs several trace vias can share fewer return vias i e 3 2 3 tra...

Page 154: ...ess subsystems The issues and recommended mitigation techniques would be similar 23 1 Mitigation Techniques Each design is different due to unique construction and relative location of USB SS circuits...

Page 155: ...mpared to fully metalized USB SS devices GROUND THE USB SS PART SOLIDLY The USB SS connector is grounded through the grounding legs previously mentioned Care must be taken to ensure the leg area is a...

Page 156: ...ption is attached to this design guide To access the attached file click the Attachment icon on the left hand toolbar on this PDF using Adobe Acrobat Reader or Adobe Acrobat Select the file and use th...

Page 157: ...or ii customer product designs No license either expressed or implied is granted under any NVIDIA patent right copyright or other NVIDIA intellectual property right under this document Information pub...

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