Operation
Chapter 4
WAAS GUS Signal Generator User Guide Rev 1
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The Message Ready signal enables the Signal Generator internal 1 MHz clock (period 1 ms) which is then returned
to the Comparator.
The Comparator counts 500 clocks and resets the Message Ready flag after the 500th clock. For each clock, the
Comparator transfers each data bit from its output buffer on the leading edge, and the Signal Generator samples the
data bit on the trailing edge. The 500 bits of data are then transferred from the CMP to the Signal Generator at the 1
MHz rate. The entire transfer takes 500
s or 1/2 ms. The Signal Generator buffers each L1 and L5 500 SPS
message from the CMP.
If quadrature (Q) data is enabled on the L1 or L5 interface, a second set of 500 bits must be provided by the
Comparator for that interface as the Q data. If the second set of 500 bits is not provided, no data shall be transmitted
and the output of both the I and Q shall be inhibited. If only in-phase (I) data is enabled and a second set of 500 bits
is provided, the second set of 500 bits shall be discarded, however, the first set of 500 bits shall be transmitted
normally as the I data.
After MSGRDY has been asserted, the Signal Generator sends its first clock within 1 microsecond of the assertion.
After the 500th clock goes low, the MSGRDY should not be reasserted until after another 4 microseconds. The
interface timing is shown in
.
Figure 9: RS-485 Symbol Timing Diagram
4.2.1
Other Control Lines
Two other control lines exist on the Message Interface. These are:
• RESET from CMP to Signal Generator
• TX INH from CMP to Signal Generator
If the RESET line is high, the Signal Generator hardware undergoes a hard reset. The Signal Generator is rebooted
to power-up state after the RESET line is de-asserted. Note, the L1 and L5 operations are independent.
If the TX INH line is high, the Signal Generator IF output switch opens, causing the IF output signal to cease. The
RF output is not switched.
