Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transaction
cycles. Select Enabled to support compliance with PCI specification version 2.1
41
4.8 Integrated Peripherals
Figure 4-6 : BIOS- Integrated Peripherals
On-Chip IDE Device
The system chipset contains IDE HDD Block mode, and a PCI IDE interface with
support for two IDE Primary (Master & Slave) PIO’s and two IDE Primary (Master &
Slave) UDMA’s, and two IDE Secondary (Master & Slave) PIO’s and two IDE Second-
ary (Master & Slave) UDMA’s. Select Enabled to activate the primary and/or second-
ary IDE interface. Select Disabled to deactivate this interface if you install a primary
and/or secondary add-in IDE interface.
USB Controller
Select Enabled if your system contains a Universal Serial Bus controller and you have
USB peripherals.
Summary of Contents for PEAK 7220VL2G
Page 1: ...www nexcom com Single Board Computer User Manual 2003 08 Edition ...
Page 5: ...4 Chapter 1 General Information Chapter 1 General Information ...
Page 11: ...10 Chapter 2 Jumper Switch Settings ...
Page 16: ...2 4 Jumper Setting 15 Mainboard ...
Page 17: ...16 Daughterboard ...
Page 18: ...17 daughterboard ...
Page 19: ...18 ...
Page 20: ...19 ...
Page 21: ...Chapter 3 Expansion Capabilities 20 ...
Page 27: ...26 Chapter 4 Award BIOS Setup ...