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Chapter 5
Memory Access Control Function
Preliminary User’s Manual U14913EE1V0UM00
Figure 5-2: SRAM, External ROM, External I/O Access Timing (3/6)
(c) During write
Remarks: 1. The circles
❍
indicate the sampling timing.
2. The broken line indicates the high-impedance state.
3. CSn = CS2 to CS4
T1
T2
Address
Data
WAIT (input)
D0 to D15 (I/O)
LWR (output)
UWR (output)
RD (output)
A0 to A23 (output)
CLKOUT (output)
Data
Address
TW
T2
T1
CSn (output)
Summary of Contents for V850E/CA1 ATOMIC
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