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NEC V850E/CA1 ATOMIC, Preliminary User'S Manual

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Chapter 14

A/D Converter

Preliminary User’s Manual U14913EE1V0UM00

14.8  Operation in Timer Trigger Mode

The A/D converter can set an interrupt signal as a conversion trigger for up to 12 channels of analog 
input (ANI0 to ANI11).
The interrupt signal that can be selected as trigger is the Timer E 0 interrupt INTPE10/TINTCCE10.

14.8.1  Operation in select mode

One analog input (ANI0 to ANI) specified by the ADSCM0 register is A/D converted. The conversion 
result is stored in the ADCRm register corresponding to the analog input (m = 0 to 11).
This is optimal for applications that read A/D conversion values synchronized to a trigger.

(1)

Timer trigger select mode

Taking the interrupt signal as a trigger, one analog input at a time is A/D converted and the result is 
stored in one ADCRm register. An A/D conversion termination interrupt (INTAD) is generated for 
each A/D conversion, which terminates A/D conversion (CS = 0).

After A/D conversion termination, the A/D converter changes to trigger wait status (CE = 1). It per-
forms A/D conversion operation again, when the interrupt signal occurs.

Remark:

m = 0 to 11

Figure 14-13:  Example of Timer Trigger Select Mode Operation (ANI4)  

Trigger

Analog Input

A/D Conversion Result Register

Timer E 0 Interrupt 

 ANIm

 ADCRm

ANI0

ANI1

ANI2

ANI3

ANI4

ANI5

:

ADCR0

ADCR1

ADCR2

ADCR3

ADCR4

ADCR5

     :

ADCR11

A/D converter

INTPE10/TINTCCE10

(1)  CE bit of ADSCM0 = 1 (Enabled)

(2)  INTPE10/TINTCCE10 interrupt generation

(3)  A/D conversion of ANI4

(4)  Store conversion result in ADCR4

(5)  INTAD interrupt generation

ANI11

Summary of Contents for V850E/CA1 ATOMIC

Page 1: ...liminary User s Manual V850E CA1TM ATOMIC 32 16 bit Single Chip Microcontroller Hardware µPD703123 µPD70F3123 Document No U14913EE1V0UM00 Date Published October 2001 NEC Corporation 2001 Printed in Germany ...

Page 2: ...Note No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins it is possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin shoul...

Page 3: ...esponsibility of customer NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information While NEC endeavours to enhance the quality reliability and safety of NEC semiconductor products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage...

Page 4: ...mbH Duesseldorf Germany Tel 0211 65 03 02 Fax 0211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Italiana s r l Milano Italy Tel 02 66 75 41 Fax 02 66 75 42 99 NEC Electronics Germany GmbH Benelux Office Eindhoven The Netherlands Tel 040 2445845 Fax 040 2444580 NEC Electronics France S A Vélizy Villacoublay France Tel 01 30 67 58 00 Fax 01 30...

Page 5: ...d notation are used as follows Weight in data notation Left is high order column right is low order column Active low notation xxx pin or signal name is over scored or xxx slash before signal name Memory map address High order at high stage and low order at low stage Note Explanation of Note in the text Caution Item deserving extra attention Remark Supplementary explanation to the text Numeric not...

Page 6: ...6 Preliminary User s Manual U14913EE1V0UM00 MEMO ...

Page 7: ...around of CPU address space 62 3 4 4 Memory map 63 3 4 5 Area 64 3 4 6 External memory expansion 68 3 4 7 Recommended use of address space 68 3 4 8 Peripheral I O registers 71 3 4 9 Programmable peripheral I O registers 81 3 5 Specific Registers 115 3 5 1 Command Register PRCMD 116 3 5 2 Peripheral Command Register PHCMD 116 3 5 3 Peripheral Status Register PHS 117 3 5 4 Internal peripheral functi...

Page 8: ...sters 0 to 3 DADC0 to DADC3 170 6 3 5 DMA channel control registers 0 to 3 DCHC0 to DCHC3 171 6 3 6 DMA disable status register DDIS 172 6 3 7 DMA restart register DRST 172 6 3 8 DMA trigger factor registers 0 to 3 DTFR0 to DTFR3 173 6 4 DMA Bus States 176 6 4 1 Types of bus states 176 6 4 2 DMAC bus cycle state transition 177 6 5 Transfer Mode 178 6 5 1 Single transfer mode 178 6 5 2 Single step ...

Page 9: ...e Interrupt Processing Control 220 7 8 Interrupt Response Time 222 7 9 Periods in Which Interrupts Are Not Acknowledged 223 Chapter 8 Clock Generator 225 8 1 Features 225 8 2 Configuration 225 8 3 Main system clock oscillator 226 8 4 Control Registers 227 8 4 1 Clock Control Register CKC 227 8 4 2 PLL Status Register PSTAT 228 8 4 3 Clock select pin 228 8 5 Power Saving Functions 230 8 5 1 General...

Page 10: ... 12 2 3 Control registers 313 12 2 4 Interrupt requests 320 12 2 5 Operation 321 12 2 6 Dedicated baud rate generators BRG of UARTn n 0 to 2 330 12 2 7 Precautions 337 12 3 Clocked Serial Interfaces 0 1 CSI0 CSI1 338 12 3 1 Features 338 12 3 2 Configuration 339 12 3 3 Control registers 341 12 3 4 Operation 353 12 3 5 Output pins 364 12 3 6 Dedicated baud rate generators 0 1 BRG0 BRG1 365 Chapter 1...

Page 11: ...lling Mode 506 14 7 1 Operation in select mode 506 14 7 2 Operation in scan mode 507 14 8 Operation in Timer Trigger Mode 508 14 8 1 Operation in select mode 508 14 8 2 Operation in scan mode 509 14 9 Precautions 511 14 9 1 Stopping conversion operation 511 14 9 2 Trigger input during conversion operation 511 14 9 3 Timer trigger interval 511 14 9 4 Operation in standby modes 511 Chapter 15 LCD Co...

Page 12: ... 572 20 3 Programming Environment 572 20 4 Communication System 573 20 5 Flash Programming Circuitry 574 20 6 Pin Handling 575 20 6 1 VPP0 VPP1 pins 575 20 6 2 Serial interface pins 576 20 6 3 RESET pin 578 20 6 4 NMI pin 578 20 6 5 MODE pin 578 20 6 6 Port pins 578 20 6 7 Other signal pins 578 20 6 8 Power supply 578 20 7 Programming Method 579 20 7 1 Flash memory control 579 20 7 2 Selection of ...

Page 13: ... Timing 1 4 158 Figure 6 1 Block Diagram of DMA Controller Configuration 164 Figure 6 2 DMA Source Address Registers H0 to H3 DSAH0 to DSAH3 165 Figure 6 3 DMA Source Address Registers L0 to L3 DSAL0 to DSAL3 166 Figure 6 4 DMA Destination Address Registers 0H to 3H DDA0H to DDA3H 167 Figure 6 5 DMA Destination Address Registers L0 to L3 DDAL0 to DDAL3 168 Figure 6 6 DMA Transfer Count Registers 0...

Page 14: ...ister 0 1 TMCD0 to TMCD1 252 Figure 9 6 TMD Compare Operation Example 254 Figure 9 7 Block Diagram of Timer E 259 Figure 9 8 Timer E Time Base Counter 0 Registers 0 to 2 TBASE00 to TBASE02 261 Figure 9 9 Timer E Time Base Counter 1 Registers 0 to 2 TBASE10 to TBASE12 261 Figure 9 10 Timer E Sub Channel 0 Capture Compare Registers 0 to 2 CVSE00 to 02 262 Figure 9 11 Timer E Sub Channel x Main Captu...

Page 15: ...B0 to RXB2 318 Figure 12 6 Transmission Buffer Registers 0 to 2 TXB0 to TXB2 319 Figure 12 7 Asynchronous Serial Interface Transmit Receive Data Format 321 Figure 12 8 Asynchronous Serial Interface Transmission Completion Interrupt Timing 322 Figure 12 9 Continuous Transmission Starting Procedure 324 Figure 12 10 Continuous Transmission End Procedure 325 Figure 12 11 Asynchronous Serial Interface ...

Page 16: ...ent generation 403 Figure 13 16 CAN Global Time System Counter CGTSC 404 Figure 13 17 CAN Message Search Start Register CGMSS 405 Figure 13 18 CAN Message Search Start Register CGMSS 406 Figure 13 19 CAN Test Bus Register CTBR 407 Figure 13 20 Internal CAN Test Bus Structure 407 Figure 13 21 CAN Interrupt Pending Register CCINTP 408 Figure 13 22 CAN Global Interrupt Pending Register CGINTP 1 2 409...

Page 17: ...3 Figure 14 9 Example of Select Mode A D Trigger Select Operation ANI2 504 Figure 14 10 Example of Scan Mode A D Trigger Scan Operation ANI2 ANI5 505 Figure 14 11 Example of Select Mode A D Trigger Polling Select Operation ANI2 506 Figure 14 12 Example of Scan Mode A D Trigger Polling Scan Operation ANI2 to ANI5 507 Figure 14 13 Example of Timer Trigger Select Mode Operation ANI4 508 Figure 14 14 ...

Page 18: ...ntrol Register PMCCS 556 Figure 16 39 Port CT PCT 557 Figure 16 40 Port CT Mode Register PMCT 557 Figure 16 41 Port CT Mode Control Register PMCCT 558 Figure 16 42 Port CM PCM 559 Figure 16 43 Port CM Mode Register PMCM 559 Figure 16 44 Port CM Mode Control Register PMCCM 560 Figure 17 1 Reset signal acknowledgment 562 Figure 17 2 Reset at power on 562 Figure 18 1 Regulator 565 Figure 19 1 Block D...

Page 19: ...n of Watch Timer 300 Table 10 3 Interval Time of Interval Timer 303 Table 11 1 Runaway Detection Time by Watchdog Timer 305 Table 11 2 Runaway Detection Time by Watchdog Timer 307 Table 12 1 Generated Interrupts and Default Priorities 320 Table 12 2 Transmission Status and Whether or Not Writing Is Enabled 323 Table 12 3 Reception Error Causes 327 Table 12 4 Baud Rate Generator Setting Data 334 Ta...

Page 20: ...ontroller Driver Configuration 513 Table 15 3 Relationship between LCD Display Data Memory Contents and Segment Common Outputs 517 Table 15 4 Memory Layout of LCD Segments 517 Table 15 5 COM Signals 518 Table 15 6 LCD Drive Voltage 518 Table 15 7 Drive Voltage Supply 520 Table 15 8 Selection and Non Selection Voltages COM0 to COM3 522 Table 17 1 Operation Status of Each Pin During Reset Period 561...

Page 21: ...or use in digital servo control a 32 bit hardware multiplier enables this CPU to support multiply instructions saturated multiply instructions bit operation instructions etc Also through 2 byte basic instructions and instructions compatible with high level languages etc object code efficiency in a C compiler is increased and program size can be made more compact Further since the on chip interrupt...

Page 22: ...g short format Signed load instructions Internal memory Flash selfprogramming support Clock Generator Internal PLL 4 fold PLL Frequency range up to 20 MHz Crystal frequency range 4 MHz fCRYSTAL 5 MHz Built in power saving modes WATCH HALT STOP Power supply voltage range 4 5 V VDD5 5 5 V Temperature range Ta 40 to 85 C Bus control unit Address data separated bus 24 bit address 16 8 bit data bus 16 ...

Page 23: ...h Note For an operating voltage below the given minimum value the quality of the displayed segments will decrease 1 3 Application Fields The V850E CA1 ATOMIC is ideally suited for automotive applications like dashboard or central gate way applications It is also an excellent choice for other applications where a combination of sophisti cated peripheral functions and CAN network support is required...

Page 24: ...13 PDL12 D12 PDL11 D11 PDL10 D10 PDL9 D9 PDL8 D8 VSS53 VDD53 VPP0 PDL7 D7 PDL6 D6 PDL5 D5 PDL4 D4 PDL3 D3 MODE3 MODE2 ANI11 ANI10 ANI9 ANI8 ANI7 ANI6 ANI5 ANI4 ANI3 ANI2 ANI1 ANI0 AV REF AV SS AV DD V DD 32 V SS 32 X2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 108 107 106 105 104 103 102 101 100 99 98...

Page 25: ...Select SEG0 to SEG39 LCD segment pins CTXD1 to CTXD3 CAN Transmit Line Output SI0 SI1 Serial Input CVDD Clock Generator Power Supply SO0 SO1 Serial Output CVSS Clock Generator Ground TCLRE0 TCLRE1 TCLRE2 Timer Clear Input GND30 to GND33 Ground for 3 V Power Supply TIE0 to TIE2 Timer Input GND50 to GND54 Ground for 5 V Power Supply TOEn0 TOEn2 Timer Output INT0 to INT2 External interrupt request TX...

Page 26: ...Watch Watchdog Timer AV REF Analog inputs supply X1 X2 MODE RESET CLKOUT Oscillator an Clock Generator with PLL System Control Ports VLCD0 VLCD2 COM0 3 SEG0 SEG39 Interrupt Controller External Interrupts Full CAN 1 Full CAN 2 UART0 UART1 UART2 BRG CTXD1 CRXD1 CTXD2 CRXD2 TXD0 RXD0 TXD1 RXD1 TXD2 RXD2 SO0 SI0 SCK0 CSI0 power supply Voltage monitor with low Voltage Detection Voltage threshold BRG BR...

Page 27: ... memory and I O There is one address mode 2 cycle transfer and there are three bus modes single transfer single step transfer and block transfer 3 ROM The µPD703123 has on chip mask ROM 256 Kbytes and the µPD70F3123 on chip flash memory 256 Kbytes During instruction fetch ROM flash memory can be accessed from the CPU in 1 clock cycles If the single chip mode 0 or flash memory programming mode is s...

Page 28: ...nctions and control pin functions Port Port Function Control Function Port 1 8 bit input output Serial interface input output Port 2 8 bit input output Serial interface input output Port 3 6 bit input output Real time pulse unit input output external interrupt input PWM output Port 4 6 bit input output Real time pulse unit input output external interrupt input PWM output Port 5 6 bit input output ...

Page 29: ... CRXD3 P15 CTXD3 P16 RXD1 P17 TXD1 P20 I O Port 2 SI0 P21 8 bit input output port SO0 P22 SCK0 P23 SI1 P24 SO1 P25 SCK1 P26 RXD0 P27 TXD0 P30 I O Port 3 TIE0 INTPE00 P31 6 bit input output port TOE10 INTPE10 P32 TOE20 INTPE20 P33 TOE30 INTPE30 P34 TOE40 INTPE40 P35 TCLRE0 INTPE50 P40 I O Port 4 TIE1 INTPE01 P41 6 bit input output port TOE11 INTPE11 P42 TOE21 INTPE21 P43 TOE31 INTPE31 P44 TOE41 INT...

Page 30: ...it input output port A0 A15 SEG23 SEG8 PAH0 PAH7 I O Port AH 8 bit input output port A16 A23 SEG7 SEG0 PDL0 PDL15 I O Port DL 16 bit input output port D0 D15 PCS2 PCS4 I O Port CS 3 bit input output port CS2 CS4 SEG24 SEG26 PCT0 I O Port CT LWR SEG27 PCT1 5 bit input output port UWR SEG28 PCT2 SEG29 PCT3 SEG30 PCT4 RD SEG31 PCM0 I O Port CM WAIT SEG32 PCM1 2 bit input output port CLKOUT SEG33 Port...

Page 31: ...tion mode connect to VSS for X1 X2 input AVDD Power supply for A D converter AVSS Ground potential for A D converter AVREF input reference voltage input for A D converter NMI input non maskable interrupt input VCMPOUT VCMPOUT output voltage comparator feedback output NMI VCMPIN input voltage comparator compare input ANI0 ANI11 input analog input to A D converter SI0 input serial receive data input...

Page 32: ...ut LCD controller driver common line 0 3 TIE0 input Timer E channel 0 capture 0 input P30 INTPE00 TOE10 TOE40 I O Timer E channel 0 capture 1 4 input compare output P31 P34 INTPE10 INTPE40 TCLRE0 input Timer E channel 0 capture 5 input or timer clear input P35 INTPE50 TIE1 input Timer E channel 1 capture 0 input P40 INTPE01 TOE11 TOE41 I O Timer E channel 1 capture 1 4 input compare output P41 P44...

Page 33: ...te VCMPIN operate operate operate operate operate SEG 39 0 N A HOLD operate operate operate operate COM 3 0 Hi Z HOLD operate operate operate operate TIExy N A operate operate INTPExy INT 2 0 NMI N A operate operate operate operate operate TOExy N A HOLD HOLD HOLD operate operate TCLRE 2 0 N A operate operate SO1 SO0 N A HOLD HOLD HOLD operate operate SI1 SI0 N A operate operate SCK1 SCK0 N A HOLD...

Page 34: ...it and specified by the port 1 mode control register PMC1 a Port mode P10 to P17 can be set to input or output in 1 bit units using the port 1 mode register PM1 b Control mode P10 to P17 can be set to port or control mode in 1 bit units using PMC1 c CTXD1 CTXD2 CTXD3 Transmit data for controller area network Output This pin outputs FCAN serial transmit data d CRXD1 CRXD2 CRXD3 Receive data for con...

Page 35: ...ode control register PMC2 a Port mode P20 to P27 can be set to input or output in 1 bit units using the port 2 mode register PM2 b Control mode P20 to P27 can be set to port or control mode in 1 bit units using PMC2 c SO0 SO1 Serial output Output These pins output CSI0 and CSI1 serial transmit data d SI0 SI1 Serial input Input These pins input CSI0 and CSI1 serial receive data e SCK0 SCK1 Serial c...

Page 36: ...d by the port 3 mode control register PMC3 a Port mode P30 to P35 can be set to input or output in 1 bit units using the port 3 mode register PM3 b Control mode P30 to P35 can be set to port or control mode in 1 bit units using PMC3 c TOE10 to TOE40 Timer output Output These pins output a timer E pulse signal d TIE0 Timer input Input This is a timer E external counter clock input pin e TCLRE0 Time...

Page 37: ...d by the port 4 mode control register PMC4 a Port mode P40 to P45 can be set to input or output in 1 bit units using the port 4 mode register PM4 b Control mode P40 to P45 can be set to port or control mode in 1 bit units using PMC4 c TOE11 to TOE41 Timer output Output These pins output a timer E pulse signal d TIE1 Timer input Input This is a timer E external counter clock input pin e TCLRE1 Time...

Page 38: ...d by the port 5 mode control register PMC5 a Port mode P50 to P55 can be set to input or output in 1 bit units using the port 5 mode register PM5 b Control mode P50 to P55 can be set to port or control mode in 1 bit units using PMC5 c TOE12 to TOE42 Timer output Output These pins output a timer E pulse signal d TIE2 Timer input Input This is a timer E external counter clock input pin e TCLRE2 Time...

Page 39: ...ter PMC6 a Port mode P60 to P65 can be set to input or output in 1 bit units using the port 6 mode register PM6 b Control mode P60 to P65 can be set to port or control mode in 1 bit units using PMC6 c CCLK External CAN clock input Input This inputs the external CAN clock supply d INT0 INT2 Interrupt request from peripherals Input These are external interrupt request input pins e SEG34 SEG 39 Segme...

Page 40: ...ler driver An operation mode of port or control mode can be selected for each bit and specified by the port AL mode control register PMCAL a Port mode PAL0 to PAL15 can be set to input or output in 1 bit units using the port AL mode register PMAL b Control mode PAL0 to PAL15 can be used as A0 to A15 by using PMCAL c A0 to A15 Address Output This pin outputs the lower 16 bit address of the 24 bit a...

Page 41: ...roller driver An operation mode of port or control mode can be selected for each bit and specified by the port AH mode control register PMCAH a Port mode PAH0 to PAH7 can be set to input or output in 1 bit units using the port AH mode register PMAH b Control mode PAH0 to PAH7 can be used as A16 to A23 by using PMCAH c A16 to A23 Address Output This pin outputs the upper 8 bit address of the 24 bit...

Page 42: ...rt in control mode external expansion mode these operate as the data bus D0 to D15 for when memory is expanded externally An operation mode of port or control mode can be selected for each bit and specified by the port DL mode control register PMCDL a Port mode PDL0 to PDL15 can be set to input or output in 1 bit units using the port DL mode register PMDL b Control mode PDL0 to PDL15 can be used a...

Page 43: ...the port CS mode control register PMCCS a Port mode PCS2 to PCS4 can be set to input or output in 1 bit units using the port CS mode register PMCS b Control mode PCS2 to PCS4 can be used as CS2 to CS4 by using PMCCS c CS2 to CS4 Chip select Output This is the chip select signal for external SRAM external ROM or external peripheral I O The signal CSn is assigned to memory block n n 2 to 4 This is a...

Page 44: ...cycle for SRAM external ROM or an external peripheral I O area In the data bus the lower byte is in effect If the bus cycle is a lower memory write it becomes active at the falling edge of a T1 state CLKOUT signal and becomes inactive at the falling edge of a T2 state CLKOUT signal d UWR Upper byte write strobe Output This is a strobe signal that shows that the executing bus cycle is a write cycle...

Page 45: ...in 1 bit units using the port CM mode register PMCM b Control mode PCM0 to PCM1 can be used as CLKOUT WAIT by using PMCCM c WAIT Wait Input This control signal input pin which inserts a data wait in a bus cycle can input asynchronously with respect to a CLKOUT signal Sampling is done at the falling edge of a CLKOUT signal in a bus cycle in a T1 or TW state If the setup or hold time is not secured ...

Page 46: ... divided into normal operation modes and flash memory programming mode The operation mode is determined by sampling the status of each of pins MODE0 to MODE3 on a reset Fix these so that the input level does not change during operation 19 RESET Reset Input RESET input is asynchronous input When a signal having a certain low level width is input in asyn chronous with the operation clock a system re...

Page 47: ...ns for the peripheral interface 27 VDD30 to VDD33 Power supply These are the positive power supply pins for the internal CPU 28 VSS30 to VSS33 Ground These are the ground pins for the internal CPU 29 AVDD Analog power supply This is the analog positive power supply pin for the A D converter 30 AVSS Analog ground This is the ground pin for the A D converter 31 AVREF Analog reference voltage Input T...

Page 48: ...P16 RXD1 P17 TXD1 P20 SI0 5 K P21 SO0 P22 SCK0 P23 SI1 P24 SO1 P25 SCK1 P26 RXD0 P27 TXD0 P30 TIE0 INTPE00 5 K P31 TOE10 INTPE10 P32 TOE20 INTPE20 P33 TOE30 INTPE30 P34 TOE40 INTPE40 P35 TCLRE0 INTPE50 P40 TIE1 INTPE01 5 K P41 TOE11 INTPE11 P42 TOE21 INTPE21 P43 TOE31 INTPE31 P44 TOE41 INTPE41 P45 TCLRE1 INTPE51 P50 TIE2 INTPE02 5 K P51 TOE12 INTPE12 P52 TOE22 INTPE22 P53 TOE32 INTPE32 P54 TOE42 I...

Page 49: ...L7 A7 SEG16 PAL8 A8 SEG15 PAL9 A9 SEG14 PAL10 A10 SEG13 PAL11 A11 SEG12 PAL12 A12 SEG11 PAL13 A13 SEG10 PAL14 A14 SEG9 PAL15 A15 SEG8 PAH0 A16 SEG7 17 G PAH1 A17 SEG6 PAH2 A18 SEG5 PAH3 A19 SEG4 PAH4 A20 SEG3 PAH5 A21 SEG2 PAH6 A22 SEG1 PAH7 A23 SEG0 PCM0 WAIT SEG32 17 G PCM1 CLKOUT SEG33 PCS2 CS2 SEG24 17 G PCS3 CS3 SEG25 PCS4 CS4 SEG26 PCT0 LWR SEG27 17 G PCT1 UWR SEG28 PCT2 SEG29 17 G PCT3 SEG3...

Page 50: ...13 PDL14 D14 PDL15 D15 AIN0 AIN11 7 Individually connect to AVDD or AVSS via a resistor MODE0 2 VSS5X MODE1 2 VDD5X MODE2 MODE3 2 VSS5X COM0 COM3 17 G VPP0 VPP1 connect to VSS via a resistor VLCD0 VLCD2 VCPMOUT NMI 5 K VCMPIN 1 connect to VDD5 via a resistor RESET 2 CLKSEL 2 connect to VDD5 or VSS5 via a resistor IC 1 VSS5x CLOCKIN 2 connect to VSS5 via a resistor X2 Please refer to the datasheet ...

Page 51: ...ure 2 1 Pin I O Circuits Type1 Type 7 Type 2 Type 17 G Type 5 K VDD P ch N ch IN IN data output disable input enable VDD P ch IN OUT N ch P ch N ch VREF IN P ch N ch SEG data P ch N ch VLC0 VLC1 P ch N ch VLC2 data output disable input enable VDD P ch IN OUT N ch P ch N ch ...

Page 52: ...52 Preliminary User s Manual U14913EE1V0UM00 MEMO ...

Page 53: ...atures Minimum instruction cycle 50 ns internal 20 MHz operation Memory space Program space 64 MB linear Data space 4 GB linear Thirty two 32 bit general registers Internal 32 bit architecture Five stage pipeline control Multiplication division instructions Saturated operation instructions One clock 32 bit shift instruction barrel shifter Long short instruction format Four types of bit manipulatio...

Page 54: ...23 r24 r25 r26 r27 r28 r29 r30 r31 Zero Register Reserved for Assembler Interrupt Stack Pointer Stack Pointer SP Global Pointer GP Text Pointer TP Element Pointer EP Link Pointer LP PC Program Counter PSW Program Status Word ECR Interrrupt Source Register FEPC FEPSW Status Saving Register during NMI Status Saving Register during NMI EIPC EIPSW Status Saving Register during interrupt Status Saving ...

Page 55: ...een used Table 3 1 Program Registers 2 Program counter This register holds the instruction address during program execution The lower 26 bits of this regis ter are valid and bits 31 to 26 are fixed to 0 If a carry occurs from bit 25 to 26 it is ignored Bit 0 is fixed to 0 and branching to an odd address cannot be performed Figure 3 2 Program Counter PC Name Usage Operation r0 Zero register Always ...

Page 56: ... Interrupt Source Register ECR No System Register Name Operand Specification LDSR Instruction STSR Instruction 0 Status saving register during interrupt EIPC Note 1 O O 1 Status saving register during interrupt EIPSW O O 2 Status saving register during NMI FEPC O O 3 Status saving register during NMI FEPSW O O 4 Interrupt source register ECR O 5 Program status word PSW O O 6 to 15 Reserved number ...

Page 57: ...ated by the saturation operation instruction this bit is set 1 but is not cleared 0 even if the operation results of subsequent instructions are not saturated To clear 0 this bit load the data in PSW Note that in a general arithmetic operation this bit is neither set 1 nor cleared 0 0 Not saturated 1 Saturated 3 CY This flag is set if carry or borrow occurs as result of operation if carry or borro...

Page 58: ...he reset entry address of the internal ROM and instruc tion processing starts By setting the PMCAL PMCAH PMCDL PMCCS PMCCT and PMCCM registers to control mode by instruction an external device can be connected to the external mem ory area The initial value of the register differs depending on the mode Table 3 3 Register Initial Values by Operation Modes 2 Flash memory programming mode µPD70F3123 o...

Page 59: ...s not guaranteed if these pins are changed during operation a µPD703123 b µPD70F3123 Remarks 1 L Low level input 2 H High level input 3 H L High level or low level input optional MODE3 MODE2 MODE1 MODE0 Operation Mode Remarks Normal operation mode L L H L Single chip mode Other than above Setting prohibited Vpp0 Vpp1 MODE3 MODE2 MODE1 MODE0 Operation Mode Remarks Normal operation mode 0 V L L H L ...

Page 60: ...orts up to 4 GB of linear address space data space during operand addressing data access Also in instruction address addressing a maximum of 64 MB of linear address space program space is supported Figure 3 5 shows the CPU address space Figure 3 5 CPU Address Space FFFFFFFFH 04000000H 03FFFFFFH 00000000H Data area 4 Gbyte linear Program area 64 Mbyte linear CPU address space ...

Page 61: ...hows the image of the virtual addressing space Physical address x0000000H can be seen as CPU address 00000000H and in addition can be seen as address 04000000H address 08000000H address F8000000H or address FC000000H Figure 3 6 Image on Address Space FFFFFFFFH FC000000H FBFFFFFFH 00000000H Internal ROM Image Image Image Internal RAM Peripheral I O External memory Physical address space x3FFFFFFH x...

Page 62: ...ontiguous like this Figure 3 7 Wrap around of Program Space Caution No instruction can be fetched from the 4 KB area of 03FFF000H to 03FFFFFFH because this area is defined as peripheral I O area Therefore do not execute any branch address calculation in which the result will reside in any part of this area 2 Data space The result of operand address calculation that exceeds 32 bits is ignored There...

Page 63: ...y Map µPD703123 703F123 Note By setting the PMCAL PMCAH PMCDL PMCCS PMCCT and PMCCM registers to control mode by instruction this area can be used as external memory area x3FFFFFFH Internal peripheral I O area Internal RAM area Access prohibitedNote Internal ROM area Single chip mode 64 Mbytes 1 Mbyte 4 Kbytes x3FFF000H x3FFEFFFH x0100000H x00FFFFFH x0000000H x3FFE800H x3FFE7FFH x3FFC000H x3FFBFFF...

Page 64: ...ses as physical internal ROM flash memory Addresses 000000H to 03FFFFH b Interrupt exception table The V850E CA1 ATOMIC increases the interrupt response speed by assigning handler addresses corresponding to interrupts exceptions The collection of these handler addresses is called an interrupt exception table which is located in the internal ROM area When an interrupt exception request is accepted ...

Page 65: ...E00 00000120H TINTOVE10 00000130H TINTCCE00 INTPE00 00000140H TINTCCE10 INTPE10 00000150H TINTCCE20 INTPE20 00000160H TINTCCE30 INTPE30 00000170H TINTCCE40 INTPE40 00000180H TINTCCE50 INTPE50 00000190H TINTOVE01 000001A0H TINTOVE11 000001B0H TINTCCE01 INTPE01 000001C0H TINTCCE11 INTPE11 000001D0H TINTCCE21 INTPE21 000001E0H TINTCCE31 INTPE31 000001F0H TINTCCE41 INTPE41 00000200H TINTCCE51 INTPE51 ...

Page 66: ...internal physical RAM Start Address of Interrupt Exception Table Interrupt Exception Source 000002D0H CAN1TRX 000002E0H CAN1ERR 000002F0H CAN2REC 00000300H CAN2TRX 00000310H CAN2ERR 00000320H CAN3REC 00000330H CAN3TRX 00000340H CAN3ERR 00000350H INTCSI0 00000360H INTCSI1 00000370H INTSER0 00000380H INTSR0 00000390H INTST0 000003A0H INTSER1 000003B0H INTSR1 000003C0H INTST1 000003D0H INTSER2 000003...

Page 67: ...ea ignoring the lower 2 bits of the address 2 For registers in which byte access is possible if half word access is executed the higher 8 bits become undefined during the read operation and the lower 8 bits of data are written to the register during the write operation 3 Addresses that are not defined as registers are reserved for future expansion If these addresses are accessed the operation is u...

Page 68: ... n AL AH DL CS CT CM 3 4 7 Recommended use of address space The architecture of the V850E CA1 ATOMIC requires that a register is utilized for address generation when accessing operand data in the data space Operand data access from instruction can be directly executed at the address in this pointer register 32 KB However the use of general registers as pointer registers decreases the number of usa...

Page 69: ...value By mapping the external memory into the 16 KB area in Figure 3 12 all resources including internal hardware can be accessed with the same pointer The zero register r0 is a register set to 0 by hardware and eliminates the need for additional regis ters for the pointer 00007FFFH R 00000000H FFFFE800H FFFFA000H Internal ROM area Internal peripheral I O area External memory area FFFFF000H FFFFEF...

Page 70: ...H FFFFF000H FFFFEFFFH FFFFC000H FFFFBFFFH 03FFE800H 03FFE7FFH 03FFF000H 03FFEFFFH 03FFC000H 03FFBFFFH 00100000H 000FFFFFH 00020000H 0001FFFFH 00000000H 03FFFFFFH 04000000H xFFFFFFFH xFFFF000H xFFFEFFFH xFFFC000H xFFFFBFFFH xFFFE800H xFFFE7FFH x0100000H x00FFFFFH x0020000H x001FFFFH x0000000H xFFFFA28H xFFFFA27H Data space Internal peripheral I O Internal peripheral I O Internal RAM Internal RAM Ex...

Page 71: ...ster PMDL R W FFFFH FFFFF024H Port DL mode register L PMDLL R W FFH FFFFF025H Port DL mode register H PMDLH R W FFH FFFFF028H Port CS mode register PMCS R W FFH FFFFF02AH Port CT mode register PMCT R W FFH FFFFF02CH Port CM mode register PMCM R W FFH FFFFF040H Port AL mode control register PMCAL R W 0000H FFFFF040H Port AL mode control register L PMCALL R W 00H FFFFF041H Port AL mode control regis...

Page 72: ...fined FFFFF0C4H DMA transfer count register 2 DBC2 R W Undefined FFFFF0C6H DMA transfer count register 3 DBC3 R W Undefined FFFFF0D0H DMA addressing control register 0 DADC0 R W 0000H FFFFF0D2H DMA addressing control register 1 DADC1 R W 0000H FFFFF0D4H DMA addressing control register 2 DADC2 R W 0000H FFFFF0D6H DMA addressing control register 3 DADC3 R W 0000H FFFFF0E0H DMA channel control regist...

Page 73: ... register PIC20 R W 47H FFFFF13AH Interrupt control register PIC21 R W 47H FFFFF13CH Interrupt control register PIC22 R W 47H FFFFF13EH Interrupt control register PIC23 R W 47H FFFFF140H Interrupt control register PIC24 R W 47H FFFFF142H Interrupt control register PIC25 R W 47H FFFFF144H Interrupt control register PIC26 R W 47H FFFFF146H Interrupt control register PIC27 R W 47H FFFFF148H Interrupt...

Page 74: ...F200H A D converter with scan mode regis ter 0 ADSCM0 R W 0000H FFFFF202H A D converter with scan mode regis ter 1 ADSCM1 R W 0000H FFFFF204H A D Voltage Detect mode register ADETM R W 0000H FFFFF210H A D conversion result register 0 ADCR0 R Undefined FFFFF212H A D conversion result register 1 ADCR1 R Undefined FFFFF214H A D conversion result register 2 ADCR2 R Undefined FFFFF216H A D conversion r...

Page 75: ...er CMD0 R W 0000H FFFFF544H Timer D0 Control register TMCD0 R W 0000H FFFFF550H Timer D1 counter TMD1 R 0000H FFFFF552H Timer D1 compare register CMD1 R W 0000H FFFFF554H Timer D1 Control register TMCD1 R W 0000H FFFFF560H Watch timer mode register WTM 0000H FFFFF570H Watch dog timer mode register WDTM 0000H FFFFF640H Timer Macro Clock Stop Register STOPTE0 R W 0000H FFFFF642H Count Clock Control ...

Page 76: ...ter_1 TBASE10 R 0000H FFFFF680H Timer Macro Clock Stop Register STOPTE1 R W 0000H FFFFF682H Count Clock Control Edge Selection Register CSE1 R W 0000H FFFFF684H Subchannel Input Event Edge Selec tion Register SESE1 R W 0000H FFFFF686H Timebases Control Register TCRE1 R W 0000H FFFFF688H Output Control Register OCTLE1 R W 0000H FFFFF68AH Capture Compare Control Register of Subchannels 0 and 5 CMSE0...

Page 77: ...ntrol Register OCTLE2 R W 0000H FFFFF6CAH Capture Compare Control Register of Subchannels 0 and 5 CMSE052 R W 0000H FFFFF6CCH Capture Compare Control Register of Subchannels 1 and 2 CMSE122 R W 0000H FFFFF6CEH Capture Compare Control Register of Subchannels 3 and 4 CMSE342 R W 0000H FFFFF6D0H Secondary Capture Compare Regis ter of Subchannel 1 CVSE12 R W 0000H FFFFF6D2H Primary Capture Compare Reg...

Page 78: ...EGREG31 R W 0000H FFFFF740H LCD segment register02 SEGREG02 R W 0000H FFFFF742H LCD segment register12 SEGREG12 R W 0000H FFFFF744H LCD segment register22 SEGREG22 R W 0000H FFFFF746H LCD segment register32 SEGREG32 R W 0000H FFFFF800H Peripheral command register PHCMD W Undefined FFFFF802H Peripheral status register PHS R W 00H FFFFF810H DMA trigger source select register 0 DTFR0 R W 00H FFFFF812...

Page 79: ... data buffer register for emulation read SIRBE0 R 0000H SIRBEL0 R 00H FFFFF908H First transmission data buffer register SOTBF0 R W 0000H SOTBFL0 R W 00H FFFFF90AH Shift register SIO0 R W 0000H SIOL0 R W 00H FFFFF910H CSI operation mode register CSIM1 R W 00H FFFFF911H Clock selection register CSIC1 R W 00H FFFFF912H Reception data buffer register SIRB1 R 0000H SIRBL1 R 00H FFFFF914H Transmission d...

Page 80: ...ffer register TXB1 R W 00H FFFFFA15H UART transmission error status regis ter ASIF1 R FFH FFFFFA16H Clock selection register CHKSR1 R W 00H FFFFFA17H Baudrate definition register BRGC1 R W FFH FFFFFA20H UART operation mode register ASIM2 R W 00H FFFFFA22H Reception buffer register RXB2 R FFH FFFFFA23H UART reception error status register ASIS2 R 00H FFFFFA24H Transmission buffer register TXB2 R W ...

Page 81: ...peripheral I O register since peripheral I O register area is allocated to the last 4 KB of the programmable peripheral I O register area Figure 3 14 Programmable Peripheral I O Register Outline Cautions 1 The CAN message buffer register can allocate address xxxx freely as a program mable peripheral I O register but once the address xxxx is set it cannot be changed 2 If the programmable peripheral...

Page 82: ...ss Initial value BPC PA15 0 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 FFFFF064H 0000H Bit Position Bit Name Function 15 PA15 Enables disables usage of programmable peripheral I O area PA15 Usage of Programmable Peripheral I O Area 0 Disables usage of programmable peripheral I O area 1 Enables usage of programmable peripheral I O area 13 to 0 PA13 to PA0 Specifies an address in pr...

Page 83: ..._IDH00 R W x Undefined xxxxn014H CAN message configuration register 00 M_CONF00 R W x Undefined xxxxn015H CAN message status register 00 M_STAT00 R x Undefined xxxxn016H CAN status set cancel register 00 SC_STAT00 W x 0000H xxxxn020H CAN message event pointer 010 M_EVT010 R W x Undefined xxxxn021H CAN message event pointer 011 M_EVT011 R W x Undefined xxxxn022H CAN message event pointer 012 M_EVT0...

Page 84: ...R W x Undefined xxxxn062H CAN message event pointer 032 M_EVT032 R W x Undefined xxxxn063H CAN message event pointer 033 M_EVT033 R W x Undefined xxxxn064H CAN message data length register 03 M_DLC03 R W x Undefined xxxxn065H CAN message control register 03 M_CTRL03 R W x Undefined xxxxn066H CAN message time stamp register 03 M_TIME03 R W x Undefined xxxxn068H CAN message data register 030 M_DATA0...

Page 85: ...W x Undefined xxxxn0A5H CAN message control register 05 M_DTRL05 R W x Undefined xxxxn0A6H CAN message time stamp register 05 M_TIME05 R W x Undefined xxxxn0A8H CAN message data register 050 M_DATA050 R W x Undefined xxxxn0A9H CAN message data register 051 M_DATA051 R W x Undefined xxxxn0AAH CAN message data register 052 M_DATA052 R W x Undefined xxxxn0ABH CAN message data register 053 M_DATA053 R...

Page 86: ... W x Undefined xxxxn0E9H CAN message data register 071 M_DATA071 R W x Undefined xxxxn0EAH CAN message data register 072 M_DATA072 R W x Undefined xxxxn0EBH CAN message data register 073 M_DATA073 R W x Undefined xxxxn0ECH CAN message data register 074 M_DATA074 R W x Undefined xxxxn0EDH CAN message data register 075 M_DATA075 R W x Undefined xxxxn0EEH CAN message data register 076 M_DATA076 R W x...

Page 87: ...R W x Undefined xxxxn12CH CAN message data register 094 M_DATA094 R W x Undefined xxxxn12DH CAN message data register 095 M_DATA095 R W x Undefined xxxxn12EH CAN message data register 096 M_DATA096 R W x Undefined xxxxn12FH CAN message data register 097 M_DATA097 R W x Undefined xxxxn130H CAN message ID register L09 M_IDL09 R W x Undefined xxxxn132H CAN message ID register H09 M_IDH09 R W x Undefi...

Page 88: ... R W x Undefined xxxxn16FH CAN message data register 117 M_DATA117 R W x Undefined xxxxn170H CAN message ID register L11 M_IDL11 R W x Undefined xxxxn172H CAN message ID register H11 M_IDH11 R W x Undefined xxxxn174H CAN message configuration register 11 M_CONF11 R W x Undefined xxxxn175H CAN message status register 11 M_STAT11 R x Undefined xxxxn176H CAN status set cancel register 11 SC_STAT11 W ...

Page 89: ... Undefined xxxxn1B4H CAN message configuration register 13 M_CONF13 R W x Undefined xxxxn1B5H CAN message status register 13 M_STAT13 R x Undefined xxxxn1B6H CAN status set cancel register 13 SC_STAT13 W x 0000H xxxxn1C0H CAN message event pointer 140 M_EVT140 R W x Undefined xxxxn1C1H CAN message event pointer 141 M_EVT141 R W x Undefined xxxxn1C2H CAN message event pointer 142 M_EVT142 R W x Und...

Page 90: ...AT15 W x 0000H xxxxn200H CAN message event pointer 160 M_EVT160 R W x Undefined xxxxn201H CAN message event pointer 161 M_EVT161 R W x Undefined xxxxn202H CAN message event pointer 162 M_EVT162 R W x Undefined xxxxn203H CAN message event pointer 163 M_EVT163 R W x Undefined xxxxn204H CAN message data length register 16 M_DLC16 R W x Undefined xxxxn205H CAN message control register 16 M_CTRL16 R W ...

Page 91: ... x Undefined xxxxn243H CAN message event pointer 183 M_EVT183 R W x Undefined xxxxn244H CAN message data length register 18 M_DLC18 R W x Undefined xxxxn245H CAN message control register 18 M_CTRL18 R W x Undefined xxxxn246H CAN message time stamp register 18 M_TIME18 R W x Undefined xxxxn248H CAN message data register 180 M_DATA180 R W x Undefined xxxxn249H CAN message data register 181 M_DATA181...

Page 92: ... x Undefined xxxxn286H CAN message time stamp register 20 M_TIME20 R W x Undefined xxxxn288H CAN message data register 200 M_DATA200 R W x Undefined xxxxn289H CAN message data register 201 M_DATA201 R W x Undefined xxxxn28AH CAN message data register 202 M_DATA202 R W x Undefined xxxxn28BH CAN message data register 203 M_DATA203 R W x Undefined xxxxn28CH CAN message data register 204 M_DATA204 R W...

Page 93: ... W x Undefined xxxxn2CAH CAN message data register 222 M_DATA222 R W x Undefined xxxxn2CBH CAN message data register 223 M_DATA223 R W x Undefined xxxxn2CCH CAN message data register 224 M_DATA224 R W x Undefined xxxxn2CDH CAN message data register 225 M_DATA225 R W x Undefined xxxxn2CEH CAN message data register 226 M_DATA226 R W x Undefined xxxxn2CFH CAN message data register 227 M_DATA227 R W x...

Page 94: ... W x Undefined xxxxn30DH CAN message data register 245 M_DATA245 R W x Undefined xxxxn30EH CAN message data register 246 M_DATA246 R W x Undefined xxxxn30FH CAN message data register 247 M_DATA247 R W x Undefined xxxxn310H CAN message ID register L24 M_IDL24 R W x Undefined xxxxn312H CAN message ID register H24 M_IDH24 R W x Undefined xxxxn314H CAN message configuration register 24 M_CONF24 R W x ...

Page 95: ...67 R W x Undefined xxxxn350H CAN message ID register L26 M_IDL26 R W x Undefined xxxxn352H CAN message ID register H26 M_IDH26 R W x Undefined xxxxn354H CAN message configuration register 26 M_CONF26 R W x Undefined xxxxn355H CAN message status register 26 M_STAT26 R x Undefined xxxxn356H CAN status set cancel register 26 SC_STAT26 W x 0000H xxxxn360H CAN message event pointer 270 M_EVT270 R W x U...

Page 96: ...F28 R W x Undefined xxxxn395H CAN message status register 28 M_STAT28 R x Undefined xxxxn396H CAN status set cancel register 28 SC_STAT28 W x 0000H xxxxn3A0H CAN message event pointer 290 M_EVT290 R W x Undefined xxxxn3A1H CAN message event pointer 291 M_EVT291 R W x Undefined xxxxn3A2H CAN message event pointer 292 M_EVT292 R W x Undefined xxxxn3A3H CAN message event pointer 293 M_EVT293 R W x Un...

Page 97: ... W x Undefined xxxxn3E1H CAN message event pointer 311 M_EVT311 R W x Undefined xxxxn3E2H CAN message event pointer 312 M_EVT312 R W x Undefined xxxxn3E3H CAN message event pointer 313 M_EVT313 R W x Undefined xxxxn3E4H CAN message data length register 31 M_DLC31 R W x Undefined xxxxn3E5H CAN message control register 31 M_CTRL31 R W x Undefined xxxxn3E6H CAN message time stamp register 31 M_TIME31...

Page 98: ...x Undefined xxxxn424H CAN message data length register 33 M_DLC33 R W x Undefined xxxxn425H CAN message control register 33 M_CTRL33 R W x Undefined xxxxn426H CAN message time stamp register 33 M_TIME33 R W x Undefined xxxxn428H CAN message data register 330 M_DATA330 R W x Undefined xxxxn429H CAN message data register 331 M_DATA331 R W x Undefined xxxxn42AH CAN message data register 332 M_DATA332...

Page 99: ... R W x Undefined xxxxn468H CAN message data register 350 M_DATA350 R W x Undefined xxxxn469H CAN message data register 351 M_DATA351 R W x Undefined xxxxn46AH CAN message data register 352 M_DATA352 R W x Undefined xxxxn46BH CAN message data register 353 M_DATA353 R W x Undefined xxxxn46CH CAN message data register 354 M_DATA354 R W x Undefined xxxxn46DH CAN message data register 355 M_DATA355 R W...

Page 100: ... W x Undefined xxxxn4ABH CAN message data register 373 M_DATA373 R W x Undefined xxxxn4ACH CAN message data register 374 M_DATA374 R W x Undefined xxxxn4ADH CAN message data register 375 M_DATA375 R W x Undefined xxxxn4AEH CAN message data register 376 M_DATA376 R W x Undefined xxxxn4AFH CAN message data register 377 M_DATA377 R W x Undefined xxxxn4B0H CAN message ID register L37 M_IDL37 R W x Und...

Page 101: ... W x Undefined xxxxn4EEH CAN message data register 396 M_DATA396 R W x Undefined xxxxn4EFH CAN message data register 397 M_DATA397 R W x Undefined xxxxn4F0H CAN message ID register L39 M_IDL39 R W x Undefined xxxxn4F2H CAN message ID register H39 M_IDH39 R W x Undefined xxxxn4F4H CAN message configuration register 39 M_CONF39 R W x Undefined xxxxn4F5H CAN message status register 39 M_STAT39 R x Un...

Page 102: ... x Undefined xxxxn532H CAN message ID register H41 M_IDH41 R W x Undefined xxxxn534H CAN message configuration register 41 M_CONF41 R W x Undefined xxxxn535H CAN message status register 41 M_STAT41 R x Undefined xxxxn536H CAN status set cancel register 41 SC_STAT41 W x 0000H xxxxn540H CAN message event pointer420 M_EVT420 R W x Undefined xxxxn541H CAN message event pointer 421 M_EVT421 R W x Undef...

Page 103: ...3 R x Undefined xxxxn576H CAN status set cancel register 43 SC_STAT43 W x 0000H xxxxn580H CAN message event pointer 440 M_EVT440 R W x Undefined xxxxn581H CAN message event pointer 441 M_EVT441 R W x Undefined xxxxn582H CAN message event pointer 442 M_EVT442 R W x Undefined xxxxn583H CAN message event pointer 443 M_EVT43 R W x Undefined xxxxn584H CAN message data length register 44 M_DLC44 R W x U...

Page 104: ...R W x Undefined xxxxn5C2H CAN message event pointer 462 M_EVT462 R W x Undefined xxxxn5C3H CAN message event pointer 463 M_EVT463 R W x Undefined xxxxn5C4H CAN message data length register 46 M_DLC46 R W x Undefined xxxxn5C5H CAN message control register 46 M_CTRL46 R W x Undefined xxxxn5C6H CAN message time stamp register 46 M_TIME46 R W x Undefined xxxxn5C8H CAN message data register 460 M_DATA4...

Page 105: ... W x Undefined xxxxn605H CAN message control register 48 M_CTRL48 R W x Undefined xxxxn606H CAN message time stamp register 48 M_TIME48 R W x Undefined xxxxn608H CAN message data register 480 M_DATA480 R W x Undefined xxxxn609H CAN message data register 481 M_DATA481 R W x Undefined xxxxn60AH CAN message data register 482 M_DATA482 R W x Undefined xxxxn60BH CAN message data register 483 M_DATA483 ...

Page 106: ...R W x Undefined xxxxn649H CAN message data register 501 M_DATA501 R W x Undefined xxxxn64AH CAN message data register 502 M_DATA502 R W x Undefined xxxxn64BH CAN message data register 503 M_DATA503 R W x Undefined xxxxn64CH CAN message data register 504 M_DATA504 R W x Undefined xxxxn64DH CAN message data register 505 M_DATA505 R W x Undefined xxxxn64EH CAN message data register 506 M_DATA506 R W ...

Page 107: ... W x Undefined xxxxn68CH CAN message data register 524 M_DATA524 R W x Undefined xxxxn68DH CAN message data register 525 M_DATA525 R W x Undefined xxxxn68EH CAN message data register 526 M_DATA526 R W x Undefined xxxxn68FH CAN message data register 527 M_DATA527 R W x Undefined xxxxn690H CAN message ID register L52 M_IDL52 R W x Undefined xxxxn692H CAN message ID register H52 M_IDH52 R W x Undefin...

Page 108: ...6 R W x Undefined xxxxn6CFH CAN message data register 547 M_DATA547 R W x Undefined xxxxn6D0H CAN message ID register L54 M_IDL54 R W x Undefined xxxxn6D2H CAN message ID register H54 M_IDH54 R W x Undefined xxxxn6D4H CAN message configuration register 54 M_CONF54 R W x Undefined xxxxn6D5H CAN message status register 54 M_STAT54 R x Undefined xxxxn6D6H CAN status set cancel register 54 SC_STAT54 W...

Page 109: ... Undefined xxxxn714H CAN message configuration register 56 M_CONF56 R W x Undefined xxxxn715H CAN message status register 56 M_STAT56 R x Undefined xxxxn716H CAN status set cancel register 56 SC_STAT56 W x 0000H xxxxn720H CAN message event pointer 570 M_EVT570 R W x Undefined xxxxn721H CAN message event pointer 571 M_EVT571 R W x Undefined xxxxn722H CAN message event pointer 572 M_EVT572 R W x Und...

Page 110: ...AT58 W x 0000H xxxxn760H CAN message event pointer 590 M_EVT590 R W x Undefined xxxxn761H CAN message event pointer 591 M_EVT591 R W x Undefined xxxxn762H CAN message event pointer 592 M_EVT592 R W x Undefined xxxxn763H CAN message event pointer 593 M_EVT593 R W x Undefined xxxxn764H CAN message data length register 59 M_DLC59 R W x Undefined xxxxn765H CAN message control register 59 M_CTRL59 R W ...

Page 111: ... x Undefined xxxxn7A3H CAN message event pointer 613 M_EVT613 R W x Undefined xxxxn7A4H CAN message data length register 61 M_DLC61 R W x Undefined xxxxn7A5H CAN message control register 61 M_CTRL61 R W x Undefined xxxxn7A6H CAN message time stamp register 61 M_TIME61 R W x Undefined xxxxn7A8H CAN message data register 610 M_DATA610 R W x Undefined xxxxn7A9H CAN message data register 611 M_DATA611...

Page 112: ...E5H CAN message control register 63 M_CTRL63 R W x Undefined xxxxn7E6H CAN message time stamp register 63 M_TIME63 R W x Undefined xxxxn7E8H CAN message data register 630 M_DATA630 R W x Undefined xxxxn7E9H CAN message data register 631 M_DATA631 R W x Undefined xxxxn7EAH CAN message data register 632 M_DATA632 R W x Undefined xxxxn7EBH CAN message data register 633 M_DATA633 R W x Undefined xxxxn...

Page 113: ... enable register Note C1IE R W x x 0000H xxxxn85AH CAN1 bus active register C1BA R x x 00FFH xxxxn85CH CAN1 bit rate prescaler register C1BRP R W x x 0000H xxxxn85DH CAN1 bus diagnostic information regis ter C1DINF R x x 0000H xxxxn85EH CAN1 synchronization control register C1SYNC R W x x 0218H xxxxn880H CAN2 address mask register L0 C2MASKL0 R W x x Undefined xxxxn882H CAN2 address mask register ...

Page 114: ...N3 information register C3LAST R x x 00FFH xxxxn8D6H CAN3 error counter register C3ERC R x x 0000H xxxxn8D8H CAN3 interrupt enable register Note C3IE R W x x 0000H xxxxn8DAH CAN3 bus active register C3BA R x x 00FFH xxxxn8DCH CAN3 bit rate prescaler register C3BRP R W x x 0000H xxxxn8DDH CAN3 bus diagnostic information regis ter C3DINF R x x 0000H xxxxn8DEH CAN3 synchronization control register C3...

Page 115: ...tion Examples 1 1 MOV 0x04 r10 2 ST B r10 PRCMD r0 3 ST B r10 PSC r0 4 NOP dummy instruction 5 times NOP required No special sequence is required when reading the specific registers Remarks 1 A store instruction to a command register will not be received with an interrupt This presupposes that this is done with the continuous store instructions in 1 and 2 above in the program If another instructio...

Page 116: ...ster PHCMD is to protect the registers that may have a significant influence on the application system CKC from an inadvertent write access so that the system does not stop in case of a program hang up This register can be only written in 8 bit units undefined data is used when this register is read Only the first write access to a specific on chip register hereafter referred to as a specific regi...

Page 117: ...ing a protection error Writing 0 to the PRERR flag after the value is checked clears the error Operation conditions of PRERR flag Set condition 1 If the most recent store instruction for peripheral I O register operation is not an operation to write the PHCMD register and if data is written to the specific register 2 If the first store instruction operation after data has been written to the PHCMD...

Page 118: ...SWL1 VSWL0 FFFFF06EH R W 77H 0 1 1 1 0 1 1 1 Bit Name Description SUWL2 SUWL1 SUWL0 Setup wait for internal peripheral bus length SUWL2 SUWL1 SUWL0 Number of data wait states n 7 0 0 0 0 0 0 0 1 1 system clock 0 1 0 2 system clock 0 1 1 3 system clock 1 0 0 4 system clock 1 0 1 5 system clock 1 1 0 6 system clock 1 1 1 7 system clock default VSWL2 VSWL1 VSWL0 internal peripheral bus wait length VS...

Page 119: ...e insertion function Bus mastership arbitration function Bus hold function External device connection can be enabled via bus control port alternate function pins 4 2 Bus Control Pins The following pins are used for connecting to external devices Bus Control Pin Function when in Control Mode Function when in Port Mode Register for Port Control Mode Switching Address data Data bus D0 to D15 PDL0 to ...

Page 120: ... 3800000H 37FFFFFH 3400000H 33FFFFFH 3000000H 2FFFFFFH 2800000H 27FFFFFH 1000000H 0FFFFFFH 0C00000H 0BFFFFFH 0400000H 03FFFFFH 0200000H 01FFFFFH 0000000H Block 1 2 Mbytes Block 0 2 Mbytes Block 3 2 Mbytes Block 13 2 Mbytes Block 14 2 Mbytes Block 12 2 Mbytes Block 15 2 Mbytes 0100000H Internal ROM area 1 Mbyte 0000000H CS7 CS5 CS6 CS4 CS6 CS4 CS4 CS3 Block 11 4 Mbytes Block 10 4 Mbytes Block 9 8 M...

Page 121: ...l I O area CS7 CS5 CS6 CS4 Note If both the CS0n and CS2n bits of the CSC0 register are set to 0 CS1 becomes active to the corre sponding block n 0 to 3 Similarly if both the CS5n and CS7n bits of the CSC1 register are set to 0 CS6 becomes active to the corresponding block n 0 to 3 Note Not all the chip area select signals are externally available on output pins Even so enabling chip area select s...

Page 122: ... access CS23 CS2 active during block 3 access CS30 CS3 active during block 0 1 2 or 3 access CS31 CS3 active during block 4 or 5 access CS32 CS3 active during block 6 access CS33 CS3 active during block 7 access CS40 CS4 active during block 12 13 14 or 15 access CS41 CS4 active during block 10 or 11 access CS42 CS4 active during block 9 access CS43 CS4 active during block 8 access CS50 CS5 active ...

Page 123: ...BCT1 registers is finished How ever it is possible to access external memory areas whose initialization has been finished 2 The Bits marked as 0 are reserved It have to leave to 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value BCT0 ME3 0 0 BT300 ME2 0 0 BT200 ME1 0 0 BT100 ME0 0 0 BT00 FFFFF480H 8888H CS3 CS2 CS1 CS0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value BCT1 ME7...

Page 124: ...of the BSC register is finished However it is possible to access external memory areas whose initialization has been finished 2 When the data bus width is specified as 8 bits only the LWR signal becomes active 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value BSC 0 BS70 0 BS60 0 BS50 0 BS40 0 BS30 0 BS20 0 BS10 0 BS00 FFFFF066H 5555H CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0 Bit Position Bit Name ...

Page 125: ...Endian format n 0 to 7 3 In the following areas the data processing method is fixed to Little Endian method Any setting of Big Endian method for these areas according to the BEC register is invalid On chip peripheral I O area Internal ROM area Internal RAM area Fetch area of external memory Figure 4 3 Big Endian Addresses within Word Figure 4 4 Little Endian Addresses within Word 15 14 13 12 11 10...

Page 126: ... starting from the lower order side 1 Byte access 8 bits a When the data bus width is 16 bits Little Endian 1 Access to even address 2n 2 Access to odd address 2n 1 b When the data bus width is 8 bits Little Endian 1 Access to even address 2n 2 Access to odd address 2n 1 7 0 7 0 Byte data 15 8 External data bus 2n Address 7 0 7 0 Byte data 15 8 External data bus 2n 1 Address 7 0 7 0 Byte data Exte...

Page 127: ...ddress 2n 2 Access to odd address 2n 1 d When the data bus width is 8 bits Big Endian 1 Access to even address 2n 2 Access to odd address 2n 1 7 0 7 0 Byte data 15 8 External data bus 2n Address 7 0 7 0 Byte data 15 8 External data bus 2n 1 Address 7 0 7 0 Byte data External data bus 2n Address 7 0 7 0 Byte data External data bus 2n 1 Address ...

Page 128: ...dress 2n 1 1 st Access 2 nd Access 7 0 7 0 Halfword data 15 8 15 8 External data bus 2n 1 Address 7 0 7 0 Halfword data 15 8 15 8 External data bus 2n 2 Address 7 0 7 0 Halfword data 15 8 External data bus 2n Address 15 8 2n 1 7 0 7 0 Halfword data 15 8 External data bus Address 7 0 7 0 Halfword data 15 8 External data bus 2n 1 Address 2n 1 st Access 2 nd Access 1 st Access 2 nd Access 7 0 7 0 Hal...

Page 129: ...t Access 2 nd Access 7 0 7 0 Halfword data 15 8 External data bus 2n 1 Address 15 8 2n 7 0 7 0 Halfword data 15 8 15 8 External data bus 2n 1 Address 7 0 7 0 Halfword data 15 8 15 8 External data bus 2n 2 Address 1 st Access 2 nd Access 1 st Access 2 nd Access 7 0 7 0 Halfword data 15 8 External data bus 2n Address 7 0 7 0 Halfword data 15 8 External data bus 2n 1 Address 7 0 7 0 Halfword data 15 ...

Page 130: ...a 15 8 External data bus 4n Address 15 8 4n 1 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 2 Address 15 8 4n 3 23 16 31 24 1 st Access 2 nd Access 7 0 7 0 Word data 15 8 External data bus Address 15 8 4n 1 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 2 Address 15 8 4n 3 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 4 Address 15 8 23 16 31 24 1 st Access 2 nd Access ...

Page 131: ...ess 15 8 4n 3 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 4 Address 15 8 4n 5 23 16 31 24 1 st Access 2 nd Access 7 0 7 0 Word data 15 8 External data bus Address 15 8 4n 3 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 4 Address 15 8 4n 5 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 6 Address 15 8 23 16 31 24 1 st Access 2 nd Access 3 rd Access ...

Page 132: ...1 24 7 0 7 0 Word data External data bus 4n 2 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 3 Address 15 8 23 16 31 24 1 st Access 2 nd Access 3 rd Access 4 th Access 7 0 7 0 Word data External data bus Address 15 8 4n 1 23 16 31 24 7 0 7 0 Word data External data bus 4n 2 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 3 Address 15 8 23 16 31 24 7 0 7 0 Word data...

Page 133: ...ta External data bus 4n 4 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 5 Address 15 8 23 16 31 24 1 st Access 2 nd Access 3 rd Access 4 th Access 7 0 7 0 Word data External data bus Address 15 8 4n 3 23 16 31 24 7 0 7 0 Word data External data bus 4n 4 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 5 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4...

Page 134: ...ernal data bus 4n 3 Addres 15 8 4n 2 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 1 Address 15 8 4n 23 16 31 24 1 st Access 2 nd Access 7 0 7 0 Word data 15 8 External data bus Address 15 8 4n 1 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 3 Address 15 8 4n 2 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 4 Address 15 8 23 16 31 24 1 st Access 2 nd Access 3 rd Access...

Page 135: ...ess 15 8 4n 4 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 3 Address 15 8 4n 2 23 16 31 24 1 st Access 2 nd Access 7 0 7 0 Word data 15 8 External data bus Address 15 8 4n 3 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 5 Address 15 8 4n 4 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 6 Address 15 8 23 16 31 24 1 st Access 2 nd Access 3 rd Access ...

Page 136: ...6 31 24 7 0 7 0 Word data External data bus 4n 1 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n Address 15 8 23 16 31 24 1 st Access 2 nd Access 3 rd Access 4 th Access 7 0 7 0 Word data External data bus Address 15 8 4n 4 23 16 31 24 7 0 7 0 Word data External data bus 4n 3 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 2 Address 15 8 23 16 31 24 7 0 7 0 Word dat...

Page 137: ...ta External data bus 4n 3 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 2 Address 15 8 23 16 31 24 1 st Access 2 nd Access 3 rd Access 4 th Access 7 0 7 0 Word data External data bus Address 15 8 4n 6 23 16 31 24 7 0 7 0 Word data External data bus 4n 5 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 4 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4...

Page 138: ...e settings of registers DWC0 and DWC1 are invalid wait control is performed by each memory controller Page ROM on page access 3 Write to the DWC0 and DWC1 registers after reset and then do not change the set values Also do not access an external memory area other than that for this initial ization routine until initial setting of the DWC0 and DWC1 registers is finished However it is possible to ac...

Page 139: ...ten in 16 bit units Remark During address setup wait the external wait function is disabled by the WAIT pin 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value ASC AC71 AC70 AC61 AC60 AC51 AC50 AC41 AC40 AC31 AC30 AC21 AC20 AC11 AC10 AC01 AC00 FFFFF48AH FFFFH CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0 Bit Position Bit Name Function 15 to 0 ACn1 ACn0 n 0 to 7 Address Cycle Specifies the number of addr...

Page 140: ... hold time at sampling timing is not satisfied the wait state may or may not be inserted in the next state 4 6 3 Relationship between programmable wait and external wait A wait cycle is inserted as the result of an OR operation between the wait cycle specified by the set value of the programmable wait and the wait cycle controlled by the WAIT pin In other words the number of wait cycles is determi...

Page 141: ... automatically programmed for all memory blocks 1 Bus cycle control register BCC This register can be read written in 16 bit units Cautions 1 The internal ROM area internal RAM area and internal peripheral I O area are not subject to insertion of an idle state 2 Write to the BCC register after reset and then do not change the set value Also do not access an external memory area other than that for...

Page 142: ...ty has the DMA cycle instruction fetch and operand data access in this order An instruction fetch may be inserted between read access and write access during read modify write access Also an instruction fetch may be inserted between bus access and bus access during CPU bus clock Table 4 2 Bus Priority Order Priority Order External Bus Cycle Bus Master High Low DMA cycle DMA controller Operand data...

Page 143: ...Data space The V850E CA1 ATOMIC is provided with an address misalign function Through this function regardless of the data format word data halfword data or byte data data can be placed in all addresses However in the case of word data and halfword data if data are not sub jected to boundary alignment the bus cycle will be generated a minimum of 2 times and bus efficiency will drop 1 In the case o...

Page 144: ...144 Preliminary User s Manual U14913EE1V0UM00 MEMO ...

Page 145: ...akes a minimum of 2 states Up to 7 states of programmable data waits can be inserted through setting of the DWC0 and DWC1 registers Data wait can be controlled with input pin WAIT Up to 3 idle states can be inserted after the read write cycle through setting of the BCC register Up to 3 address set up wait starts can be inserted through setting of the ASC register ...

Page 146: ...tion to SRAM a When data bus width is 16 bits b When data bus width is 8 bits Remark CSn CS2 to CS4 2 Mbit SRAM 256 Kwords x 16 bits V850E CA1 D0 to D15 CSn LWR UWR LBE UBE RD WE A1 to A17 A1 to A17 D1 to D16 CS OE A0 to A16 D1 to D8 1 Mbit SRAM 128 Kwords x 8 bits CS OE WE A1 to A17 D0 to D7 CSn RD LWR D8 to D15 V850E CA1 UWR A0 to A16 D1 to D8 1 Mbit SRAM 128 Kwords x 8 bits CS OE WE ...

Page 147: ...igure 5 2 SRAM External ROM External I O Access Timing 1 6 a During read Remarks 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS2 to CS4 T1 T2 Address Data WAIT input D0 to D15 I O LWR output UWR output RD output CSn output A0 to A23 output CLKOUT output Data Address TW T2 T1 ...

Page 148: ...l I O Access Timing 2 6 b During read address setup wait idle state insertion Remarks 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS2 to CS4 TASW T1 Address Data WAIT input D0 to D15 I O LWR output UWR output RD output CSn output A0 to A23 output CLKOUT output TI T2 ...

Page 149: ...l ROM External I O Access Timing 3 6 c During write Remarks 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS2 to CS4 T1 T2 Address Data WAIT input D0 to D15 I O LWR output UWR output RD output A0 to A23 output CLKOUT output Data Address TW T2 T1 CSn output ...

Page 150: ...l I O Access Timing 4 6 d During write address setup wait idle state insertion Remarks 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS2 to CS4 TASW T1 Address Data WAIT input D0 to D15 I O LWR output UWR output RD output A0 to A23 output CLKOUT output TI T2 CSn output ...

Page 151: ... ROM External I O Access Timing 5 6 e When read write operation Remarks 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS2 to CS4 T1 T2 Address Data Data WAIT input D0 to D15 I O LWR output UWR output RD output A0 to A23 output CLKOUT output T2 T1 CSn output ...

Page 152: ... ROM External I O Access Timing 6 6 f When write read operation Remarks 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS2 to CS4 T1 T2 Address Data WAIT input D0 to D15 I O LWR output UWR output RD output A0 to A23 output CLKOUT output T2 T1 CSn output Data ...

Page 153: ... 5 2 1 Features Direct connection to 8 bit 16 bit page ROM supported In case of 16 bit bus width 4 8 16 32 64 word page access supported In case of 8 bit bus width 8 16 32 64 128 word page access supported Page ROM access a minimum of 2 states On page judgment function Addresses to be compared can be changed through setting of the PRC register Up to 7 states of programmable data waits can be inser...

Page 154: ...le of Page ROM Connections a In case of 16 bit data bus width b In case of 8 bit data bus width Remark CSn CS2 to CS4 A0 to A19 O1 to O16 CE OE 16 Mbit page ROM 1 Mword x 16 bits A1 to A20 D0 to D15 CSn RD V850E CA1 A0 to A20 O1 to O8 CE OE 16 Mbit page ROM 2 Mwords x 8 bits A1 to A21 D0 to D7 CSn RD D8 to D15 V850E CA1 A0 to A20 O1 to O8 CE OE 16 Mbit page ROM 2 Mwords x 8 bits ...

Page 155: ... of 16 Mbit 1 M 16 bits page ROM 4 word page access b In case of 16 Mbit 1 M 16 bits page ROM 8 word page access a23 a22 a21 a20 a7 a6 a5 a4 a3 A23 A22 A21 A20 A7 A6 A5 A4 A3 A2 A1 A1 A0 A0 Internal address latch immediately preceding address V850E CA1 address output Page ROM address A19 Off page address On page address A6 A5 A4 A3 A2 MA6 0 MA5 0 MA4 0 MA3 0 PRC register setting Comparison Continu...

Page 156: ... M 16 bits page ROM 16 word page access a23 a22 a21 a20 a7 a6 a5 a4 a3 A23 A22 A21 A20 A7 A6 A5 A4 A3 A2 A1 A1 A0 A0 Internal address latch immediately preceding address V850E CA1 address output Page ROM address A19 Off page address On page address Continuous reading possible 16 bit data bus width 16 words A6 A5 A4 A3 A2 MA6 0 MA5 0 MA4 1 MA3 1 PRC register setting Comparison ...

Page 157: ...emory areas whose initialization has been finished 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value PRC 0 PRW2 PRW1 PRW0 0 0 0 0 0 0 0 0 MA6 MA5 MA4 MA3 FFFFF49AH 7000H Bit Position Bit Name Function 14 to 12 PRW2 to PRW0 Page ROM On page Wait Control Sets the number of waits corresponding to the internal system clock The number of waits set by this bit are inserted only when on page Wh...

Page 158: ...word word access with 8 bit bus width or when word access with 16 bit bus width Remarks 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS2 to CS4 T1 TW Off page address Data WAIT input D0 to D15 I O D0 to D7 I O LWR output UWR output RD output CSn output A0 to A23 output CLKOUT output Data On page address TO1 TO2 T2 ...

Page 159: ... 8 bit bus width or when byte half word access with 16 bit bus width Remarks 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS2 to CS4 T1 TW Off page address Data WAIT input D0 to D15 I O D0 to D7 I O LWR output UWR output RD output CSn output A0 to A23 output CLKOUT output Data On page address TO1 TO2 T2 ...

Page 160: ...alf word word access with 8 bit bus width or when word access with 16 bit bus width Remarks 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS2 to CS4 TASW T1 Off page address Data WAIT input D0 to D15 I O D0 to D7 I O LWR output UWR output RD output CSn output A0 to A23 output CLKOUT output Data On page address TASW TO1 TO2 TI T2 ...

Page 161: ...yte access with 8 bit bus width or when byte half word access with 16 bit bus width Remarks 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS2 to CS4 TASW T1 Off page address Data WAIT input D0 to D15 I O D0 to D7 I O LWR output UWR output RD output CSn output A0 to A23 output CLKOUT output Data On page address TASW TO1 TO2 TI T2 ...

Page 162: ...162 Preliminary User s Manual U14913EE1V0UM00 MEMO ...

Page 163: ...s issued by the on chip peripheral I O or software triggers memory refers to internal RAM 6 1 Features 4 independent DMA channels Transfer units 8 16 and 32 bits Maximum transfer count 65 536 216 Two cycle transfer Three transfer modes Single transfer mode Single step transfer mode Block transfer mode Transfer requests Request by interrupts from on chip peripheral I O Requests by software trigger ...

Page 164: ... On chip peripheral I O bus Internal bus Data control Address control Count control Channel control DMAC V850E CA1 Bus interface DMA source address register DSAHn DSALn DMA transfer count register DBCn DMA channel control register DCHCn DMA destination address register DDAHn DDALn DMA addressing control register DADCn DMA disable status register DDIS DMA trigger factor register DTFRn DMA restart r...

Page 165: ...riph eral I O register image 3FFF000H to 3FFFFFFH must not be specified Figure 6 2 DMA Source Address Registers H0 to H3 DSAH0 to DSAH3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DSAH0 IR 0 0 0 SA26 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 FFFFF082H undef 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DSAH1 IR 0 0 0 SA26 SA26 SA25 SA24 SA23 SA22 SA21 SA2...

Page 166: ...5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DSAL1 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 FFFFF088H undef 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DSAL2 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 FFFFF090H undef 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DSAL3 SA15 SA14 SA13 SA12 SA11 SA10 S...

Page 167: ...I O register image 3FFF000H to 3FFFFFFH must not be specified Figure 6 4 DMA Destination Address Registers 0H to 3H DDA0H to DDA3H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DDAH0 IR 0 0 0 DA27 DA26 DA25 DA24 DA23 DA22 DA21 DA20 DA19 DA18 DA17 DA16 FFFFF086H undef 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DDAH1 IR 0 0 0 DA27 DA26 DA25 DA24 DA23 DA22 DA21 DA20 DA1...

Page 168: ...5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DDAL1 DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 FFFFF08CH undef 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DDAL2 DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 FFFFF094H undef 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DDAL3 DA15 DA14 DA13 DA12 DA11 DA10 D...

Page 169: ...e read written in 16 bit units Figure 6 6 DMA Transfer Count Registers 0 to 3 DBC0 to DBC3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DBC0 BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 BC7 BC6 BC5 BC4 BC3 B2C BC1 BC0 FFFFF0C0H undef 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DBC1 BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 BC7 BC6 BC5 BC4 BC3 B2C BC1 BC0 FFFFF0C2H undef 15 14 1...

Page 170: ... TM0 0 0 FFFFF0D4H 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value DADC3 DS1 DS0 0 0 0 0 0 0 SAD1 SAD0 DAD1 DAD0 TM1 TM0 0 0 FFFFF0D6H 0000H Bit Position Bit Name Function 15 14 DS1 DS0 Sets the transfer data size for DMA transfer DS1 DS0 Transfer Data Size 0 0 8 bits 0 1 16 bits 1 0 32 bits 1 1 Setting prohibited For the peripheral I O and programmable peripheral I O registers e...

Page 171: ...ansfer through DMA channel n has ended or not It is read only and is set to 1 when DMA transfer ends and cleared 0 when it is read 0 DMA transfer had not ended 1 DMA transfer had ended 3 MLEn When this bit is set to 1 at terminal count output the Enn bit is not cleared to 0 and the DMA transfer enable state is retained Moreover the next DMA transfer request can be accepted even when the TCn bit is...

Page 172: ... by setting the ENn bit of the corresponding channel to 1 This register can be read written in 8 bit or 1 bit units Figure 6 10 DMA Restart Register DRST 7 6 5 4 3 2 1 0 Address Initial value DDIS 0 0 0 0 CH3 CH2 CH1 CH0 FFFFF0F0H 00H Bit Position Bit Name Function 3 to 0 CH3 to CH0 Reflects the contents of the ENn bit of the DCHCn register during NMI input The contents of this register are held u...

Page 173: ...e as DMA transfer start factors These registers can be read written in 8 bit 1 bit units Figure 6 11 DMA Trigger Factor Registers 0 to 3 DTFR0 to DTFR3 1 3 7 6 5 4 3 2 1 0 Address Initial value DTFR0 0 0 IFC5 IFC4 IFC3 IFC2 IFC1 IFC0 FFFFF810H 00H 7 6 5 4 3 2 1 0 Address Initial value DTFR1 0 0 IFC5 IFC4 IFC3 IFC2 IFC1 IFC0 FFFFF812H 00H 7 6 5 4 3 2 1 0 Address Initial value DTFR2 0 0 IFC5 IFC4 IF...

Page 174: ...T 0 0 0 1 0 0 TINTCMD0 0 0 0 1 0 1 TINTCMD1 0 0 0 1 1 0 INTWTI 0 0 0 1 1 1 INT0 0 0 1 0 0 0 INT1 0 0 1 0 0 1 INT2 0 0 1 0 1 0 TINTOVE00 0 0 1 0 1 1 TINTOVE10 0 0 1 1 0 0 TINTCCE00 INTPE00 0 0 1 1 0 1 TINTCCE10 INTPE10 0 0 1 1 1 0 TINTCCE20 INTPE20 0 0 1 1 1 1 TINTCCE30 INTPE30 0 1 0 0 0 0 TINTCCE40 INTPE40 0 1 0 0 0 1 TINTCCE50 INTPE50 0 1 0 0 1 0 TINTOVE01 0 1 0 0 1 1 TINTOVE11 0 1 0 1 0 0 TINTCC...

Page 175: ...or IFC5 IFC4 IFC3 IFC2 IFC1 IFC0 Interrupt Source 0 1 1 1 0 1 TINTCCE12 INTPE12 0 1 1 1 1 0 TINTCCE22 INTPE22 0 1 1 1 1 1 TINTCCE32 INTPE32 1 0 0 0 0 0 TINTCCE42 INTPE42 1 0 0 0 0 1 TINTCCE52 INTPE52 1 0 0 0 1 0 INTAD 1 0 0 0 1 1 INTMAC 1 0 0 1 0 0 INTACT 1 0 0 1 0 1 CAN1REC 1 0 0 1 1 0 CAN1TRX 1 0 0 1 1 1 CAN1ERR 1 0 1 0 0 0 CAN2REC 1 0 1 0 0 1 CAN2TRX 1 0 1 0 1 0 CAN2ERR 1 0 1 0 1 1 CAN3REC 1 0 ...

Page 176: ...d After entering the last T2R state the bus invariably enters the T1W state 5 T2RI state State in which the bus is ready for DMA transfer to on chip peripheral I O or internal RAM state in which the bus mastership is acquired for DMA transfer to on chip peripheral I O or internal RAM After entering the last T2RI state the bus invariably enters the T1W state 6 T1W state The bus enters the T1W state...

Page 177: ...14913EE1V0UM00 6 4 2 DMAC bus cycle state transition Except for the block transfer mode each time the processing for a DMA transfer is completed the bus mastership is released Figure 6 12 DMAC Bus Cycle Two Cycle Transfer State Transition TI T0 T1R T2R T1W T2W TE TI T2RI ...

Page 178: ...n continues until a terminal count occurs When the DMAC has released the bus if another higher priority DMA transfer request is issued the higher priority DMA request always takes precedence 6 5 3 Block transfer mode In the block transfer mode once transfer starts the DMAC continues the transfer operation without releasing the bus until a terminal count occurs No other DMA requests are acknowledge...

Page 179: ...estination address of DMA transfer Be sure to specify an address between FFFF000H and FFFFFFFH 6 8 DMA Channel Priorities The DMA channel priorities are fixed as follows DMA channel 0 DMA channel 1 DMA channel 2 DMA channel 3 These priorities are valid in the TI state only In the block transfer mode the channel used for transfer is never switched In the single step transfer mode if a higher priori...

Page 180: ...e registers are automatically rewritten with the value that was set immediately before Therefore during DMA transfer transfer is automatically started when a new DMA transfer setting is made for these registers and the MLEn bit of the DCHCn register is set to 1 however the DMA transfer end interrupt may be issued even if DMA transfer is automatically started Figure 6 13 shows the configuration of ...

Page 181: ...rrupted by NMI input during DMA transfer At such a time the DMAC resets the ENn bit of the DCHCn register of all channels to 0 and the DMA transfer disabled state is entered An NMI request can then be acknowledged after the DMA transfer executed during NMI input is terminated n 0 to 3 In the single step transfer mode or block transfer mode the DMA transfer request is held in the DMAC If the ENn bi...

Page 182: ... register is invalid refer to 6 9 Next Address Setting Function and 6 3 4 DMA addressing control regis ters 0 to 3 DADC0 to DADC3 6 14 Precautions 1 Memory boundary The transfer operation is not guaranteed if the source or the destination address exceeds the area of DMA objects internal RAM or peripheral I O during DMA transfer 2 Transfer of misaligned data DMA transfer of 16 bit 32 bit bus width ...

Page 183: ...exception event i e fetching of an illegal opcode exception trap Eight levels of software programmable priorities can be specified for each interrupt request Interrupt servicing starts after no fewer than 11 system clocks 550 ns 20 MHz following the generation of an interrupt request 7 1 Features Interrupts Non maskable interrupts 2 sources Maskable interrupts 60 sources 8 levels of programmable p...

Page 184: ...terrupt INT0 PIC6 INT0 input Pin 6 00E0H 000000E0H nextPC Interrupt INT1 PIC7 INT1 input Pin 7 00F0H 000000F0H nextPC Interrupt INT2 PIC8 INT2 input Pin 8 0100H 00000100H nextPC Interrupt TINTOVE00 PIC9 Time base Overflow Timer E0 9 0110H 00000110H nextPC Interrupt TINTOVE10 PIC10 Time base Overflow Timer E0 10 0120H 00000120H nextPC Interrupt TINTCCE00 INTPE00 PIC11 CC coincidence Pin TimerE0 INT...

Page 185: ...002C0H nextPC Interrupt CAN1TRX PIC37 CAN1 transmit interrupt pending FCAN1 37 02D0H 000002D0H nextPC Interrupt CAN1ERR PIC38 CAN1 error interrupt pend ing FCAN1 38 02E0H 000002E0H nextPC Interrupt CAN2REC PIC39 CAN2 receive interrupt pending FCAN2 39 02F0H 000002F0H nextPC Interrupt CAN2TRX PIC40 CAN2 transmit interrupt pending FCAN2 40 0300H 00000300H nextPC Interrupt CAN2ERR PIC41 CAN2 error in...

Page 186: ... 03C0H 000003C0H nextPC Interrupt INTSER2 PIC53 UART2 reception error UART2 53 03D0H 000003D0H nextPC Interrupt INTSR2 PIC54 UART2 reception comple tion UART2 54 03E0H 000003E0H nextPC Interrupt INTST2 PIC55 UART2 transmission com pletion UART2 55 03F0H 000003F0H nextPC Interrupt INTDMA0 PIC56 DAM completed DMA0 56 0400H 00000400H nextPC Interrupt INTDMA1 PIC57 DMA completed DMA1 57 0410H 00000410...

Page 187: ...ced the service is executed as follows 1 If an NMIVC is generated while NMIVC is being serviced The new NMIVC request is held pending regardless of the value of the PSW NP bit The pending NMIVC request is acknowledged after servicing of the current NMIVC request has finished after execution of the RETI instruction 2 If an NMIWDT request is generated while NMIVC is being serviced If the PSW NP bit ...

Page 188: ...FECC of ECR 4 Sets the NP and ID bits of the PSW and clears the EP bit 5 Sets the handler address 00000010H corresponding to the non maskable interrupt to the PC and transfers control The processing configuration of a non maskable interrupt is shown in Figure 7 1 Figure 7 1 Processing Configuration of Non Maskable Interrupt Non maskable interrupt request FEPC Restored PC FEPSW PSW ECR FECC Excepti...

Page 189: ... NMIVC request is generated twice while an NMIVC service program is being exe cuted Main routine NMI request NMI request PSW NP 1 NMI request held pending because PSW NP 1 Pending NMI request processed Main routine NMI request NMI request Held pending because NMI service program is being processed Only one NMI request is acknowledged even though two NMI requests are generated NMI request Held pend...

Page 190: ...3EE1V0UM00 Figure 7 3 Example of Non Maskable Interrupt Request Acknowledgement Operation 1 2 c Multiple NMI requests generated at the same time NMIVC and NMIWD requests generated simultaneously NMIVC and NMIWD requests generated simultaneously Main routine NMIWD servicing System reset ...

Page 191: ...re NMIWD request NMIWD request generated during NMIVC servicing NP 0 set before NMIWD request NMIWD NMIVC request generated during NMIWD servicing NMIWD request generated during NMIWD servicing Main routine NMIVC request NMIVC request NMIVC servicing Held pending Servicing of pending NMIVC Main routine NMIWD request NMIVC request NMIWD servicing Invalid System reset Main routine NMIWD request NMIW...

Page 192: ...ess of the restored PC and PSW Figure 7 4 illustrates how the RETI instruction is processed Figure 7 4 RETI Instruction Processing Caution When the PSW EP bit and PSW NP bit are changed by the LDSR instruction during non maskable interrupt processing in order to restore the PC and PSW correctly dur ing recovery by the RETI instruction it is necessary to set PSW EP back to 0 and PSW NP back to 1 us...

Page 193: ...NMI interrupt has been acknowledged and masks all interrupt requests and exceptions to prohibit multiple interrupts from being acknowledged Figure 7 5 Non maskable Interrupt Status Flag NP 31 8 7 6 5 4 3 2 1 0 Initial value PSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NP EP ID SAT CY OV S Z 00000020H Bit Position Bit Name Function 7 NP Indicates whether NMI interrupt processing is in progre...

Page 194: ...age Comparator Mode Register VCMPM 7 6 5 4 3 2 1 0 Address R W Initial value VCMPM VCEN NSOCE EFBK 0 EDN1 EDN0 EDM1 EDM0 FFFFF860H R W 00H Bit position Bit Name Function 7 VCEN Enables the voltage comparator 6 NSOCE Specifies the NMI source 0 NMI pin 1 Comparator output 5 EFBK Enables comparator feedback 3 2 EDN1 EDN0 Specifies the NMI pin s valid edge EDN1 EDN0 Operation 0 0 No edge detection 0 1...

Page 195: ...rupts having a higher priority than the interrupt request in progress specified by the interrupt control register Note that only interrupts with a higher priority will have this capability interrupts with the same priority level cannot be nested However if multiple interrupts are executed the following processing is necessary 1 Save EIPC and EIPSW in memory or a general purpose register before exe...

Page 196: ...PSW ID 0 as set by the RETI and LDSR instructions input of the pending INT starts the new maskable interrupt processing INT input xxIF 1 No xxMK 0 No Is the interrupt mask released Yes Yes No No No Maskable interrupt request Interrupt request held pending PSW NP PSW ID 1 1 Interrupt request held pending 0 0 Interrupt processing CPU processing INTC accepted Yes Yes Yes Priority higher than that of ...

Page 197: ...s of the restored PC and PSW Figure 7 8 illustrates the processing of the RETI instruction Figure 7 8 RETI Instruction Processing Note For the ISPR register see 7 3 6 In service priority register ISPR Caution When the PSW EP bit and the PSW NP bit are changed by the LDSR instruction during maskable interrupt processing in order to restore the PC and PSW correctly during recovery by the RETI instru...

Page 198: ...register xxICn When two or more interrupts having the same prior ity level specified by the xxPRn bit are generated at the same time interrupts are serviced in order depending on the priority level allocated to each interrupt request type default priority level before hand For more information refer to Table 7 1 Interrupt Exception Source List Sheet 1 of 3 The programmable priority control customi...

Page 199: ...requests Main routine EI EI Interrupt request a level 3 Processing of a Processing of b Processing of c Interrupt request c level 3 Processing of d Processing of e EI Interrupt request e level 2 Processing of f EI Processing of g Interrupt request g level 1 Interrupt request h level 1 Processing of h Interrupt request b is acknowledged because the priority of b is higher than that of a and interru...

Page 200: ...Interrupt request p level 2 Interrupt request q level 1 Interrupt request r level 0 Interrupt request u level 2 Note 2 Interrupt request t level 2 Note 1 Processing of p Processing of q Processing of r EI If levels 3 to 0 are acknowledged Interrupt request j is held pending because its priority is lower than that of i k that occurs after j is acknowledged because it has the higher priority Interru...

Page 201: ...le interrupt servicing restore the values of EIPC and EIPSW after executing the DI instruction Default priority a b c Main routine EI Interrupt request a level 2 Interrupt request b level 1 Interrupt request c level 1 Processing of interrupt request b Processing of interrupt request c Processing of interrupt request a Interrupt request b and c are acknowledged first according to their priorities B...

Page 202: ...PICn PIFn PMKn 0 0 0 PPRn2 PPRn1 PPRn0 FFFFF110H to FFFF18EH 47H Bit Position Bit Name Function 7 PIFn This is an interrupt request flag 0 Interrupt request not issued 1 Interrupt request issued The flag xxIFn is reset automatically by the hardware if an interrupt request is acknowledged 6 PMKn This is an interrupt mask flag 0 Enables interrupt processing 1 Disables interrupt processing pending 2 ...

Page 203: ...PIF18 PMK18 0 0 0 PPR182 PPR181 PPR180 FFFFF136H PIC19 PIF19 PMK19 0 0 0 PPR192 PPR191 PPR190 FFFFF138H PIC20 PIF20 PMK20 0 0 0 PPR202 PPR201 PPR100 FFFFF13AH PIC21 PIF21 PMK21 0 0 0 PPR212 PPR11 PPR110 FFFFF13CH PIC22 PIF22 PMK22 0 0 0 PPR222 PPR221 PPR220 FFFFF13EH PIC23 PIF23 PMK23 0 0 0 PPR232 PPR231 PPR230 FFFFF140H PIC24 PIF24 PMK24 0 0 0 PPR242 PPR241 PPR240 FFFFF142H PIC25 PIF25 PMK25 0 0 ...

Page 204: ...IF48 PMK48 0 0 0 PPR482 PPR481 PPR480 FFFFF172H PIC49 PIF49 PMK49 0 0 0 PPR492 PPR491 PPR490 FFFFF174H PIC50 PIF50 PMK50 0 0 0 PPR502 PPR501 PPR500 FFFFF176H PIC51 PIF51 PMK51 0 0 0 PPR512 PPR511 PPR510 FFFFF178H PIC52 PIF52 PMK52 0 0 0 PPR522 PPR521 PPR520 FFFFF17AH PIC53 PIF53 PMK53 0 0 0 PPR532 PPR531 PPR530 FFFFF17CH PIC54 PIF54 PMK54 0 0 0 PPR542 PPR541 PPR540 FFFFF17EH PIC55 PIF55 PMK55 0 0 ...

Page 205: ...egisters 0 to 3 IMR0 to IMR3 Remark n peripheral unit number refer to Table 7 2 Addresses and Bits of Interrupt Control Regis ters Sheet 1 of 2 on page 203 15 14 13 12 11 10 9 8 Address Initial value IMR0 PMK15 PMK14 PMK13 PMK12 PMK11 PMK10 PMK9 PMK8 FFFFF100H FFFFH 7 6 5 4 3 2 1 0 PMK7 PMK6 PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 15 14 13 12 11 10 9 8 Address Initial value IMR1 PMK31 PMK30 PMK29 PMK28 PMK2...

Page 206: ...Figure 7 14 Maskable Interrupt Status Flag ID 7 6 5 4 3 2 1 0 Address Initial value ISPR ISPR7 ISPR6 ISPR5 ISPR4 ISPR3 ISPR2 ISPR1 ISPR0 FFFFF1FAH 00H Bit Position Bit Name Function 7 to 0 ISPR7 to ISPR0 Indicates priority of interrupt currently acknowledged 0 Interrupt request with priority n not acknowledged 1 Interrupt request with priority n acknowledged 31 8 7 6 5 4 3 2 1 0 Initial value PSW ...

Page 207: ...e selection Figure 7 15 Timer E Input Circuit Overview Remark m 0 to 5 Filter Clock Digital Filter Frequencies Clock 0 Clock 1 Clock 2 Input INTPEm0 Input INTPEm2 FSMP1 FSMP0 DFEN DFEN TMS1 TMS0 EDGEM1 EDGEM0 Analog Filter Analog Filter Digital Filter Digital Filter Edge Detection Edge Detection FSMP1 FSMP0 TMS1 TMS0 EDGEM1 EDGEM0 TINTCCEm0 from Timer E0 TINTCCEm2 from Timer E2 To Timer E0 TNIEm E...

Page 208: ...er output follows the filter input if this compare operation matches The delay stage is set to a fixed delay of 50 ns The tolerance of this delay is at about 70 This defines the filter frequency in a range from 12 MHz to 67 MHz An edge detection circuitry can detect rising falling or both edges selectable Filter Clock Digital Filter Frequencies Clock 0 Clock 1 Clock 2 Input INTPn FSMP1 FSMP0 DFEN ...

Page 209: ...e for its output that differs from the current output state 4 subsequent samples are required where each sample has read the same new input value However to accept an input sample to be relevant for the new value the level of the detection enable signal has to be high The detection enable signal is a divided clock derived from the system clock with frequencies fCPU fCPU 2 fCPU 4 To reject an input...

Page 210: ...MS1 TMS0 FFFFF880H 00H FEM01 DFEN 0 FSMP1 FSMP0 EDGEM1 EDGEM0 TMS1 TMS0 FFFFF890H 00H FEM02 DFEN 0 FSMP1 FSMP0 EDGEM1 EDGEM0 TMS1 TMS0 FFFFF8A0H 00H FEM10 DFEN 0 FSMP1 FSMP0 EDGEM1 EDGEM0 TMS1 TMS0 FFFFF881H 00H FEM11 DFEN 0 FSMP1 FSMP0 EDGEM1 EDGEM0 TMS1 TMS0 FFFFF891H 00H FEM12 DFEN 0 FSMP1 FSMP0 EDGEM1 EDGEM0 TMS1 TMS0 FFFFF8A1H 00H FEM20 DFEN 0 FSMP1 FSMP0 EDGEM1 EDGEM0 TMS1 TMS0 FFFFF882H 00H...

Page 211: ... Filter sampling rate Selects the sampling clock for the digital filter FSMP1 FSMP0 Sampling clock clock input 0 0 fCPU 1 0 1 fCPU 2 1 0 fCPU 4 1 1 reserved EDGEM1 EDGEM0 Edge selection for INTPEmn to interrupt controller Selects active edge for interrupt generation EDGEM1 EDGEM0 Edge selection 0 0 Internal interrupt source direct 0 1 Positive edge 1 0 Falling edge 1 1 Both edges Remark m 0 to 5 n...

Page 212: ...DGEM0 0 0 FFFFF8B0H 00H FEM13 DFEN1 0 FSMP1 FSMP0 EDGEM1 EDGEM0 0 0 FFFFF8B1H 00H FEM23 DFEN2 0 FSMP1 FSMP0 EDGEM1 EDGEM0 0 0 FFFFF8B2H 00H Bit Name Description DFEN Digital filter enable Selects analog or digital filter for interrupt input 0 Analog filter 1 Digital filter Note Refer to Figure 7 16 Port Interrupt Input Circuit Overview on page 208 FSMP1 FSMP0 Filter sampling rate Selects the sampl...

Page 213: ... ECR interrupt source 4 Sets the EP and ID bits of the PSW 5 Sets the handler address 00000040H or 00000050H corresponding to the software exception to the PC and transfers control Figure 7 20 illustrates the processing of a software exception Figure 7 20 Software Exception Processing Note TRAP Instruction Format TRAP vector the vector is a value from 0 to 1FH The handler address is determined by ...

Page 214: ...ntrol to the address of the restored PC and PSW Figure 7 21 illustrates the processing of the RETI instruction Figure 7 21 RETI Instruction Processing Caution When the PSW EP bit and the PSW NP bit are changed by the LDSR instruction during the software exception processing in order to restore the PC and PSW correctly dur ing recovery by the RETI instruction it is necessary to set PSW EP back to 1...

Page 215: ...te that exception processing is in progress It is set when an exception occurs Figure 7 22 Exception Status Flag EP 31 8 7 6 5 4 3 2 1 0 Initial value PSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NP EP ID SAT CY OV S Z 00000020H Bit Position Bit Name Function 6 EP Shows that exception processing is in progress 0 Exception processing not in progress 1 Exception processing in progress ...

Page 216: ...enerated when an instruction applicable to this illegal instruction is executed Remark Arbitrary 1 Operation If an exception trap occurs the CPU performs the following processing and transfers control to the handler routine 1 Saves the restored PC to DBPC 2 Saves the current PSW to DBPSW 3 Sets the NP EP and ID bits of the PSW 4 Sets the handler address 00000060H corresponding to the exception tra...

Page 217: ...uction the CPU carries out the following processing and controls the address of the restored PC 1 Loads the restored PC and PSW from DBPC and DBPSW 2 Transfers control to the address indicated by the restored PC and PSW Figure 7 24 illustrates the restore processing from an exception trap Figure 7 24 Restore Processing from Exception Trap DBRET instruction PC PSW DBPC DBPSW Jump to address of rest...

Page 218: ...is generated the CPU performs the following processing transfers control to the debug monitor routine and shifts to debug mode 1 Saves the restored PC to DBPC 2 Saves the current PSW to DBPSW 3 Sets the NP EP and ID bits of the PSW 4 Sets the handler address 00000060H corresponding to the debug trap to the PC and transfers control Figure 7 25 illustrates the processing of the debug trap Figure 7 2...

Page 219: ...truction the CPU carries out the following processing and controls the address of the restored PC 1 Loads the restored PC and PSW from DBPC and DBPSW 2 Transfers control to the address indicated by the restored PC and PSW Figure 7 26 illustrates the restore processing from a debug trap Figure 7 26 Restore Processing from Debug Trap DBRET instruction PC PSW DBPC DBPSW Jump to address of restored PC...

Page 220: ...ocessing control is executed when an interrupt has an enable status ID 0 Thus if multiple interrupts are executed it is necessary to have an interrupt enable status ID 0 even for an interrupt processing routine If a maskable interrupt enable or a software exception is generated in a maskable interrupt or software exception service program it is necessary to save EIPC and EIPSW This is accomplished...

Page 221: ... PPRn0 to PPRn2 bits The priority order of maskable interrupts is as follows High Level 0 Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Low Interrupt processing that has been suspended as a result of multiple processing control is resumed after the processing of the higher priority interrupt has been completed and the RETI instruction has been executed A pending interrupt request is ackn...

Page 222: ...errupt Response Time Interrupt Response Time Internal System Clocks Condition Internal Interrupt External interrupt INTP0 to INTP2 INTPE00 to INTPE52 Minimum 5 5 analog delay time 5 digital noise filter The following cases are excep tions In IDLE software STOP mode External bit access Two or more interrupt request non sample instructions are executed Access to interrupt con trol register Maximum 1...

Page 223: ...nstruction is being executed However no interrupt will be acknowledged between an interrupt non sample instruction and the next instruction The interrupt request non sampling instructions are as follows EI instruction DI instruction LDSR reg2 0x5 instruction for PSW The store instruction for the interrupt control register PlCn in service priority register ISPR and command register PRCMD ...

Page 224: ...224 Preliminary User s Manual U14913EE1V0UM00 MEMO ...

Page 225: ...onfiguration Figure 8 1 Block Diagram of the Clock Generator This block diagram does not necessarily show the exact wiring in hardware but the functional structure For example the CLKSEL pin is not connected to the CVDD of the PLL block but the function is as if OSC x1 x2 PLL circuit x 4 selector selector CVDD CVDD selector 1 23 27 1 22 1 Watch Timer Asynchronous Ripple Counters Prescaler Watchdog...

Page 226: ...nary User s Manual U14913EE1V0UM00 8 3 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or ceramic resonator connected to the X1 and X2 pins Figure 8 2 Main system clock oscillator X2 X1 IC ...

Page 227: ...bled when 1 is written to this bit Passing stabilization time and synchro nization stage PLL output is used for system clock CESEL Clock selection bit X1 X2 pin function This bit sets PLL for proper operation with resonator or external oscillator 0 Oscillation is enabled for a resonator 1 Oscillation is disabledNote Note If direct mode is selected by CLKSEL pin 1 CESEL must be set to 1 by software...

Page 228: ... is selected by specifying the CLKSEL pin Table 8 1 PLL mode direct mode Note If direct mode is selected by CLKSEL pin 1 CESEL must be set to 1 by software after reset The CLKSEL pin level should be fixed according to the application system Switching this pin during operation may cause malfunction In OSC mode the external signal supplied by a connected resonator is used to generate the system cloc...

Page 229: ...ication systems that do not require very high frequency operation To reduce noise most efficiently the frequency of the externally supplied clock by CLKIN pin is recommended to be set to 40 MHz when system clock fCPU 20 MHz 2 Available configurations Table 8 3 CESEL setting Note If direct mode is selected by CLKSEL pin 1 CESEL must be set to 1 by software after reset System clock frequency fCPU PL...

Page 230: ...n the comparator circuit needs to be switched off in watch mode and STOP mode to save power consumption 4 The LCD driver probably have to be switched off in watch mode and or in low voltage mode to meet the power consumption requirements Note Only for flash devices in IDLE mode flash memory is active in watch mode the power supply to the flash memory is switched off Clock Source Mode Operation of ...

Page 231: ...h off PLL if activated before 2 Enable PLL if required The following table shows the supplied operating frequencies of all macros if a 4 MHz crystal is applied to the oscillator circuit or an external clock signal with 16 MHz is applied to the CLOCKIN pin Normal operation mode Software STOP mode Set STOP mode IDLE mode Set IDLE mode Release by RESET NMI or maskable interrupt Set HALT mode NMI or m...

Page 232: ...ce Mode Operation of Clock Supply to oscillator PLL peripherals CPU LCD prescaler watch watch dog prescaler OSC mode Initial Status Normal 4 MHz 4 MHz 4 MHz 27 4 MHz 27 29 PLL enabled Normal 16 MHz 16 MHz 4 MHz 27 4 MHz 27 29 watch mode IDLENote1 4 MHz 27 4 MHz 27 29 HALT 16 MHz 4 MHz 27 4 MHz 27 29 STOP Direct mode Normal 16 MHz 16 MHz 32 MHz 210 32 MHz 210 212 watch mode IDLENote1 32 MHz 210 32 ...

Page 233: ...rmal operating mode quickly in response to a release signal This mode provides low power consumption where the power is only consumed from the OSC Watch Watchdog LCD and the flash memory This mode is entered by setting registers with software 3 WATCH mode In this mode the clock generator stop to supply the clock excluding Watch Watchdog timer unit The entire system stops This mode provides ultra l...

Page 234: ...n also continues to operate The state of the various hardware units in the HALT mode is tabulated below Table 8 6 Operating states in HALT mode Remark Even after the HALT instruction is executed instruction fetch operations continue until the internal instruction prefetch queue is full After the queue becomes full the CPU stops with the items set as tabulated above Items Operation Clock generator ...

Page 235: ...pt is not acknowledged The interrupt request itself is retained b If an interrupt request including a non maskable one prioritized than the currently serviced interrupt request is generated the interrupt request is acknowledged along with the HALT mode release Table 8 7 Operation after HALT mode release by interrupt request Remark If HALT mode is entered during execution of a particular interrupt ...

Page 236: ... the IDLE mode is tabulated below Table 8 8 Operating States in IDLE Mode IDLE mode release Release operation is same as release from HALT mode The IDLE mode is released by NMI RESET signal input or an unmasked maskable interrupt request a Release by Interrupt input When the IDLE mode is released the NMI request is acknowledged If the IDLE mode is entered during the execution of NMI handler the ID...

Page 237: ...RESET signal input 1 Release by interrupt request The WATCH mode is released unconditionally by an unmasked maskable interrupt request regard less of its priority level After 1 ms has passed CPU starts operation However if the WATCH mode is entered during execution of an interrupt handler the operation differs on interrupt priority levels as follows a If an interrupt request less priorities than t...

Page 238: ...ms has passed CPU starts operation Remark Before entering the WATCH mode the PLL must be switched off by software After the WATCH mode has been released the PLL can be switched on again However the start up of the PLL causes always a certain delay of some Milliseconds During this time the clock operates but the CPU operation is suspended due to clock security reasons If it is required to have a fa...

Page 239: ...n stops but the contents of all registers and internal RAM prior to entering this mode are retained V850E CA1 ATOMIC peripherals operations are also stopped The state of the various hardware units in the software STOP mode is tabulated below Table 8 11 Operating States in STOP Mode Note When the VDD value is within the operating range However even if VDD falls below the lowest operating voltage th...

Page 240: ...is register can be read or written in 8 or 1 bit units Note If this bit is set to 1 proper operation can not be guaranteed 7 6 5 4 3 2 1 0 Address R W At Reset PSC 0Note NMI1M NMI0M INTM 0 0 STB 0 FFFFF1FEH R W 00H Bit name Function STB Power save mode specification 0 IDLE WATCH STOP mode are released 1 IDLE WATCH STOP mode are entered INTM Intsignal release mask 0 Release by maskable interrupt 1 ...

Page 241: ...on routine after software STOP mode and IDLE mode release No special sequence is required to read the specific register Cautions 1 A store instruction for the command register does not accept interrupts This cod ing is made on assumption that 3 and 4 above are executed by the program with consecutive store instructions If another instruction is set between 3 and 4 the above sequence may become ine...

Page 242: ... 8 or 1 bit units The contents of this register can be read in the normal sequence 7 6 5 4 3 2 1 0 Address R W At Reset PSM 0 0 0 0 0 0 PSM1 PSM0 FFFFF820H R W 00H Bit name Function PSM1 PSM0 Standby mode specification after STB bit PSC 1 set to 1 Sets the standby mode PSM1 PSM0 Standby Mode 0 0 IDLE 0 1 STOP 1 0 WATCH 1 1 reserved Note The setting is automatically reset to 00 when STOP mode is re...

Page 243: ...nput to the NMI pin or a maskable interrupt request is input INTPn Valid edge input to the pin causes the time base coun ter TBC to start counting and the time until the clock output from the oscillator stabilizes is secured during that counting time Oscillation stabilization time TBC counting time After a fixed time internal system clock output begins and processing branches to the NMI inter rupt...

Page 244: ...ut or maskable interrupt request input INTPn timing in which STOP mode is set until the CPU acknowledges the interrupt If direct mode CESEL bit of CKC register 1 is used stabilization stage will be skipped If PLL mode and resonator connection mode CESEL bit of CKC register 0 are used program execution begins after the oscillation stabilization time or the flash stabilization time is secured accord...

Page 245: ...ns after a rising edge is input to the RESET pin and processing branches to the handler address used for a system reset Figure 8 6 WATCH mode release by reset or watchdog timer Figure 8 7 STOP mode release by RESET pin input Watch mode setting Oscillation circuit System clock Watch state Watch clock working RESET signal Internal system reset signal Flash stabilization time secured by RESET or NMIW...

Page 246: ...e STOP mode is released It also is used to secure the flash stabilization time when software WATCH mode is released The TBC count clock is selected according to the TBCS bit of the CKC register and the next counting time can be set reference Table 8 12 Counting Time Examples Remark fxx External oscillation frequency TBCS Bit Counting Time fXX 4 0000 MHz fXX 5 0000 MHz 0 12 5 ms 10 0 ms 1 25 0 ms 2...

Page 247: ...system clock maximum frequency of count clock 10 MHz fCPU 20 MHz Prescaler division ratio The following division ratios can be selected related to the internal system clock fCPU Interrupt request sources 2 Compare match interrupt TINTCMDn generated with CMDn match signal Timer clear TMDn register can be cleared by CMDn register match Remarks 1 fCPU Internal system clock 2 n 0 1 Division Ratio Coun...

Page 248: ...m of the channel of timer D Figure 9 1 Block Diagram of Timer D Remark n 0 1 Timer Count Clock Register R W Generated Interrupt Signal Capture Trigger Timer Output S R Other Functions Timer D fCPU 2 fCPU 4 fCPU 8 fCPU 16 fCPU 32 fCPU 64 fCPU 128 fCPU 256 TMD0 R CMD0 R W TINTCMD0 TMCD0 R W TMD1 R CMD1 R W TINTCMD1 TMCD1 R W TMDn 16 bit CMDn TINTCMDn 1 2 1 4 1 8 1 16 1 32 1 64 1 128 1 256 Clear star...

Page 249: ...ed asynchro nously 2 If the CE bit of the TMCDn register is cleared 0 a reset is performed synchro nized with the internal clock Similarly a synchronized reset is performed after a match with the CMDn register and after an overflow 3 The count clock must not be changed during a timer operation If it is to be over written it should be overwritten after the CE bit is cleared 0 4 Up to fCPU 2 clocks ...

Page 250: ...e master side is read out CMDn can be read written in 16 bit units Figure 9 3 Timer D Compare Registers 0 1 CMD0 to CMD1 Cautions 1 A write operation to the a CMDn register requires fCPU 2 clocks until the value that was set in the CMDn register is transferred to internal units When writing continu ously to the CMDn register be sure to reserve a time interval of at least fCPU 2 clocks 2 The CMDn r...

Page 251: ...er s Manual U14913EE1V0UM00 Figure 9 4 Example of Timing During TMD Operation a When TMDn CMDn b When TMDn CMDn Remarks 1 p TMDn value when overwritten 2 q CMDn value when overwritten 3 n 0 1 TMDn CAE CE CMDn TINTCMDn q p q q TMDn CAE CE CMDn INTCMDn m FFFFH n n n ...

Page 252: ...8 1 1 1 fCPU 256 Caution Do not change the CS2 to CS0 bits during timer operation If they are to be changed they must be changed after setting the CE bit to 0 If the CS2 to CS0 bits are overwritten during timer operation the operation is not guaranteed 1 CE Count Enable Controls the operation of TMDn n 0 1 0 Disable count timer stopped at 0000H and does not operate 1 Perform count operation Cautio...

Page 253: ... If a match is detected by the compare operation an interrupt TINTCMDn is generated The gener ation of the interrupt causes TMDn to be cleared 0 at the next count timing This function enables timer D to be used as an interval timer CMDn can also be set to 0 In this case when an overflow occurs and TMDn becomes 0 a match is detected and TINTCMDn is generated Although the TMDn value is cleared 0 at ...

Page 254: ...n is set to m non zero Remarks 1 Interval time m 1 Count clock cycle 2 m 1 to 65536 FFFFH 3 n 0 1 b When CMDn is set to 0 Remark Interval time FFFFH 2 Count clock cycle 1 TMDn Count clock 0 m CMDn m TMDn clear Match detected TINTCMDn Count up Clear 1 0 0 0 FFFFH Overflow TMDn Count clock CMDn TMDn clear Match detected TINTCMDn Count up Clear ...

Page 255: ... count operation begins the count cycle from 0000H to 0001H differs from subsequent count cycles 3 To initialize the TMDn register status and start counting again clear 0 the CE bit and then set 1 the CE bit after an interval of fCPU 2 clocks has elapsed 4 Up to fCPU 2 clocks are required until the value that was set in the CMDn register is transferred to internal units When writing continuously t...

Page 256: ...omparison with sub channel n capture compare register and generate the TINTCCExn interrupt upon compare match Timer counter overflow interrupt requests 2 types The TINTOVE0n TINTOVE1n interrupt is generated when the count value of TBASE0n TBASE1n becomes FFFFH Capture request Count values of TBASE0n TBASE1n can be latched using external pin INTPExn Note 1 Note 2 PWM output function Control of the ...

Page 257: ...FEMn5 Notes 1 For the registers used to specify the valid edge for external interrupt requests INTPE0n through INTPE5n to timer E refer to the chapter Timer E input filter mode registers 0 to 5 FEM0n to FEM5n 2 The pairs TIEn and INTPE0n TOE1n and INTPE1n TOE2n and INTPE2n TOE3n and INTPE3n TOE4n and INTPE4n TCLREn and INTPE5n are each alternate function pins 3 The count enable operation for the t...

Page 258: ... to 4 n 0 to 2 Timer Count Clock Register R W Generated Interrupt Signal Capture Trigger Timer Output Note 1 S R Other Functions Timer En fCPU 2 fCPU 4 fCPU 8 fCPU 16 fCPU 32 fCPU 64 fCPU 128 TIEn pin TBASE0n TINTOVE0n Note 2 Note 3 TBASE1n TINTOVE1n Note 2 Note 3 CVSE0n R W TINTCCE0n INTPE0n INTPE5n CVSE1n R W INTPE1n INTPE4n TOE1nNote 4 TOE4nNote 4 BufferNote 5 CVSE2n R W INTPE2n INTPE3n TOE2nNo...

Page 259: ... ECLR CT CTC CASC ED2 Sub channel 4 Sub channel 3 Sub channel 2 Sub channel 1 CVSE4n 16 bit CVPE4n 16 bit S T RA RB RN Output circuit 4 Sub channel 0 CVSE0n 16 bit TBASE0n 16 bit TINTCCE0n TINTCCE1n TINTCCE2n TINTCCE3n TINTCCE4n TINTCCE5n TINTOVE0n TOE1n TOE2n TOE3n TOE4n TINTOVE1n Sub channel 5 CVSE5n 16 bit TBASE1n 16 bit TNIE5 edge selection TNIE4 edge selection TNIE3 edge selection TNIE2 edge ...

Page 260: ...ut of timer generated when TBASE0n TBASE1n 0000H CT TBASE0n TBASE1n count signal input in 16 bit mode CTC TBASE1n count signal input in 32 bit mode ECLR External control signal input from TCLREn input ED1 ED2 Capture event signal input from edge selection circuit RNote 2 Compare match signal input sub channel 0 5 RA TBASE0n zero count signal input reset signal of output circuit RB TBASE1n zero cou...

Page 261: ...count operation enable disable can be controlled with external pin TCLREn Counter up down and clear operation control method can be set by software Stop upon occurrence of count value 0 and count operation start stop can be controlled by software Figure 9 8 Timer E Time Base Counter 0 Registers 0 to 2 TBASE00 to TBASE02 Figure 9 9 Timer E Time Base Counter 1 Registers 0 to 2 TBASE10 to TBASE12 15 ...

Page 262: ...compare register of timer TMEn n 0 to 2 In the capture register mode it captures the TBASE0n count value In the compare register mode it detects match with TBASE0n This register can be read written in 16 bit units Figure 9 10 Timer E Sub Channel 0 Capture Compare Registers 0 to 2 CVSE00 to 02 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value CVSE00 FFFFF660H 0000H CVSE01 FFFFF6A0H 0000H ...

Page 263: ...s This register is read only in 16 bit units In compare mode this register represents the actual compare value To write a compare value the registers CVSExn have to be used This double register structure refers to the buffered operations in compare mode Figure 9 11 Timer E Sub Channel x Main Capture Compare Registers 0 to 2 CVPEx0 to CVPEx2 x 1 to 4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address In...

Page 264: ...r 16 bits The CVSExn register can be written only in the compare register mode If this register is written in the capture register mode the contents written to CVSExn register will be lost This register can be read written in 16 bit units Figure 9 12 Timer E Sub Channel x Sub Capture Compare Registers 0 to 2 CVSEx0 to CVSEx2 x 1 to 4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value CVSE...

Page 265: ...compare register of timer TMEn n 0 to 2 In the capture register mode it captures the count value of TBASE1n In the compare register mode it detects match with TBASE1n This register can be read written in 16 bit units Figure 9 13 Timer E Sub Channel 5 Capture Compare Registers CVSE50 to CVSE52 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value CVSE50 FFFFF662H 0000H CVSE51 FFFFF6A2H 0000H ...

Page 266: ...autions 1 Initialize TMEn when the STFTEn bit is cleared 0 TMEn cannot be initialized when the STFTEn bit is set 1 2 If the STFTEn bit is set 1 after initialization the initialized state is maintained Remark n 0 to 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value STOPTE0 STFTE0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FFFFF640H 0000H STOPTE1 STFTE1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FFFFF680H 0000H S...

Page 267: ...CSE00 FFFFF682H 0000H CSE2 0 0 0 0 TES1E1 TES1E0 TES0E1 TES0E0 CESE1 CESE0 CSE12 CSE11 CSE10 CSE02 CSE01 CSE00 FFFFF6C2H 0000H Bit Position Bit Name Function 11 10 9 8 TESyE1 TESyE0 Specifies the valid edge of the corresponding timer base counter TBASEyn count clock signal TCOUNTEy TESyE1 TESyE0 Valid Edge 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges 7 ...

Page 268: ...5 n 0 to 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value SESE0 0 0 0 0 IESE51 IESE50 IESE41 IESE40 IESE31 IESE30 IESE21 IESE20 IESE11 IESE10 IESE01 IESE00 FFFFF644H 0000H SESE1 0 0 0 0 IESE51 IESE50 IESE41 IESE40 IESE31 IESE30 IESE21 IESE20 IESE11 IESE10 IESE01 IESE00 FFFFF684H 0000H SESE2 0 0 0 0 IESE51 IESE50 IESE41 IESE40 IESE31 IESE30 IESE21 IESE20 IESE11 IESE10 IESE01 IESE00 FFF...

Page 269: ... capture register mode can be used for the capture compare register Caution In the 32 bit cascade operation mode CASE1 bit 1 only the 32 bit capture function is permitted set TB1Ex and TB0Ex bits of the CMSEmn registers to 11B m 12 34 x when m 12 x 1 2 and when m 34 x 3 4 14 6 CLREy Specifies software clear for TBASEyn 0 Continue TBASEyn operation 1 Clear 0 TBASEyn count value Cautions 1 Setting t...

Page 270: ...Eyn count operation enable disable through ECLR signal input 0 Don t enable TBASEyn count operation 1 Enable TBASEyn count operation Cautions 1 In the 32 bit cascade operation mode CASE1 bit 1 control of the TBASEyn count operation using ECLR signal input is not enabled 2 When the ECEEy bit 1 always set the CESE1 and CESE0 bits of the CSEn register to 10B through input 10 2 OSTEy Specifies stop mo...

Page 271: ...en ALVEx 1 fix output level to high level 14 10 6 2 ALVEx Specifies the active level of the TOExn pin output 0 Active level is high level 1 Active level is low level 13 12 9 8 5 4 1 0 OTMEx1 OTMEx0 Specifies toggle mode OTMEx1 OTMEx0 Toggle Mode 0 0 Toggle mode 0 Reverse output level of TOExn output every time a sub channel x compare match occurs 0 1 Toggle mode 1 Upon sub channel x compare match ...

Page 272: ... 0000H CMSE052 0 0 EEVE5 0 LNKE5 CCSE5 0 0 0 0 EEVE0 0 LNKE0 CCSE0 0 0 FFFFF6CAH 0000H Bit Position Bit Name Function 13 5 EEVEx Enables disables capture event detection by sub channel x capture compare register 0 Don t detect events 1 Detect events 11 3 LNKEx Specifies capture event signal input from edge selection to ED1 or ED2 of timer TMEn sub channel x 0 In capture register mode select ED1 si...

Page 273: ...ompare register CVSExn as buffer 1 Use sub channel x sub capture compare register CVSExn as buffer Remarks 1 The operations in the capture register mode and compare register mode when the sub channel x sub capture compare register CVSExn is not used as a buffer are shown below BFEEx 0 In capture register mode The CPU can read both the master register CVPExn and slave register CVSExn The next event...

Page 274: ...ch 1 Select ED2 signal input in capture register mode In the compare register mode the data of the CVSExn register is transferred to the CVPExn register when the TBASE0n TBASE1nNote count value becomes zero Note TBASE0n TBASE1n time base counter specified by the corresponding TB1Ex TB0Ex bits 10 2 CCSEx Selects capture compare register operation mode 0 Capture register mode 1 Compare register mode...

Page 275: ...compare register CVSExn as buffer 1 Use sub channel x sub capture compare register CVSExn as buffer Remarks 1 The operations in the capture register mode and compare register mode when the sub channel x sub capture compare register CVSExn is not used as a buffer are shown below BFEEx 0 In capture register mode The CPU can read both the master register CVPExn and slave register CVSExn The next even...

Page 276: ...ch 1 Select ED2 signal input in capture register mode In the compare register mode the data of the CVSExn register is transferred to the CVPExn register when the TBASE0n TBASE1nNote count value becomes zero Note TBASE0n TBASE1n time base counter specified by the corresponding TB1Ex TB0Ex bits 10 2 CCSEx Selects capture compare register operation mode 0 Capture register mode 1 Compare register mode...

Page 277: ...12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value TBSTATE0 0 0 0 0 OVFE1 ECFE1 RSFE1 UDFE1 0 0 0 0 OVFE0 ECFE0 RSFE0 UDFE0 FFFFF664H 0000H TBSTATE1 0 0 0 0 OVFE1 ECFE1 RSFE1 UDFE1 0 0 0 0 OVFE0 ECFE0 RSFE0 UDFE0 FFFFF6A4H 0000H TBSTATE2 0 0 0 0 OVFE1 ECFE1 RSFE1 UDFE1 0 0 0 0 OVFE0 ECFE0 RSFE0 UDFE0 FFFFF6E4H 0000H Bit Position Bit Name Function 11 3 OVFEy Indicates TBASEyn overflow status 0 No o...

Page 278: ...tion Bit Name Function 14 10 6 2 CEFEx Indicates the capture compare event occurrence status 0 In capture register mode No capture operation has occurred In compare register mode No compare match has occurred 1 In capture register mode At least one capture operation has occurred In compare register mode At least one compare match has occurred Caution The CEFEx bit can be cleared 0 by performing wr...

Page 279: ...00H ODELE1 0 ODLE42 ODLE41 ODLE40 0 ODLE32 ODLE31 ODLE30 0 ODLE22 ODLE21 ODLE20 0 ODLE12 ODLE11 ODLE10 FFFFF6A8H 0000H ODELE2 0 ODLE42 ODLE41 ODLE40 0 ODLE32 ODLE31 ODLE30 0 ODLE22 ODLE21 ODLE20 0 ODLE12 ODLE11 ODLE10 FFFFF6E8H 0000H Bit Position Bit Name Function 14 to 12 10 to 8 6 to 4 2 to 0 ODLEx2 ODLEx1 ODLEx0 Specifies output delay operation of TOExn ODLEx2 ODLEx1 ODLEx0 Set Output Delay Ope...

Page 280: ...LNKEx bits of the CMSEmn register 2 The SEVEx bit is automatically cleared 0 at the end of an event Remark x 0 to 5 n 0 to 2 m 12 34 05 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value CSCE0 0 0 0 0 0 0 0 0 0 0 SEVE5 SEVE4 SEVE3 SEVE2 SEVE1 SEVE0 FFFFF66AH 0000H CSCE1 0 0 0 0 0 0 0 0 0 0 SEVE5 SEVE4 SEVE3 SEVE2 SEVE1 SEVE0 FFFFF6AAH 0000H CSCE2 0 0 0 0 0 0 0 0 0 0 SEVE5 SEVE4 SEVE3 SEVE...

Page 281: ... the SESEn register are shown Remarks 1 fCLK fCPU Base clock 2 CT TBASEyn count signal input in the 16 bit mode ECLR External control signal input from TCLREn pin input ED1 ED2 Capture event signal input from edge selection circuit MUXTB0 TBASE0n multiplex signal TCOUNTEy Timer En count enable signal input of time base TBASEyn TIEx Timer En sub channel x capture event signal pin input TCLREn Timer...

Page 282: ...it 0 ECREy Bit 0 CLREy Bit 0 CASE1 Bit 0 Notes 1 Bits OSTEy CEEy of TCREn register 2 Controls TBASE0n TBASE1n clear by sub channel 0 5 compare match or count direction Remarks 1 fCLK fCPU Base clock 2 CNT Count value of time base TBASEyn CT TBASEyn count signal input in the 16 bit mode R Compare match signal input sub channel 0 5 3 y 0 1 n 0 to 2 fCLK FFFDH Stop FFFEH FFFFH 0000H 1234H 1235H 0000H...

Page 283: ... UDSEy0 Bits 00B OSTEy Bit 0 CEEy Bit 1 CASE1 Bit 0 Note Bits ECEEy ECREy CLREy of TCREn register Remarks 1 fCLK fCPU Base clock 2 CNT Count value of time base TBASEyn CT TBASEyn count signal input in the 16 bit mode ECLR External control signal input from TCLREn pin input 3 y 0 1 n 0 to 2 fCLK ECREyNote CLREyNote ECLR CNT CT ECEEyNote 1234H 1235H 0000H 0001H 0000H ...

Page 284: ...ister 2 Controls TBASE0n TBASE1n clear by sub channel 0 5 compare match or count direction Remarks 1 fCLK fCPU Base clock 2 CNT Count value of time base TBASEyn CT TBASEyn count signal input in 16 bit mode ECLR External control signal input from TCLREn pin input R Compare match signal input sub channel 0 5 3 y 0 1 n 0 to 2 fCLK ECLR RNote 2 CNT TINTOVEyn output CNT 0 CT UDSEy1 UDSEy0Note 1 FFFFH 0...

Page 285: ... Bit 1 CASE1 Bit 1 Note If in the 32 bit mode CASC CNT MAX for TBASE0n is input to TBASE1n and the CTC ris ing edge is detected TBASE1n performs count operation Remarks 1 fCLK fCPU Base clock 2 CASC TBASE1n count signal input in 32 bit mode CNT TBy Count value of time base TBASEyn CTC TBASE1n count signal input in 32 bit mode 3 y 0 1 n 0 to 2 fCLK CNT TB0 CNT TB1 CTC CASCNote FFFBH FFFCH FFFDH FFF...

Page 286: ...at the rising edge of MUXTB1 Figure 9 31 shows the block diagram of the timer TMEn multiplex count generation circuit and Fig ure 9 32 shows the multiplex count timing Figures 9 33 to 9 38 show the operation of the capture compare register sub channels 1 to 4 Figure 9 31 Block Diagram of Timer E Multiplex Count Generation Circuit Remarks 1 fCLK fCPU Base clock 2 CNT Count value of time base TBASE0...

Page 287: ...e TBASE1n MUXTB0 Multiplex signal of TBASE0n MUXTB1 Multiplex signal of TBASE1n MUXCNT Count value to sub channel x TB0 TB1 Time base TBASE0n TBASE1n 3 x 1 to 4 n 0 to 2 fCLK MUXTB0 MUXTB1 MUXCNT CNT TB0 CNT TB1 FFFEH FFFFH 0000H 1235H 1234H TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 0001H FFFEH 1234H FFFFH FFFFH FFFFH 1234H 1234H 0000H 1234H 1235H 0000H 1235H ...

Page 288: ... capture register CAPTURE_S Capture trigger signal of sub capture register ED1 ED2 Capture event signal input from edge selection circuit MUXCNT Count value to sub channel x MUXTB0 Multiplex signal of TBASE0n MUXTB1 Multiplex signal of TBASE1n READ_ENABLE_P Read timing for CVPExn register TB0 TB1 Time base TBASE0n TBASE1n 3 x 1 to 4 m 12 when x 1 or 2 m 34 when x 3 or 4 n 0 to 2 CVPExn register fC...

Page 289: ...er to the CVPExn register is enabled Remarks 1 fCLK fCPU Base clock 2 BUFFER Timing of write operation from CVSExn register to CVPExn register CAPTURE_P Capture trigger signal of main capture register CAPTURE_S Capture trigger signal of sub capture register ED1 Capture event signal input from edge selection circuit MUXCNT Count value to sub channel x MUXTB0 Multiplex signal of TBASE0n MUXTB1 Multi...

Page 290: ...e of time baser TBASE0n CNT TB1 Count value of time baser TBASE1n ED1 Capture event signal input from edge selection circuit MUXCNT Count value to sub channel x MUXTB0 Multiplex signal of TBASE0n MUXTB1 Multiplex signal of TBASE1n READ_ENABLE_P Read timing of CVPExn register TB0 TB1 Time base TBASE0n TBASE1n TCOUNTE0 Timer TMEn count enable signal input of time base TBASE0n TCOUNTE1 Timer TMEn cou...

Page 291: ...n capture register CAPTURE_S Capture trigger signal of sub capture register ED1 Capture event signal input from edge selection circuit MUXCNT Count value to sub channel x MUXTB0 Multiplex signal of TBASE0n MUXTB1 Multiplex signal of TBASE1n TB0 TB1 Time base TBASE0n TBASE1n 3 x 1 to 4 m 12 when x 1 or 2 m 34 when x 3 or 4 n 0 to 2 fCLK EEVExNote 1 SEVExNote 2 MUXTB0 MUXTB1 MUXCNT ED1 CAPTURE_P CAP...

Page 292: ... Base clock 2 MUXCNT Count value to sub channel x MUXTB0 Multiplex signal of TBASE0n MUXTB1 Multiplex signal of TBASE1n RELOAD1 Compare match signal RELOAD_PRIMARY Timing of write operation from CVSExn register to CVPExn register WRITE_ENABLE_S Timing of CVSExn register write operation TB0 TB1 Time base TBASE0n TBASE1n 3 x 1 to 4 m 12 when x 1 or 2 m 34 when x 3 or 4 n 0 to 2 fCLK TB0ExNote 1 TB1E...

Page 293: ... of TBASE1n RELOAD1 Compare match signal RELOAD2A Zero count signal input of TBASE0n occurs when TBASE0n 0000H RELOAD_PRIMARY Timing of write operation from CVSExn register to CVPExn register WRITE_ENABLE_S Timing of CVSExn register write operation TB0 TB1 Time base TBASE0n TBASE1n 3 x 1 to 4 m 12 when x 1 or 2 m 34 when x 3 or 4 n 0 to 2 fCLK LNKExNote WRITE_ENABLE_S MUXTB0 MUXTB1 MUXCNT RELOAD2A...

Page 294: ...0 EEVEx Bit 1 and CSCEn Register s SEVEx Bit 0 Notes 1 LNKEx bit of CMSE05n register 2 If an event occurs in this timing it is ignored Remarks 1 fCLK fCPU Base clock 2 CNT Count value of time base TBASEyn CAPTURE_S Capture trigger signal of sub capture register ED1 ED2 Capture event signal inputs from edge selection circuit READ_ENABLE_S Read timing for CVSExn register 3 x 0 5 y 0 when x 0 y 1 whe...

Page 295: ...otes 1 Controls TBASEyn clear by sub channel x compare match and count direction 2 MATCH is forwarded to the R input of the timebase s 3 The pulse width is always 1 clock Remarks 1 fCLK fCPU Base clock 2 CNT Count value of time base TBASEyn MATCH CVSExn register compare match timing R Compare match input sub channel x 3 x 0 5 y 0 when x 0 y 1 when x 5 n 0 to 2 fCLK CVSExn register MATCH RNote 1 CN...

Page 296: ... s ODLEx2 to ODLEx0 Bits 0 Note ALVEx OTMEx1 OTMEx0 bits of OCTLEn register Remarks 1 fCLK fCPU Base clock 2 RA Zero count signal input of TBASE0n output circuit reset signal RB Zero count signal input of TBASE1n output circuit reset signal RN Interrupt signal input of sub channel x output circuit reset signal S T Interrupt signal input of sub channel x output circuit set signal 3 x 1 to 4 n 0 to ...

Page 297: ...OTMEx0 bits of OCTLEn register Remarks 1 fCLK fCPU Base clock 2 RA Zero count signal input of TBASE0n output circuit reset signal RB Zero count signal input of TBASE1n output circuit reset signal RN Interrupt signal input of sub channel x output circuit reset signal S T Interrupt signal input of sub channel x output circuit set signal 3 x 1 to 4 n 0 to 2 fCLK RA RB RN TOExn timer output ALVEx 0Not...

Page 298: ...DLEx0 Bits 0 Note ALVEx bit of OCTLEn register Remarks 1 fCLK fCPU Base clock 2 x 1 to 4 n 0 to 2 Figure 9 44 Timer E Signal Output Operation During Delay Output Operation When OCTLEn Register s OTMEx1 OTMEx0 Bits 0 ALVEx 0 SWFEx Bit 0 Note Refer to 11 Timer E output delay registers 0 to 2 ODELE0 to ODELE2 on page 279 Remarks 1 fCLK fCPU Base clock 2 x 1 to 4 n 0 to 2 fCLK ALVExNote TOExn timer ou...

Page 299: ... functions can be used at the same time Figure 10 1 shows the block diagram of the watch timer Figure 10 1 Block Diagram of Watch Timer fW 29 Selector 11 bit prescaler fW 28 fW 2 7 fW 26 fW 25 fW 24 5 bit counter INTWT INTWTI WTM0 WTM1 WTM3 WTM4 WTM5 WTM6 WTM7 Watch timer mode control register WTM Internal bus Clear Clear WTM2 fW 211 fW 210 Selector Selector Selector CKSEL1 CKSEL2 f f fW ...

Page 300: ...als specified in advance Table 10 1 Interval Time of Interval Timer fSUB 4 MHz Remarks 1 fw Watch timer clock frequency 2 interval times change accordingly if fSUB 5 MHz 10 2 Configuration The watch timer consists of the following hardware Table 10 2 Configuration of Watch Timer Interval Time fw fCKSEL2 fw fCKSEL1 24 1 fW 2 408 ms 512 µs 25 1 fW 4 096 ms 1 024 ms 26 1 fW 8 192 ms 2 048 ms 27 1 fW ...

Page 301: ...3 2 1 0 Address R W After Reset WTM WTM7 WTM6 WTM5 WTM4 WTM3 WTM2 WTM1 WTM0 FFFFF560H R W 00H WTM6 WTM5 WTM4 Selects Interval Time of Prescaler fSUB 4 MHz 0 0 0 24 fW 2 408 ms 512 µs 0 0 1 25 fW 4 096 ms 1 024 ms 0 1 0 26 fW 8 192 ms 2 048 ms 0 1 1 27 fW 16 384 ms 4 096 ms 1 0 0 28 fW 32 768 ms 8 192 ms 1 0 1 29 fW 65 536 ms 16 384 ms 1 1 0 210 fW 131 072 ms 32 768 ms 1 1 1 211 fW 262 144 ms 62 53...

Page 302: ...302 Chapter 10 Watch Timer Preliminary User s Manual U14913EE1V0UM00 Sub Clock fSUB Input Clock fw 4 MHz fCKSEL1 31250 Hz 4 MHz fCKSEL2 7812 5 Hz 5 MHz fCKSEL1 39062 5 Hz 5 MHz fCKSEL2 9765 625 Hz ...

Page 303: ... 09715 s to 512 µs may occur when the watch timer overflows INTWT Notes 1 fSUB 4 MHz with fw of 31250 Hz fCKSEL1 7812 5 Hz fCKSEL2 2 fSUB 5 MHz with fw of 39062 5 Hz fCKSEL1 9765 625 Hz fCKSEL2 10 4 2 Operation as interval timer The watch timer can also be used as an interval timer that repeatedly generates an interrupt at intervals specified by a count value set in advance The interval time can b...

Page 304: ...z fCKSEL2 2 fSUB 5 MHz with fw of 39062 5 Hz fCKSEL1 9765 625 Hz fCKSEL2 Remarks 1 fw Watch timer clock frequency 2 n Interval timer operation numbers Start 5 bit counter Overflow Overflow 0H Interrupt time of watch timer Interrupt time of watch timer Interval time T Count clock fW or fW 211 Watch timer interrupt INTWT Interval timer interrupt INTWTI nT nT Note Note Interval time T ...

Page 305: ...d a non maskable interrupt can be gen erated Table 11 1 Runaway Detection Time by Watchdog Timer Note fSUB 4 MHz with fw of 31250 Hz fCKSEL1 7812 5 Hz fCKSEL2 fSUB 5 MHz with fw of 39062 5 Hz fCKSEL1 9765 625 Hz fCKSEL2 Clock Runaway detection time fSUB 4 MHz fSUB 5 MHz 215 fCKSEL1 1 04 s 0 839 s 214 fCKSEL1 0 52 s 0 419 s 26 fCKSEL1 0 002 s 0 0016 s 25 fCKSEL1 0 001 s 0 0008 s 215 fCKSEL2 4 19 s ...

Page 306: ... the set time 7 6 5 4 3 2 1 0 Address R W At Reset WDTM WDTEN WDTM 0 0 0 WDCK2 WDCK1 WDCK0 FFFFF570H R W 00H Bit name Function WDTEN Watch Dog Timer enable Starts Stops and clears Watch Dog Timer 0 Watch Dog Timer not started 1 clear counter and start counting continue counting Note Once set only a reset signal clears this bit WDTM Watch Dog Timer Mode Selects event type 0 watch dog timer generate...

Page 307: ...f WDTEN is not set to 1 and the runaway detection time has elapsed a non maskable interrupt NMI WDT or a RESET is generated The watchdog timer stops running in the STOP mode Consequently set WDTEN to 1 and clear the watchdog timer before entering the STOP mode Caution Sometimes the actual runaway detection time is a maximum of 0 5 less than the set time Table 11 2 Runaway Detection Time by Watchdo...

Page 308: ...308 Preliminary User s Manual U14913EE1V0UM00 MEMO ...

Page 309: ... UART2 3 channels 2 Clocked serial interfaces CSI0 CSI1 2 channels 3 FCAN controller 3 channels Remark For details about the FCAN controller refer to Chapter 13 FCAN Interface Function UART0 to UART2 transmit receive 1 byte serial data following a start bit and support full duplex com munication CSI0 and CSI1 perform data transfer according to three types of signals namely serial clocks SCK0 SCK1 ...

Page 310: ...Framing error Overrun error Interrupt sources 3 types Reception error interrupt INTSERn Interrupt is generated according to the logical OR of the three types of reception errors Reception completion interrupt INTSRn Interrupt is generated when receive data is trans ferred from the shift register to the reception buffer register after serial transfer is completed during a reception enabled state Tr...

Page 311: ...er data flag which indicates the hold status of TXBn data and the transmission shift register data flag which indicates whether transmission is in progress 4 Reception control parity check The receive operation is controlled according to the contents set in the ASIMn register A check for parity errors is also performed during a receive operation and if an error is detected a value corre sponding t...

Page 312: ...ntrol parity A transmit operation is controlled by adding a start bit parity bit or stop bit to the data that is written to the TXBn register according to the contents that were set in the ASIMn register Figure 12 1 Asynchronous Serial Interfaces 0 to 2 Block Diagram Remark n 0 to 2 Parity Framing Overrun Internal bus Asynchronous serial interface mode register n ASIMn Reception buffer register n ...

Page 313: ...ir cuit are performed with the CAE bit When the CAE bit is set to 0 the UARTn operation clock stops fixed to low level and an asynchronous reset is applied to internal UARTn latch The TXDn pin output is low level when the CAE bit 0 and high level when the CAE bit 1 Therefore perform CAE setting in combination with port mode register PM1 PM2 PM6 so as to avoid malfunction on the other side at start...

Page 314: ...ization may not be successful For details about the base clock refer to 12 2 6 Dedicated baud rate gen erators 1 to 3 BRG1 to BRG3 4 3 PS1 PS0 Controls parity bit PS1 PS0 Transmit Operation Receive Operation 0 0 Don t output parity bit Receive with no parity 0 1 Output 0 parity Receive as 0 parity 1 0 Output odd parity Judge as odd parity 1 1 Output even parity Judge as even parity Cautions 1 To o...

Page 315: ...a 0 7 bits 1 8 bits Caution To overwrite the CL bit first clear 0 the TXE and RXE bits 1 SL Specifies stop bit length of transmit data 0 1 bit 1 2 bits Caution To overwrite the SL bit first clear 0 the TXE bit Since reception is always done using a single stop bit the SL bit setting does not affect receive operations 0 ISRM Enables disables generation of reception completion interrupt requests whe...

Page 316: ...s Initial value ASIS0 0 0 0 0 0 PE FE OVE FFFFFA03H 00H 7 6 5 4 3 2 1 0 Address Initial value ASIS1 0 0 0 0 0 PE FE OVE FFFFFA13H 00H 7 6 5 4 3 2 1 0 Address Initial value ASIS2 0 0 0 0 0 PE FE OVE FFFFFA23H 00H Bit Position Bit Name Function 2 PE This is a status flag that indicates a parity error 0 When the ASIMn register s CAE and RXE bits are both set to 0 or when the ASISn register has been r...

Page 317: ...o TXBn register 7 6 5 4 3 2 1 0 Address Initial value ASIF0 0 0 0 0 0 0 TXBF0 TXSF0 FFFFFA05H 00H 7 6 5 4 3 2 1 0 Address Initial value ASIF1 0 0 0 0 0 0 TXBF0 TXSF0 FFFFFA15H 00H 7 6 5 4 3 2 1 0 Address Initial value ASIF2 0 0 0 0 0 0 TXBF0 TXSF0 FFFFFA25H 00H Bit Position Bit Name Function 1 TXBF This is a transmission buffer data flag 0 When the ASIMn register s CAE or TXE bits is 0 or when dat...

Page 318: ...rring data to the RXBn register even when the shift in processing of one frame is completed Also no reception completion interrupt is generated When 7 bits is specified for the data length bits 6 to 0 of the RXBn register are transferred for the receive data and the MSB bit 7 is always 0 However if an overrun error OVE occurs the receive data at that time is not transferred to the RXBn register Ex...

Page 319: ...synchronized with the completion of the transmission of one frame from the transmission shift register For information about the timing for generating this interrupt request refer to 12 2 5 2 Transmit operation on page 322 When TXBF bit 1 in the ASIFn register writing must not be performed to TXBn register This register can be read or written in 8 bit or 1 bit units n 0 to 2 Figure 12 6 Transmissi...

Page 320: ...or a reception completion interrupt INTSRn is generated when an error occurs can be specified according to the ISRM bit of the ASIMn register When reception is disabled no reception error interrupt is generated 2 Reception completion interrupt INTSR0 to INTSR2 When reception is enabled a reception completion interrupt is generated when data is shifted in to the reception shift register and transfe...

Page 321: ...n Figure 12 7 The character bit length within one data frame the type of parity and the stop bit length are speci fied according to the asynchronous serial interface mode register ASIMn n 0 to 2 Also data is transferred with LSB first Figure 12 7 Asynchronous Serial Interface Transmit Receive Data Format Start bit 1 bit Character bits 7 bits or 8 bits Parity bit Even parity odd parity 0 parity or ...

Page 322: ...ansmission shift register outputs data to the TXDn pin the transmit data is transferred sequential starting with the start bit The start bit parity bit and stop bits are added automatically c Transmission interrupt request When the transmission shift register becomes empty a transmission completion interrupt request INTSTn is generated The timing for generating the INTSTn interrupt differs accordi...

Page 323: ...he transmission status and whether or not data can be written to the TXBn reg ister n 0 to 2 Caution Transmit data should be written when the TXBF bit is 0 The transmission unit should be initialized when the TXSF bit is 0 If these actions are performed at other times the transmit data cannot be guaranteed Table 12 2 Transmission Status and Whether or Not Writing Is Enabled TXBF TXSF Transmission ...

Page 324: ...erate start bit Start data 1 transmissionNote 0 1 4 Read ASIFn register confirm that TXBF bit 0 Write data 2 1 1 Transmission in progress 5 Generate transmission completion interrupt INTSTn 0 1 6 Read ASIFn register confirm that TXBF bit 0 Write data 3 1 1 7 Generate start bit Start data 2 transmission Transmission in progress 8 Generate transmission completion interrupt INTSTn 0 1 9 Read ASIFn re...

Page 325: ...ission in progress 5 Generate transmission completion interrupt INTSTn 0 1 6 Read ASIFn register confirm that TXSF bit 1 There is no write data 7 Generate start bit Start data n transmission Transmission in progress 8 Generate transmission completion interrupt INTSTn 0 0 9 Read ASIFn register confirm that TXSF bit 0 Clear 0 the CAE bit or TXE bit of ASIMn register Initialize internal circuits Star...

Page 326: ... to 2 c Reception completion interrupt When RXE bit 1 in the ASIMn register and the reception of one frame of data is completed the stop bit is detected a reception completion interrupt INTSRn is generated and the receive data within the reception shift register is transferred to RXBn at the same time Also if an overrun error OVE occurs the receive data at that time is not transferred to the recep...

Page 327: ...d as an INTSERn interrupt by clearing the ISRM bit of the ASIMn register to 0 Figure 12 12 When Reception Error Interrupt Is Separated from INTSRn Interrupt ISRM Bit 0 a No error occurs during reception b An error occurs during reception Figure 12 13 When Reception Error Interrupt Is Included in INTSRn Interrupt ISRM Bit 1 a No error occurs during reception b An error occurs during reception Error...

Page 328: ...number is odd b Odd parity During transmission In contrast to even parity the parity bit is controlled so that the number of bits with the value 1 within the transmit data including the parity bit is odd The parity bit value is as follows If the number of bits with the value 1 within the transmit data is odd 0 If the number of bits with the value 1 within the transmit data is even 1 During recepti...

Page 329: ...is not delivered to the internal circuit see Figure 12 15 Refer to 12 2 6 1 a Basic clock Clock regarding the basic clock Also since the circuit is configured as shown in Figure 12 14 internal processing during a receive operation is delayed by up to 2 clocks according to the external signal status Figure 12 14 Noise Filter Circuit Figure 12 15 Timing of RXDn Signal Judged as Noise Remark n 0 to 2...

Page 330: ... for reception 1 Baud rate generator configuration Figure 12 16 Baud Rate Generator BRG Configuration of UARTn n 0 to 2 Remark n 0 to 2 a Basic clock Clock When CAE bit 1 in the ASIMn register the clock selected according to the TPS3 to TPS0 bits of the CKSRm register is supplied to the transmission reception unit This clock is called the basic clock Clock and its frequency is referred to as fCLK ...

Page 331: ...k of the transmis sion reception module Its frequency is referred to as fCLK This register can be read or written in 8 bit or 1 bit units Figure 12 17 Clock Select Registers 1 to 3 CKSR1 to CKSR3 7 6 5 4 3 2 1 0 Address Initial value CKSR0 0 0 0 0 TPS3 TPS2 TPS1 TPS0 FFFFFA06H 00H 7 6 5 4 3 2 1 0 Address Initial value CKSR1 0 0 0 0 TPS3 TPS2 TPS1 TPS0 FFFFFA16H 00H 7 6 5 4 3 2 1 0 Address Initial ...

Page 332: ...cording to MDL7 to MDL0 bits k 8 9 10 255 3 The baud rate is the output clock for the 8 bit counter divided by 2 4 x don t care 7 6 5 4 3 2 1 0 Address Initial value BRGC0 MDL7 MDL6 MDL5 MDL4 MDL3 MDL2 MDL1 MDL0 FFFFFA07H FFH 7 6 5 4 3 2 1 0 Address Initial value BRGC1 MDL7 MDL6 MDL5 MDL4 MDL3 MDL2 MDL1 MDL0 FFFFFA17H FFH 7 6 5 4 3 2 1 0 Address Initial value BRGC2 MDL7 MDL6 MDL5 MDL4 MDL3 MDL2 MD...

Page 333: ...utions 1 Make sure that the baud rate error during transmission does not exceed the allow able error of the reception destination 2 Make sure that the baud rate error during reception is within the allowable baud rate range during reception which is described in chapter 12 2 6 3 Allowable baud rate range during reception Example Basic clock frequency 10 MHz Settings of MDL7 to MDL0 bits in BRGC0 r...

Page 334: ...fCPU 128 130 0 16 fCPU 128 104 0 16 fCPU 32 130 0 16 fCPU 32 104 0 16 1200 fCPU 64 130 0 16 fCPU 64 104 0 16 fCPU 16 130 0 16 fCPU 16 104 0 16 2400 fCPU 32 130 0 16 fCPU 32 104 0 16 fCPU 8 130 0 16 fCPU 8 104 0 16 4800 fCPU 16 130 0 16 fCPU 16 104 0 16 fCPU 4 130 0 16 fCPU 4 104 0 16 9600 fCPU 8 130 0 16 fCPU 8 104 0 16 fCPU 2 130 0 16 fCPU 2 104 0 16 19200 fCPU 4 130 0 16 fCPU 4 104 0 16 fCPU 2 6...

Page 335: ...register If all data up to the final data stop bit is in time for this latch timing the data can be received normally Applying this to 11 bit reception is theoretically as follows FL BR 1 BR UARTn baud rate k BRGCm register setting value FL 1 bit data length When the latch timing margin is made 2 basic clocks Clock the minimum allowable transfer rate FLmin is as follows Therefore the transfer dest...

Page 336: ...puting the minimum and maximum baud rate values Table 12 5 Maximum and Minimum Allowable Baud Rate Error Remarks 1 The reception precision depends on the number of bits in one frame the basic clock fre quency and the division ratio k The higher the basic clock frequency and the larger the division ratio k the higher the precision 2 k BRGCm setting value Division Ratio k Maximum Allowable Baud Rate...

Page 337: ...n Therefore the transfer rate during continuous transmission is as follows 12 2 7 Precautions When the supply of clocks to UARTn n 0 to 2 is stopped for example IDLE or STOP mode opera tion stops with each register retaining the value it had immediately before the supply of clocks was stopped The TXDn pin output also holds and outputs the value it had immediately before the supply of clocks was st...

Page 338: ...first Eight clock signals can be selected 7 master clocks and 1 slave clock 3 wire type SOn Serial transmit data output SIn Serial transmit data input SCKn Serial clock input output Interrupt sources 1 type Transmission reception completion interrupt INTCSIn Transmission reception mode and reception only mode can be specified Two transmission buffers SOTBFn SOTBFLn SOTBn SOTBLn and two reception b...

Page 339: ... transmission reception operations are started up by access of the buffer register 5 Clocked serial interface reception buffer registers 0 1 SIRB0 SIRB1 The SIRBn register is a 16 bit buffer register that stores receive data 6 Clocked serial interface reception buffer registers L0 L1 SIRBL0 SIRBL1 The SIRBLn register is an 8 bit buffer register that stores receive data 7 Clocked serial interface r...

Page 340: ...ounter Counts the serial clock output or input during transmission reception operation and checks whether 8 bit data transmission reception has been performed 16 Interrupt control circuit Controls the interrupt request timing Figure 12 21 Block Diagram of Clocked Serial Interfaces Remark n 0 1 Selector Transmission control SO selection SO latch Transmit data buffer register SOTBn SOTBLn Receive da...

Page 341: ... to 0 For the SCKn and SOn pin output status when the CSIE bit 0 refer to 12 3 5 Output pins 6 TRMD Specifies transmission reception mode 0 Receive only mode 1 Transmission reception mode When the TRMD bit 0 receive only transfer is performed and the SOn pin output is fixed to low level Data reception is started by reading the SIRBn register When the TRMD bit 1 transmission reception is started by...

Page 342: ... 4 3 CKP DAP Specifies operation mode CKP DAP Operation Mode 0 0 0 1 1 0 1 1 Remark n 0 1 2 to 0 CKS2 to CKS0 Specifies input clock CKS2 CKS1 CKS0 Input Clock Mode 0 0 0 fCPU 4 Master mode 0 0 1 Internal BRG Channel 0 Master mode 0 1 0 Internal BRG Channel 1 Master mode 0 1 1 fCPU 8 Master mode 1 0 0 fCPU 16 Master mode 1 0 1 fCPU 32 Master mode 1 1 0 fCPU 64 Master mode 1 1 1 External clock SCKn ...

Page 343: ...0 1 SIRB0 SIRB1 Cautions 1 Read the SIRBn register only when the 16 bit data length has been set CCL bit of CSIMn register 1 2 When the single transfer mode has been set AUTO bit of CSIMn register 0 per form read operation only in the idle state CSOT bit of CSIMn register 0 If the SIRBn register is read during data transfer the data cannot be guaranteed 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Addres...

Page 344: ...s the same as the lower bytes of the SIRBn register Figure 12 25 Clocked Serial Interface Reception Buffer Registers L0 L1 SIRBL0 SIRBL1 Cautions 1 Read the SIRBLn register only when the 8 bit data length has been set CCL bit of CSIMn register 0 2 When the single transfer mode is set AUTO bit of CSIMn register 0 perform read operation only in the idle state CSOT bit of CSIMn register 0 If the SIRB...

Page 345: ...al Interface Read Only Reception Buffer Registers 0 1 SIRBE0 SIRBE1 Cautions 1 The receive operation is not started even if data is read from the SIRBEn register 2 The SIRBEn register can be read only if the 16 bit data length is set CCL bit of CSIMn register 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value SIRBE0 SIRBE15 SIRBE14 SIRBE13 SIRBE12 SIRBE11 SIRBE10 SIRBE9 SIRBE8 SIRBE7 SI...

Page 346: ...Bn register It is used to read the contents of the SIRBLn register Figure 12 27 Clocked Serial Interface Read Only Reception Buffer Registers L0 L1 SIRBEL0 SIRBEL1 Cautions 1 The receive operation is not started even if data is read from the SIRBELn register 2 The SIRBELn register can be read only if the 8 bit data length has been set CCL bit of CSIMn register 0 7 6 5 4 3 2 1 0 Address Initial val...

Page 347: ...TBn register only when the 16 bit data length is set CCL bit of CSIMn register 1 2 When the single transfer mode is set AUTO bit of CSIMn register 0 perform access only in the idle state CSOT bit of CSIMn register 0 If the SOTBn register is accessed during data transfer the data cannot be guaranteed 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value SOTB0 SOTB15 SOTB14 SOTB13 SOTB12 SOTB1...

Page 348: ...ter Figure 12 29 Clocked Serial Interface Transmission Buffer Registers L0 L1 SOTBL0 SOTBL1 Cautions 1 Access the SOTBLn register only when the 8 bit data length has been set CCL bit of CSIMn register 0 2 When the single transfer mode is set AUTO bit of CSIMn register 0 perform access only in the idle state CSOT bit of CSIMn register 0 If the SOTBLn regis ter is accessed during data transfer the d...

Page 349: ...BFn register only when the 16 bit data length has been set CCL bit of CSIMn register 1 and only in the idle state CSOT bit of CSIMn register 0 If the SOTBFn register is accessed during data transfer the data cannot be guaranteed 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value SOTBF0 SOTBF15 SOTBF14 SOTBF13 SOTBF12 SOTBF11 SOTBF10 SOTBF9 SOTBF8 SOTBF7 SOTBF6 SOTBF5 SOTBF4 SOTBF3 SOTBF2 ...

Page 350: ...register Figure 12 31 Clocked Serial Interface Initial Transmission Buffer Registers L0 L1 SOTBFL0 SOTBFL1 Caution Access the SOTBFLn register only when the 8 bit data length has been set CCL bit of CSIM0 register 0 and only in the idle state CSOT bit of CSIMn register 0 If the SOTBFLn register is accessed during data transfer the data cannot be guaranteed 7 6 5 4 3 2 1 0 Address Initial value SOT...

Page 351: ...aution Access the SIOn register only when the 16 bit data length has been set CCL bit of CSIMn register 1 and only in the idle state CSOT bit of CSIMn register 0 If the SIOn register is accessed during data transfer the data cannot be guaranteed 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value SIO0 SIO15 SIO14 SIO13 SIO12 SIO11 SIO10 SIO9 SIO8 SIO7 SIO6 SIO5 SIO4 SIO3 SIO2 SIO1 SIO0 FFF...

Page 352: ...the same as the lower bytes of the SIOn register Figure 12 33 Serial I O Shift Registers L0 L1 SIOL0 SIOL1 Caution Access the SIOLn register only when the 8 bit data length has been set CCL bit of CSIMn register 0 and only in the idle state CSOT bit of CSIMn register 0 If the SIOLn register is accessed during data transfer the data cannot be guaranteed 7 6 5 4 3 2 1 0 Address Initial value SIOL0 S...

Page 353: ...ster 1 has been set read the SIRBn register When the 8 bit data length CCL bit of CSIMn register 0 has been set read the SIRBLn register 2 When the 16 bit data length CCL bit of CSIMn register 1 has been set write to the SOTBn register When the 8 bit data length CCL bit of CSIMn register 0 has been set write to the SOTBLn register Caution When the CSOT bit of the CSIMn register 1 do not manipulate...

Page 354: ...ation mode CKP bit 0 DAP bit 1 Remarks 1 n 0 1 2 Reg_R W Internal signal This signal indicates that receive data buffer register SIRBn SIRBLn read or transmit data buffer register SOTBn SOTBLn write was performed 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 AAH AAH ABH 56H ADH 5AH B5H 6AH D5H SCKn input output SOn output SIn input output Reg_R W SOTBLn register SIOLn register SIRBLn register CSOT bit INTCSIn i...

Page 355: ...t signal delay control CSIT bit of CSIMn register 0 Figure 12 35 Timing Chart According to Clock Phase Selection 1 2 a When CKP bit 0 DAP bit 0 b When CKP bit 1 DAP bit 0 Remarks 1 n 0 1 2 Reg_R W Internal signal This signal indicates that receive data buffer register SIRBn SIRBLn read or transmit data buffer register SOTBn SOTBLn write was performed DI7 DI6 DI5 DI4 DI3 DI2 DI1 DO7 DO6 DO5 DO4 DO3...

Page 356: ...nternal signal This signal indicates that receive data buffer register SIRBn SIRBLn read or transmit data buffer register SOTBn SOTBLn write was performed DI7 DI6 DI5 DI4 DI3 DI2 DI1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 SCKn input output SIn input SOn output Reg_R W INTCSIn interrupt CSOT bit DI0 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 SCKn input output SIn input SOn output Reg_R W INTC...

Page 357: ...re not 111B The delay mode cannot be set when the slave mode is set bits CKS2 to CKS0 111B Figure 12 36 Timing Chart of Interrupt Request Signal Output in Delay Mode 1 2 a When CKP bit 0 DAP bit 0 Remarks 1 n 0 1 2 Reg_R W Internal signal This signal indicates that receive data buffer register SIRBn SIRBLn read or transmit data buffer register SOTBn SOTBLn write was performed DI7 DI6 DI5 DI4 DI3 D...

Page 358: ...b When CKP bit 1 DAP bit 1 Remarks 1 n 0 1 2 Reg_R W Internal signal This signal indicates that receive data buffer register SIRBn SIRBLn read or transmit data buffer register SOTBn SOTBLn write was performed DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Input clock SCKn input output SIn input SOn output Reg_R W INTCSIn interrupt CSOT bit Delay ...

Page 359: ...d by reading the SIOn register Figure 12 37 Repeat Transfer Receive Only Timing Chart Remarks 1 n 0 1 2 Reg_RD Internal signal This signal indicates that the receive data buffer register SIRBn SIRBLn has been read rq_clr Internal signal Transfer request clear signal trans_rq Internal signal Transfer request signal In the case of the repeat transfer mode two transfer requests are set at the start o...

Page 360: ...ignal indicates that the transmit data buffer register SOTBn SOTBLn has been written Reg_RD Internal signal This signal indicates that the receive data buffer register SIRBn SIRBLn has been read rq_clr Internal signal Transfer request clear signal trans_rq Internal signal Transfer request signal In the case of the repeat transfer mode two transfer requests are set at the start of the first transfe...

Page 361: ...ration mode CKP bit 0 DAP bit 0 b When data length 16 bits operation mode CKP bit 0 DAP bit 0 c When data length 8 bits operation mode CKP bit 0 DAP bit 1 d When data length 16 bits operation mode CKP bit 0 DAP bit 1 Remark n 0 1 SCKn input output INTCSIn interrupt Reservation period 7 SCKn cycles SCKn input output INTCSIn interrupt Reservation period 15 SCKn cycles SCKn input output INTCSIn inter...

Page 362: ...curs In case of contention between transfer request clear and register access Since request cancellation has higher priority the next transfer request is ignored Therefore trans fer is interrupted and normal data transfer cannot be performed Figure 12 40 Transfer Request Clear and Register Access Contention Remarks 1 n 0 1 2 rq_clr Internal signal Transfer request clear signal Reg_WR Internal sign...

Page 363: ...or results refer to Figure 12 41 In the transmission reception mode the value of the SOTBFn register is retransmitted and illegal data is sent Figure 12 41 Interrupt Request and Register Access Contention Remarks 1 n 0 1 2 rq_clr Internal signal Transfer request clear signal Reg_WR Internal signal This signal indicates that the transmit data buffer register SOTBn SOTBLn has been written SCKn input...

Page 364: ...en any of bits TRMD CCL DIR AUTO and CSICn of the CSIMn register or DAP bit of the CSICn register is overwritten the SOn pin output changes 2 SOTBm Bit m of SOTBn register m 0 7 15 3 SOTBFm Bit m of SOTBFn register m 0 7 15 4 n 0 1 CKP CKS2 CKS1 CKS0 SCKn Pin Output 0 Don t care Don t care Don t care Fixed to high level 1 1 1 1 Fixed to high level Other than above Fixed to low level TRMD DAP AUTO ...

Page 365: ...egisters CSIC0 and CSIC1 refer to 12 3 3 2 Clocked serial interface clock selection registers 0 1 CSIC0 CSIC1 If the dedicated baud rate generator output is specified BRG0 or BRG1 respectively is selected as the clock source Since the same serial clock can be shared for transmission and reception baud rate is the same for the transmission reception Figure 12 42 Baud Rate Generators 0 1 BRG0 BRG1 B...

Page 366: ...n in 8 bit or 1 bit units n 0 1 Figure 12 43 Prescaler Mode Registers 0 1 PRSM0 PRSM1 Cautions 1 Do not change the value of the BGCS1 BGCS0 bits during transmission reception operation 2 Set the PRSMn register prior to setting the CE bit to 1 7 6 5 4 3 2 1 0 Address Initial value PRSM0 0 0 0 CE 0 0 BGCS1 BGCS0 FFFFF920H 00H 7 6 5 4 3 2 1 0 Address Initial value PRSM1 0 0 0 CE 0 0 BGCS1 BGCS0 FFFFF...

Page 367: ...ontents of the PRSCMn register are overwritten when the value of the CE bit is 1 the cycle of the baud rate signal is not guaranteed d Baud rate signal cycle The baud rate signal cycle is calculated as follows When setting value of PRSCMn register is 00H Cycle of signal selected with bits BGCS1 BGCS0 of PRSMn register 256 2 In cases other than above Cycle of signal selected with bits BGCS1 BGCS2 o...

Page 368: ... below the minimum value of 200 ns of the SCKn cycle tCYSK1 prescribed in the electrical specifications BGCS1 BGCS0 PRSCM Register Value Clock Hz 0 0 1 4000000 0 0 2 2000000 0 0 4 1000000 0 0 8 500000 0 0 16 250000 0 0 40 100000 0 0 80 50000 0 0 160 25000 0 1 200 10000 1 0 200 5000 BGCS1 BGCS0 PRSCM Register Value Clock Hz 0 0 2 2500000 0 0 5 1000000 0 0 10 500000 0 0 20 250000 0 0 50 100000 0 0 1...

Page 369: ...otal Mask option for receive messages BasicCAN channels 4 masks per CAN module each mask can be assigned to each message Buffered reception FIFO Message buffers can be redefined in normal operation mode FCAN interface and CPU share common RAM area Interrupt on receive transmit and error condition Time stamp and global time system function Two power save modes SLEEP mode wake up at CAN bus activity...

Page 370: ...ovide no memory for the necessary data buffers rather all CAN mod ules have access to the common CAN memory area via a memory access controller MAC The MAC allows integration of machines other than CAN modules e g CAN bridge The CAN bridge accomplishes data processing among the CAN modules without involving the CPU The CPU also accesses to the common CAN memory via the MAC The MAC offers data scan...

Page 371: ...ined as illegal addresses or CANx temporary buffer x 1 to 3 Remarks 1 Areas defined as illegal addresses contain neither FCAN registers nor FCAN buffers Those area must not be read nor written by user program 2 CANx temporary buffers can be accessed by CPU write and read accesses when the GOM bit of the CGST register is cleared 0 means FCAN system inactive Whenever the FCAN system is in global ope...

Page 372: ...software As a consequence the message buffers can be allocated to a CAN module according to the need of the particular CAN network Table 13 1 Configuration of the CAN Message Buffer Section Note The address of a message buffer entry is calculated according to the following formula effective address PP_BASE address offset Each message buffer has the same register layout refer to Table 13 2 Address ...

Page 373: ... length code register 420 R W m 20H 005H M_CTRLm Message control register 421 R W m 20H 006H M_TIMEm Message time stamp register 423 R W m 20H 008H M_DATAm0 Message data byte 0 418 R W m 20H 009H M_DATAm1 Message data byte 1 R W m 20H 00AH M_DATAm2 Message data byte 2 R W m 20H 00BH M_DATAm3 Message data byte 3 R W m 20H 00CH M_DATAm4 Message data byte 4 R W m 20H 00DH M_DATAm5 Message data byte 5...

Page 374: ...lated according to the following formula effective address PP_BASE address offset Address Off setNote Symbol Name Ref Page Access Type Comment R W 1 bit 8 bits 16 bits 800H CCINTP CAN interrupt pending register 408 R 802H CGINTP CAN global interrupt pending register 409 R W bit set function only 804H C1INTP CAN1 interrupt pending register 411 R W bit clear function only 806H C2INTP CAN2 interrupt ...

Page 375: ...mbol Name Ref Page Access Type Comment R W 1 bit 8 bits 16 bits 80CH CSTOP CAN stop register 396 R W 810H CGST CAN global status register 399 R W bit set clear function 812H CGIE CAN global interrupt enable register 401 R W bit set clear function 814H CGCS CAN main clock select register 397 R W only if GOM bit 0 816H CGTEN CAN timer event enable register 403 R W 818H CGTSC CAN global time system c...

Page 376: ... W lower half word 846H C1MASKH1 CAN1 mask 1 register H R W upper half word 848H C1MASKL2 CAN1 mask 2 register L R W lower half word 84AH C1MASKH2 CAN1 mask 2 register H R W upper half word 84CH C1MASKL3 CAN1 mask 3 register L R W lower half word 84EH C1MASKH3 CAN1 mask 3 register H R W upper half word 850H C1CTRL CAN1 control register 427 R W bit set clear function 852H C1DEF CAN1 definition regi...

Page 377: ...er half word 88EH C2MASKH3 CAN2 mask 3 register H R W upper half word 890H C2CTRL CAN2 control register 427 R W bit set clear function 892H C2DEF CAN2 definition register 431 R W bit set clear function 894H C2LAST CAN2 information register 434 R read only 896H C2ERC CAN2 error counter register 435 R read only 898H C2IE CAN2 interrupt enable register 436 R W bit set clear function 89AH C2BA CAN2 bu...

Page 378: ...er half word 8CEH C3MASKH3 CAN3 mask 3 register H R W upper half word 8D0H C3CTRL CAN3 control register 427 R W bit set clear function 8D2H C3DEF CAN3 definition register 431 R W bit set clear function 8D4H C3LAST CAN3 information register 434 R read only 8D6H C3ERC CAN3 error counter register 435 R read only 8D8H C3IE CAN3 interrupt enable register 436 R W bit set clear function 8DAH C3BA CAN3 bu...

Page 379: ...tNote Symbol Name Ref Page Access Type Comment R W 1 bit 8 bits 16 bits A10H TEP0 Timer event pointer register 0 480 R W A11H TEP1 Timer event pointer register 1 R W A12H Reserved A13H TEP3 Timer event pointer register 3 480 R W A14H SEPCC Script event pointer and com mand counter register 481 R W A16H EEPS ELISA event processing status register 482 R W A18H ELSR ELISA status register 483 R W bit ...

Page 380: ...unctional block is supplied by the global time system clock fGTS which is derived from fMEM The time system prescaler scales fGTS and is also controlled by the CGCS register The time base of the global time system is realised by the 16 bit free running counter the CAN global time system counter CGTSC Time stamp information is captured from the CGTSC counter For details refer to chapter 13 2 5 Time...

Page 381: ...ng flags of a bundled interrupt signal group After the particular interrupt has been identified the corresponding interrupt pending flag must be reset by soft ware at least before leaving the interrupt service routine Figure 13 4 FCAN Interrupt Bundling of V850E CA1 Atomic Remark x 1 to 3 The interrupt pending registers of the FCAN system are CGINTP Global interrupt pending register C1INTP CAN mod...

Page 382: ...e message or it is captured at the time the message is detected as valid i e if no error was detected until the last but one bit of the end of frame EOF was received The selection of the two trigger options is controlled by the TMR bit in the CxCTRL register x 1 to 3 The capture value itself is stored in the M_TIMEm register m 00 to 63 of the message buffer for which the received message has been ...

Page 383: ... at SOF Remark m 00 to 63 M_DLCm Bus Data 1 Bus Data 2 Bus Data 3 Bus Data 4 Bus Data 5 Bus Data 6 Bus Data 7 Bus Data 8 1 M_DATAm 0 2 lower 8 bit of CGTSCNote upper 8 bit of CGTSC Note 3 M_DATAm 0 lower 8 bit of CGTSCNote upper 8 bit of CGTSC Note 4 M_DATAm 0 M_DATAm 1 lower 8 bit of CGTSCNote upper 8 bit of CGTSC Note 5 M_DATAm 0 M_DATAm 1 M_DATAm 2 lower 8 bit of CGTSCNote upper 8 bit of CGTSC ...

Page 384: ...ust always gain the CAN bus access against lower prior messages sent by other nodes at the same time due to arbitration mechanism of CAN protocol and against messages waiting to be transmitted in the same node i e inner prior ity inversion The FCAN system scans the message buffer section at the beginning of each message transmit to analyse that no other message with a higher priority is waiting to...

Page 385: ...e the user must allocate the 5 higher prior transmit messages to message buffers with a lower address There is no sorting needed among the 5 higher prior message buffer Message Buffer Address OffsetNote1 Message Buffer Number Message Buffer Link Message Buffer TypeNote2 Waiting for Transmission Identifier 7E0H 63 300H 24 2E0H 23 2C0H 22 CAN 1 TRX 123H 2A0H 21 280H 20 260H 19 240H 18 220H 17 200H 1...

Page 386: ... higher prior transmit messages assigned to messages buffer with lower address values Message Buffer Address OffsetNote1 Message Buffer Number Message Buffer Link Message Buffer TypeNote2 Identifier 7E0H 63 300H 24 2E0H 23 2C0H 22 CAN1 TRX 005H 2A0H 21 280H 20 260H 19 CAN1 TRX 006H 240H 18 220H 17 200H 16 1E0H 15 CAN1 TRX 007H 1C0H 14 CAN1 TRX 001H Note 3 1A0H 13 180H 12 160H 11 140H 10 CAN1 TRX 0...

Page 387: ... stored in the receive buffer linked to mask 2 but always into the non masked receive buffer Furthermore there is a fixed inner storage rule in case several buffers of the same priority class are linked to a CAN module For the inner priority class storage rule the data new flag DN in the M_STATm register is the first storage criteria m 00 to 63 Whenever the DN flag cannot provide an unambiguous cr...

Page 388: ...ous message storage As soon the CPU reads one of the message buffer with DN flag set and then clears the DN flag the storing in ascending message buffer number order is interrupted Due to the storage priority for receive messages it is possible to design multiple buffer arrays for a CAN message while not all message buffers assigned to the same identifier contain new data DN flag set the FCAN syst...

Page 389: ...s can be limited to reduce the CPU load caused by message sorting In the FCAN system each CAN module provides 4 different masks For a receive message buffer assigned to a CAN module one of the 4 masks can be selected when the BasicCAN concept is used When using a mask a certain identifier value must be written into the identifier register M_IDm equals 32 bit value build by M_IDHm and M_IDLm of the...

Page 390: ...hen setting the transmit request bit TRQ of the M_STATm register for a message buffer defined as receive message buffer m 00 to 63 Same as for generating a data frame from a transmit message buffer the ready bit RDY of M_STATm register must be set 1 Remote frames can also be generated by means of a transmit message buffer by setting the RTR bit of the M_CTRLm register and using the same transmissi...

Page 391: ...automatic remote frame handling activities from the FCAN system The application software must handle the remote frame in the expected way 2 RMDE0 RMDE1 bits as well as ATS bit of M_CTRLm register are set to 0 M_DLCm message data length code register M_CTRLm message control register M_TIMEm message time stamp register 16 bit M_DATAm0 message data byte 0 M_DATAm1 message data byte 1 M_DATAm2 message...

Page 392: ...the DN flag in the transmit message buffer No reaction at all Table 13 15 shows the detailed handling reaction upon the reception of a remote frame for a trans mit message buffer depending on the settings of RMDE0 RMDE1 and RTR flags Table 13 15 Remote Frame Handling upon Reception into a Transmit Message Buffer Note Auto answer upon remote frame is suppressed because the transmit message buffer i...

Page 393: ...s whether event processing for this message is pending In addition to this flag two 8 bit event pointers M_EVTm0 and M_EVTm1 are available M_EVTm0 is assigned for an event caused either by receiving a new data frame into the message buffer or by the successful transmission of a data frame from the message buffer M_EVTm1 is assigned for an event caused by receiving a remote frame into the message b...

Page 394: ...ELSR Remark x 1 to 3 Registers like above where bit access and direct write operations are prohibited are organized in such a way that all bits allowed for manipulation are located in the lower byte bits 7 to 0 while in the upper byte bits 15 to 8 either no or read only information is located The registers can be read in the usual way to get all 16 data bits in their actual setting ref to appropri...

Page 395: ...ess for better visi bility of the program code it is recommended to perform only 16 bit write accesses 2 n 0 to 7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ST_7 ST_6 ST_5 ST_4 ST_3 ST_2 ST_1 ST_0 CL_7 CL_6 CL_5 CL_4 CL_3 CL_2 CL_1 CL_0 Bit Name Function ST_n Sets the register bit n 0 No change of register bit n 1 Register bit n is set 1 CL_n Clears the register bit n 0 No change of register bit n 1 Re...

Page 396: ...y for the complete FCAN system The CSTP flag can be used to reduce the power consumption when the FCAN system is set to SLEEP mode and STOP mode to a minimum 0 FCAN system is supplied with clock fMEM 1 Clock supply of the FCAN system is stopped Remark When switching off the clock supply of the FCAN system during SLEEP mode wake up by CAN bus activity is possible But instead of CxINT4 interrupt i e...

Page 397: ...MCP0 814H 7F05H Bit Position Bit Name Function 15 to 8 CGTS7 to CGTS0 Specifies the 8 bit prescaler compare value for the global time system clock fGTS ref to Fig 13 11 Remark The global time system clock is the source clock for the 16 bit timer used for the time stamp functionality This clock is common for all CAN mod ules 7 6 GTCS1 GTCS0 Selects the global time system basic clock fGTS1 from the ...

Page 398: ...ELISA meaning all time events are derived from this clock See timer event module in the CAN bridge ELISA description for details Bit Position Bit Name Function 3 to 0 MCP3 to MCP0 Specifies the prescaler for the memory access clock fMEM ref to Fig 13 10 MCP3 MCP2 MCP1 MCP0 Prescaler m 1 Memory Clock fMEM fMEM1 m 1 0 0 0 0 1 fMEM fMEM1 0 0 0 1 2 fMEM fMEM1 2 0 0 1 0 3 fMEM fMEM1 3 1 1 1 1 16 fMEM f...

Page 399: ...ry access controller MAC 0 No error occurrence 1 At least one error occurred since the flag was cleared last A MAC error occurs under the following conditions An attempt to clear the GOM flag was performed although not all CAN modules are set to initialization state Access to an illegal address or access is prohibited by MAC see GOM flag description below 3 EFSD Enable forced shut down 0 Forced sh...

Page 400: ...ag If the software clears the flag while at least one CAN module is still not in initialisation state ISTAT flag of CxCTRL register x 1 to 3 is set 1 the GOM flag remains set Write Bit Position Bit Name Function 11 3 ST_EFSD CL_EFSD Sets clears the EFSD bit 10 2 ST_TSM CL_TSM Sets clears the TSM bit 9 1 ST_EVM CL_EVM Sets clears the EVM bit 8 0 ST_GOM CL_GOM Sets clears the GOM bit 7 CL_MERR Clear...

Page 401: ... 0 CL_ G_IE2 CL_ G_IE1 0 812H Read Bit Position Bit Name Function 7 G_IE7 Enables interrupt by CAN bridge ELISA 0 Interrupt disabled 1 Interrupt enabled 2 G_IE2 Enables illegal address interrupt 0 Interrupt disabled 1 Interrupt enabled Remarks 1 Interrupt signals an illegal address access refer to Figure 13 2 2 Interrupt signals a write access to temporary buffer while GOM bit of the CGST register...

Page 402: ...E2 Sets clears the G_IE2 bit 9 1 ST_G_IE1 CL_G_IE1 Sets clears the G_IE1 bit ST_G_IE7 CL_G_IE7 Status of G_IE7 Bit 0 1 G_IE7 bit is cleared 0 1 0 G_IE7 bit is set 1 Others No change in G_IE7 bit value ST_G_IE2 CL_G_IE2 Status of G_IE2 Bit 0 1 G_IE2 bit is cleared 0 1 0 G_IE2 bit is set 1 Others No change in G_IE2 bit value ST_G_IE1 CL_G_IE1 Status of G_IE1 Bit 0 1 G_IE1 bit is cleared 0 1 0 G_IE1 ...

Page 403: ... Function 3 CTEN3 Enables CAN timer event 3 0 Timer event disabled 1 Timer event enabled 2 CTEN2 Enables CAN timer event 2 0 Timer event disabled 1 Timer event enabled 1 CTEN1 Enables CAN timer event 1 0 Timer event disabled 1 Timer event enabled 0 CTEN0 Enables CAN timer event 0 0 Timer event disabled 1 Timer event enabled The timer events are as follows timer event 0 fGTS 210 timer event 1 fGTS ...

Page 404: ...read and writtenNote 1 in 16 bit units only Figure 13 16 CAN Global Time System Counter CGTSC Notes 1 When writing is performed to CGTSC register the counter is cleared to 0 2 The register address is calculated according to the following formula effective address PP_BASE address offset Remark The CGTSC register can be read at any time 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address OffsetNote2 Initi...

Page 405: ... M_STATm registers 0 Do not check status of TRQ flag and RDY flag 1 TRQ flag and RDY flag must be set 12 CMSK Search criteria for the mask link bits MT2 to MT0 of the M_CONFm registers 0 Do not check mask link bits 1 Check only message buffers not linked with a mask 11 CDN Search criteria for data new flag DN of the M_STATm registers 0 Do not check status of the DN flag 1 DN flag must be set 9 8 S...

Page 406: ...r search function 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address OffsetNote1 Initial value CGMSR 0 0 0 0 0 0 MM AM 0Note3 0Note3 MFND5 MFND4 MFND3 MFND2 MFND1 MFND0 81AH 0000H Bit Position Bit Name Function 9 8 MM AM Indicates the match result of the preceding message search 5 to 0 MFND5 to MFND0 Indicates the number of the message buffer which was found by the message search 0 to 63 Note 2 Remarks...

Page 407: ... system without any external hardware e g CAN transceiver bus harness etc 3 x 1 to 3 Caution The internal test bus must only be used when none of the CAN modules are con nected to a CAN bus 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address OffsetNote Initial value CTBR 0 0 0 0 0 0 0 0 0 0 0 0 0 RXEN TXPRE TEN 81CH 0000H Bit Position Bit Name Function 2 RXEN Enables the receive line 0 CAN module receiv...

Page 408: ...dicated interrupt pending registers CGINTP C1INTP C2INTP and C3INTP 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address OffsetNote 1 Initial value CCINTP INTACT INTMAC 0 0 0 0 0 CAN3ERR CAN3REC CAN3TRX CAN2ERR CAN2REC CAN2TRX CAN1ERR CAN1REC CAN1TRX 800H 0000H Bit Position Bit Name Note 2 Function 15 INTACT Indicates an interrupt of the CAN bridge ELISA GINT7 bit of CGINTP register 0 No Interrupt pendin...

Page 409: ... 0 0 0 CL_ GINT3 CL_ GINT2 CL_ GINT1 0 802H Read Bit Position Bit Name Function 7 GINT7 Indicates an interrupt of the CAN bridge ELISA GINT7 bit of CGINTP register 0 No Interrupt pending 1 Interrupt pending 3 GINT3 Indicates a wake up interrupt from CAN sleep mode while clock supply to the FCAN system was stopped ref to CSTOP register 0 No Interrupt pending 1 Interrupt pending 2 GINT2 Indicates an...

Page 410: ...ared by software in the interrupt service routine Caution In case the interrupt pending bit is not cleared by software in the interrupt service routine no subsequent interrupt is generated anymore Write Bit Position Bit Name Function 7 CL_GINT7 Clears the interrupt pending bit GINT7 0 No change of GINT7 bit 1 GINT7 bit is cleared 0 3 CL_GINT3 Clears the interrupt pending bit GINT3 0 No change of G...

Page 411: ...3 C2INT2 C2INT1 C2INT0 806H 0000H C3INTP 0 0 0 0 0 0 0 0 0 C3INT6 C3INT5 C3INT4 C3INT3 C3INT2 C3INT1 C3INT0 808H 0000H Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C1INTP 0 0 0 0 0 0 0 0 0 CL_ C1INT6 CL_ C1INT5 CL_ C1INT4 CL_ C1INT3 CL_ C1INT2 CL_ C1INT1 CL_ C1INT0 804H C2INTP 0 0 0 0 0 0 0 0 0 CL_ C2INT6 CL_ C2INT5 CL_ C2INT4 CL_ C2INT3 CL_ C2INT2 CL_ C2INT1 CL_ C2INT0 806H C3INTP 0 0 0 0 0 0 0 0 ...

Page 412: ...nding 0 CxINT0 Indicates a transmission completion interrupt of CAN module x 0 No Interrupt pending 1 Interrupt pending Write Bit Position Bit Name Note Function 6 CL_CxINT6 Clears the interrupt pending bit CxINT6 0 No change of CxINT6 bit 1 CxINT6 bit is cleared 0 5 CL_CxINT5 Clears the interrupt pending bit CxINT5 0 No change of CxINT5 bit 1 CxINT5 bit is cleared 0 4 CL_CxINT4 Clears the interru...

Page 413: ...e D2 3 When received message in standard format mode IDE 0 has less than 18 data bits the values of the not received bits are undefined Remark m 00 to 63 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address OffsetNote 1 Initial value M_IDHm IDE 0 0 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 012H m 20H undef 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M_IDLm ID15 ID14 ID13 ID12 ID11 ID10 I...

Page 414: ...ntifier standard or extended and the type of the frame remote or data frame are not respected In normal operation mode the message buffer is not han dled 5 If the message buffer is not assigned to a CAN module it can be used as temporary buffer of the application or by the CAN bridge ELISA Remark m 00 to 63 7 6 5 4 3 2 1 0 Address OffsetNote 1 Initial value M_CONFm 0 0 MT2 MT1 MT0 0 MA1 MA0 014H m...

Page 415: ...nsmit message buffer it indicates a remote frame reception In case auto answering RMDE0 bit of the M_CTRLm register is active the DN flag is cleared automatically after the answering data frame is sent 2 If the OVM bit of CxCTRL register is cleared 0 a message buffer assigned to the CAN module might be overwritten by new messages although the DN flag is already set x 1 to 3 Checking the MOVR bit o...

Page 416: ...3 16 Table 13 16 CAN Message Processing by TRQ and RDY Bits Message Type TRQ RDY Message Processing Any 0 Message buffer is disabled for any processing by the assigned CAN module Receive message 0 1 Message buffer is ready for reception 1 1 Request for sending a remote frame Transmit message 0 1 No processing of the transmit message 1 1 Request for message transmission ...

Page 417: ...te Initial value SC_STAT m 0 0 0 0 ST_ ERQ ST_ DN ST_ TRQ ST_ RDY 0 0 0 0 CL_ ERQ CL_ DN CL_ TRQ CL_ RDY 016H m 20H Bit Position Bit Name Function 11 3 ST_ERQ CL_ERQ Sets clears the ERQ bit of the M_STATm register 10 2 ST_DN CL_DN Sets clears the DN bit of the M_STATm register 9 1 ST_TRQ CL_TRQ Sets clears the TRQ bit of the M_STATm register 8 0 ST_RDY CL_RDY Sets clears the RDY bit of the M_STATm...

Page 418: ... m 00 to 63 7 6 5 4 3 2 1 0 Address OffsetNote Initial value M_DATAm0 D0_7 D0_6 D0_5 D0_4 D0_3 D0_2 D0_1 D0_0 008H m 20H undef M_DATAm1 D1_7 D1_6 D1_5 D1_4 D1_3 D1_2 D1_1 D1_0 009H m 20H undef M_DATAm2 D2_7 D2_6 D2_5 D2_4 D2_3 D2_2 D2_1 D2_0 00AH m 20H undef M_DATAm3 D3_7 D3_6 D3_5 D3_4 D3_3 D3_2 D3_1 D3_0 00BH m 20H undef M_DATAm4 D4_7 D4_6 D4_5 D4_4 D4_3 D4_2 D4_1 D4_0 00CH m 20H undef M_DATAm5 ...

Page 419: ... these bytes a time stamp value is sent x 1 to 3 refer to chapter 13 2 5 3 When a new message is received all data bytes are updated even if the data length code DLC in the M_DLCm register is less than 8 The values of the data bytes that have not been received may be change undefined Bit Position Bit Name Function 7 to 0 M_DATAm0 D0_7 to D0_0 Contents of the message data byte 0 first message data ...

Page 420: ...BASE address offset 2 RFU Reserved for future use Ensure to set these bits to 0 when writing to the M_DLCm register 3 If a DLC is specified to a value greater 8 for a transmit message 8 byte transfer is per formed regardless of the DLC value Remark m 00 to 63 7 6 5 4 3 2 1 0 Address OffsetNote 1 Initial value M_DLCm RFUNote 2 RFUNote 2 RFUNote 2 RFUNote 2 DLC3 DLC2 DLC1 DLC0 004H m 20H undef Bit P...

Page 421: ... is only valid for transmit messages and indicates how the DN flag is updated if a remote frame is received on that message buffer For details refer to chapter 13 2 8 Remote frame handling 6 RMED0 Specifies the remote frame handling mode 0 0 Auto answering of remote frame is not active 1 Auto answering of remote frame is active Remark The remote frame handling mode 0 is only valid for transmit mes...

Page 422: ...sages although the DN flag is already set Checking the MOVR bit additionally indicates whether the message buffer has been overwritten 2 R1 Reserved bit value of CAN bus bit r0 for receive message buffer 1 R0 Reserved bit value of CAN bus bit r1 for receive message buffer 0 RTR Specifies remote or data frame type of the message buffer 0 Message received or to be sent is a data frame 1 Message rece...

Page 423: ...he address of a message time stamp register is calculated according to the following formula effective address PP_BASE address offset Remarks 1 m 00 to 63 2 x 1 to 3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address OffsetNote Initial value M_TIMEm TS15 TS14 TS13 TS12 TS11 TS19 TS9 TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS0 006H m 20H undef Bit Position Bit Name Function 15 to 0 TS15 to TS0 16 bit time stamp...

Page 424: ...TR12 PTR11 PTR10 001H m 20H undef M_EVTm3 PTR37 PTR36 PTR35 PTR34 PTR33 PTR32 PTR31 PTR30 003H m 20H undef Bit Position Bit Name Function 7 to 0 M_EVTm0 PTR07 to PTR00 8 bit event pointer 0 for processing with the CAN bridge ELISA CAN bridge ELISA uses this pointer when receiving or sending a data frame in the message buffer m or from the message buffer m 7 to 0 M_EVTm1 PTR17 to PTR10 8 bit event ...

Page 425: ...eceived message 1 Do not check identifier type Remark When CMIDE is cleared 0 the specified identifier type standard or extended of the message buffer linked to this CAN mask register must match the identifier type of the received message in order to accept it for that message buffer 12 to 0 CxMASKHn 15 to 0 CxMASKLn CMID28 to CMID0 Sets the CAN module mask option for the corresponding identifier ...

Page 426: ...umber x 1 to 3 2 The register address is calculated according to the following formula effective address PP_BASE address offset SymbolNote Address OffsetNote 2 x 1 x 2 x 3 CxMASKL0 840H 880H 8C0H CxMASKH0 842H 882H 8C2H CxMASKL1 844H 884H 8C4H CxMASKH1 846H 886H 8C6H CxMASKL2 848H 888H 8C8H CxMASKH2 84AH 88AH 8CAH CxMASKL3 84CH 88CH 8CCH CxMASKH3 84EH 88EH 8CEH ...

Page 427: ...EVR DLEVT OVM TMR STOP SLEEP INIT 8D0H 0101H Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C1CTRL 0 ST_ DLEVT ST_ DLEVT ST_ OVM ST_ TMR ST_ STOP ST_ SLEEP ST_ INIT 0 CL_ DLEVR CL_ DLEVT CL_ OVM CL_ TMR CL_ STOP CL_ SLEEP CL_ INIT 850H C2CTRL 0 ST_ DLEVT ST_ DLEVT ST_ OVM ST_ TMR ST_ STOP ST_ SLEEP ST_ INIT 0 CL_ DLEVR CL_ DLEVT CL_ OVM CL_ TMR CL_ STOP CL_ SLEEP CL_ INIT 890H C3CTRL 0 ST_ DLEVT ST_ ...

Page 428: ...e transmission and reception error counters are cleared and any error status is reset 6 DLEVR Specifies the dominant level of the CAN receive input pin 0 Low level at the receive input is interpreted as a dominant bit 0 1 High level at the receive input is interpreted as a dominant bit 0 Remark From software point of view a dominant bit is always a 0 value 5 DLEVT Specifies the dominant level of t...

Page 429: ... the CPU 3 In case there is activity on the CAN bus and in parallel the SLEEP bit is set 1 the CAN module remains in normal operating mode and the SLEEP bit is cleared 0 automatically 4 The CAN sleep mode is released and normal operating mode is entered under the following conditions a CPU clears the SLEEP bit i e internal wake up by CPU b first dominant bit on the idle CAN bus i e external wake u...

Page 430: ...s of DLEVT bit 0 1 DLEVT bit is cleared 0 1 0 DLEVT bit is set 1 Others No change in DLEVT bit value ST_OVM CL_OVM Status of OVM bit 0 1 OVM bit is cleared 0 1 0 OVM bit is set 1 Others No change in OVM bit value ST_TMR CL_TMR Status of TMR bit 0 1 TMR bit is cleared 0 1 0 TMR bit is set 1 Others No change in TMR bit value ST_STOP CL_STOP Status of STOP bit 0 1 STOP bit is cleared 0 1 0 STOP bit i...

Page 431: ... MOM CL_ SSHT CL_ PBB CL_ BERR CL_ VALID CL_ WAKE CL_ OVR 892H C3DEF ST_ DGM ST_ MOM ST_ SSHT ST_ PBB 0 0 0 0 CL_ DGM CL_ MOM CL_ SSHT CL_ PBB CL_ BERR CL_ VALID CL_ WAKE CL_ OVR 8D2H Read 1 2 Bit Position Bit Name Function 7 DGM Specifies the storage of receive message in diagnostic mode 0 receive only and store valid message in message buffer type 7 1 receive only and store valid message as in n...

Page 432: ... it was caused by an error or a loss of arbitration 4 PBB Defines the priority by message buffer numbers 0 Transmission priority is given by message identifier 1 Transmission priority is given by the number of the message buffer Remark Normally the message identifier defines the transmission priority If the PBB flag is set the location of a message defines the priority the lower the message buffer...

Page 433: ...ID bit 0 No change of VALID bit 1 VALID bit is cleared 0 1 CL_WAKE Clears the WAKE bit 0 No change of WAKE bit 1 WAKE bit is cleared 0 0 CL_OVR Clears the OVR bit 0 No change of OVR bit 1 OVR bit is cleared 0 ST_DGM CL_DGM Status of DGM bit 0 1 DGM bit is cleared 0 1 0 DGM bit is set 1 Others No change in DGM bit value ST_MOM CL_MOM Status of MOM bit 0 1 MOM bit is cleared 0 1 0 MOM bit is set 1 O...

Page 434: ...ERR1 LERR0 LREC7 LREC6 LREC5 LREC4 LREC3 LREC2 LREC1 LREC0 894H 00FFH C3LAST 0 0 0 0 LERR3 LERR2 LERR1 LERR0 LREC7 LREC6 LREC5 LREC4 LREC3 LREC2 LREC1 LREC0 8D4H 00FFH Bit Position Bit Name Function 11 to 8 LERR3 to LERR0 Holds the code of the last CAN protocol error Remark The LERR3 to LERR0 bits cannot be cleared Thus these bits remain unchanged until the next error occurs 7 to 0 LREC7 to LREC0 ...

Page 435: ...ddress offset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address OffsetNote Initial value C1ERC REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 856H 00FFH C2ERC REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 896H 00FFH C3ERC REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 8D6H 00FFH Bit Position Bit Name Fu...

Page 436: ..._ E_INT5 ST_ E_INT4 ST_ E_INT3 ST_ E_INT2 ST_ E_INT1 ST_ E_INT0 0 CL_ E_INT6 CL_ E_INT5 CL_ E_INT4 CL_ E_INT3 CL_ E_INT2 CL_ E_INT1 CL_ E_INT0 858H C2IE 0 ST_ E_INT6 ST_ E_INT5 ST_ E_INT4 ST_ E_INT3 ST_ E_INT2 ST_ E_INT1 ST_ E_INT0 0 CL_ E_INT6 CL_ E_INT5 CL_ E_INT4 CL_ E_INT3 CL_ E_INT2 CL_ E_INT1 CL_ E_INT0 898H C3IE 0 ST_ E_INT6 ST_ E_INT5 ST_ E_INT4 ST_ E_INT3 ST_ E_INT2 ST_ E_INT1 ST_ E_INT0 ...

Page 437: ...bit is set 1 Others No change in E_INT6 bit value ST_E_INT5 CL_E_INT5 Status of E_INT5 bit 0 1 E_INT5 bit is cleared 0 1 0 E_INT5 bit is set 1 Others No change in E_INT5 bit value ST_E_INT4 CL_E_INT4 Status of E_INT4 bit 0 1 E_INT4 bit is cleared 0 1 0 E_INT4 bit is set 1 Others No change in E_INT4 bit value ST_E_INT3 CL_E_INT3 Status of E_INT3 bit 0 1 E_INT3 bit is cleared 0 1 0 E_INT3 bit is set...

Page 438: ...NO2 TMNO1 TMNO0 89AH 00FFH C3BA 0 0 0 CACT4 CACT3 CACT2 CACT1 CACT0 TMNO7 TMNO6 TMNO5 TMNO4 TMNO3 TMNO2 TMNO1 TMNO0 8DAH 00FFH Bit Position Bit Name Function 12 to 8 CACT4 to CACT0 Indicates the CAN module activity Remark The CACT4 to CACT0 bits reflect the status of the CAN protocol layer CACT4 CACT3 CACT2 CACT1 CACT0 CAN Module Activity 0 0 0 0 0 Reset state 0 0 0 0 1 Waiting for bus idle 0 0 0 ...

Page 439: ...ction 7 to 0 TMNO7 to TMNO0 Indicates the message buffer which is either waiting to be transmitted or in transmis sion progress TMNO7 to TMNO0 Number of Transmit Message Buffer 0 to 63 Current transmit message buffer waiting for trans mission or in transmission progress 64 to 254 Reserved not possible 255 No message waiting for transmission or in transmis sion progress ...

Page 440: ...ead CxBRP register at any time Caution In diagnostic mode the CxBRP register is hidden and the CxDINF register appears instead of it at the same address TLM 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address OffsetNote Initial value C1BRP TLM 0 0 0 0 0 0 0 0 BTYPE BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 85CH 0000H C2BRP TLM 0 0 0 0 0 0 0 0 BTYPE BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 89CH 0000H C3BRP TLM 0 0 0 0 0 0 0 ...

Page 441: ...TLM 1 BRP5 to BRP0 TLM 0 Specifies the bit rate prescaler for the CAN protocol layer TLM 0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Bit Rate Prescaler fBTL fMEM 2 k 1 k 0 0 0 0 0 0 fBTL fMEM 2 0 1 0 0 0 0 1 fBTL fMEM 4 1 0 0 0 0 1 0 fBTL fMEM 6 2 1 0 0 0 1 1 fBTL fMEM 8 3 0 0 0 1 0 0 fBTL fMEM 10 4 1 1 1 1 1 0 fBTL fMEM 126 62 1 1 1 1 1 1 fBTL fMEM 128 63 TLM 1 BRP7 BRP6 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Bit Rat...

Page 442: ...SEG2 by one or more TQ The total number of TQ for which the CAN module is permitted to lengthen or shorten the phase segments is called synchronisation jump width SJW The SJW value must be less or equal the difference of DBT and SPT which corresponds to PHASE_SEG2 and can be specified in the range of 1 TQ to 4 TQ For additional information on the CAN bus bit timing please refer to ISO 11898 The re...

Page 443: ...alue C1SYNC 0 0 0 SAMP SJW1 SJW0 SPT4 SPT3 SPT2 SPT1 SPT0 DBT4 DBT3 DBT2 DBT1 DBT0 85EH 0218H C2SYNC 0 0 0 SAMP SJW1 SJW0 SPT4 SPT3 SPT2 SPT1 SPT0 DBT4 DBT3 DBT2 DBT1 DBT0 89EH 0218H C3SYNC 0 0 0 SAMP SJW1 SJW0 SPT4 SPT3 SPT2 SPT1 SPT0 DBT4 DBT3 DBT2 DBT1 DBT0 8DEH 0218H Bit Position Bit Name Function 12 SAMP Specifies the bit sampling 0 Sample receive data one time at sampling point 1 Sample rece...

Page 444: ...le when the CAN module is set to INIT mode 3 For setting the DBT and SPT bits some rules must be observed otherwise the CAN module will malfunction for details refer to chapter 13 4 Bit Position Bit Name Function 4 to 0 DBT4 to DBT0 Specifies the number of TQ per bit DBT4 DBT3 DBT2 DBT1 DBT0 Data Bit Time DBT q 1 TQ q 0 0 0 0 0 Setting prohibited 0 0 1 0 1 0 0 1 1 1 8 TQ 7 0 1 0 0 0 9 TQ 8 0 1 0 0...

Page 445: ...knowledge delimiter It is automati cally reset whenever a SOF is detected on the CAN bus Caution In normal operating mode the CxDINF register is hidden and the corresponding CxBRP register appears instead of it at the same address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address OffsetNote Initial value C1DINF DINF15 DINF14 DINF13 DINF12 DINF11 DINF10 DINF9 DINF8 DINF7 DINF6 DINF5 DINF4 DINF3 DINF2 D...

Page 446: ...ich corre sponds to the DBT4 to DBT0 bits of the CxSYNC register 3 Rule for synchronization jump width SJW setting The number of TQ allowed for soft synchronization must not exceed the number of TQ for PHASE_SEG2 The length of PHASE_SEG2 is given by the difference of data bit time DBT and the sampling point position SPT Converted to register values the following condition applies Remark The time q...

Page 447: ...s baud rate is calculated The register descriptions show that the prescaler must be an even number between 2 and 128 the data bit time must be a value in the range 8 to 25 As the synchronization jump width SJW is defined as 3 TQ the maximum setting for the sampling point SPT can be only 3 TQ less than the setting for the data bit time DBT and also less than 17 TQ Based on the restrictions and assu...

Page 448: ...01111B 15 data bit time DBT 16 TQ SPT4 to SPT0 01100B 12 sampling point SPT 13 TQ or BRP5 to BRP0 000111B 7 prescaler BRP 16 TQ DBT4 to DBT0 01011B 11 data bit time DBT 12 TQ SPT4 t oSPT0 01000B 8 sampling point SPT 9 TQ 2 TLM 1 BRP7 to BRP0 00001011B 11 prescaler BRP 12 DBT4 to DBT0 01111B 15 data bit time DBT 16 TQ SPT4 to SPT0 01100B 12 sampling point SPT 13 TQ or BRP7 to BRP0 00001111B 15 pres...

Page 449: ...CPU by sequential accesses to the CAN message buffers the following sequence has to be observed Figure 13 44 Sequential CAN Data Read by CPU As the DN flag is only set by the CAN module and cleared by the CPU only it is ensured that the CPU can recognize that new data is stored in the message buffer during the read operation Remark If the CPU reads the data by only one read access the data consist...

Page 450: ...the message is automatically started whenever the data length code from the M_DLCm register is read by the CPU and the data is copied from the message buffer into the temporary buffer As long as the CPU reads 16 bit data from consecutive addresses that means 16 bit burst read sequence M_DLCm M_CTRLm M_TIMEm M_DATAm0 m1 M_DATAm2 m3 M_DATAm4 m5 M_DATAm6 m7 M_IDLm M_IDHm the data is read from the tem...

Page 451: ...k x 1 to 3 PowerOn RESET or RESET CxCTRL ISTAT 1 INIT 0 CxCTRL ISTAT 0 INIT 1 and CAN bus busy CAN bus idle SLEEP 1and CANbusbusy CxCTRL ISTAT 0 CxCTRL SLEEP 1 CxCTRL STOP 0 SLEEP 0 CxCTRL ISTAT 1 CxCTRL SLEEP 1 CxCTRL STOP 1 STOP 1 PowerOffor RESET PowerOffor RESET STOP 0 Detectionofbus transition Power Off or RESET CANbusbusy PowerOffor RESET INIT 1and CAN bus idle SLEEP 1and CANbusidle WAKE 1 I...

Page 452: ... CAN interface Before any operation on the CAN memory can be done it is essential that the common control reg ister are initialised The general initialisation sequence is shown in Figure 13 46 Figure 13 46 General Initialisation Sequence for the CAN Interface Remark Enabling the global operation does not automatically enable any CAN module Each CAN module must be initialised and enabled separately...

Page 453: ...t void unsigned char i CGST 0x00FF clear all flags of CGST CGIE 0x00FF disable global interrupts CGCS 0x0000 define internal clock CGTSC 0x0000 clear CAN global time system counter CGTEN 0x0000 disable all timer events for i 0 i CAN_MESSAGES i CAN_ClearMessage i clear all message buffers CGST 0x0100 set GOM bit return 0 ...

Page 454: ...a CAN Module Each CAN module must be initialised by the sequence according to Figure 13 47 Figure 13 47 Initialisation Sequence for a CAN module Remark x 1 to 3 INIT CAN MODULE Init the module registers CxCTRL but do not clear the INIT flag CxDEF CxIE CxBRP CxSYNC Define Masks Clear INIT flag register CxCTRL END ...

Page 455: ...xCTRL 0x00FE clear CxCTRL except INIT can_mod_ptr CxDEF 0x00FF clear CxDEF can_mod_ptr CxIE 0x00FF clear CxIE can_mod_ptr CxBRP brp_value set CxBRP can_mod_ptr CxSYNC sync_value set CxSYNC can_mod_ptr mask0_low 0x0000 clear mask0 can_mod_ptr mask0_high 0x0000 can_mod_ptr mask1_low 0x0000 clear mask1 can_mod_ptr mask1_high 0x0000 can_mod_ptr mask2_low 0x0000 clear mask2 can_mod_ptr mask2_high 0x000...

Page 456: ...sation State Note In case of permanent bus activity the program loops for a long time Therefore a timeout mech anism should be provided in order to limit the runtime of the routine Remark x 1 to 3 Example for C routine Yes No Note Normal Operation Set INIT flag register CxCTRL Read ISTAT flag register CxCTRL ISTAT set INIT Mode int CAN_ModuleStop unsigned char module_no can_module_type can_mod_ptr...

Page 457: ...not observed any active CAN module may cause malfunction on the corresponding CAN bus 1 For each CAN module x x 1 to 3 a Enter sleep mode Set SLEEP bit 1 CxCTRL register or b Enter initialisation mode Set INIT bit 1 CxCTRL register and wait for ISTAT bit 1 2 Disable event processing Clear EVM flag CGST register 3 Stop the CAN global time system counter Clear the TSM flag CGST register 4 Stop the g...

Page 458: ...mber to the higher command number The event pointers refer to chapter 13 3 4 9 Message event registers m0 m1 and m3 M_EVTm0 M_EVTm1 M_EVTm3 m 00 to 63 link a message object to the start of a command sequence to be executed if an event occurs ELISA continuously checks the event request flag ERQ of all message buffers M_STATm register m 00 to 63 Whenever the ERQ flag of a particular message buffer i...

Page 459: ... events The lower the message number the higher the priority of the message event The lowest priority is given to the script event The script event is only executed if no other event is pending If several timer events are waiting to be processed at the same time the pending timer event with the lowest number is processed first ELISA MAIN any timer event pending any msg event pending any script eve...

Page 460: ...rmination of a command list M_EVTm3 is cleared In case of a command execution error M_EVTm3 contains the number of the command that led to the erroneous execution At the beginning of processing a command list ELISA adds the value of M_EVTm3 to the value of M_EVTm0 That technique allows the user to design a convenient error recovery procedure For example In an application where the full execution o...

Page 461: ...UM00 Figure 13 51 End of Event Processing End Event Processing Clear internal ERQ flag message event Clear ERQ flag of message temporary message event temporary pointer Source modified Write ELISA source buffer to Message Buffer ELISA MAIN yes yes no no new source loaded yes no ...

Page 462: ...is set ELISA ends the processing by saving the data writing 0 to M_EVTm3 and clearing the ERQ flag of the message M_EVTm3 is basically desired for error recovery but it can also be used by the application for special conditions Whenever an error occurs ELISA does not write back a 0 to M_EVTm3 but the offset of the command that caused the error If for example the second command in the figure above ...

Page 463: ... recovery then Cautions 1 Any violation of this rule could cause data inconsistency 2 Never modify by CPU any message with ERQ flag set 1 while ELISA is in opera tion EER flag 0 4 Syntax check of commands There is no syntax check implemented in ELISA that takes care that temporary sums and counters are not mixed that copy commands especially bit string copy parameters are within the valid range Th...

Page 464: ...quired or if a temporary sum is calculated a 64 bit temporary buffer is available within ELISA The 64 bit can either be used as 8 bit counters or as temporary 16 bit sums The table below shows how the 64 bit temporary buffer can be split Table 13 18 Format of 64 bit Temporary Buffer The counters can be set or decremented by certain commands If a decrement command is exe cuted on a counter already ...

Page 465: ... After executing 8 consecutive commands without any END flag set the execution module automatically stops the execution First imple mentations only 30 EHDL Error Handling 0 On error store source message and command number back to message buffer 1 On error do not store anything back to message buffer Remark If an error occurs during the event processing of ELISA the EHDL bit defines how ELISA stops...

Page 466: ...yte location is 4 Formula for start byte and start bit byte BIT_POS div 8 byte offset for 5 bit value bit BIT_POS modulo 8 Example 1 BIT_POS is set to 43 as 6 bit value BIT_POS div 8 43 div 8 5 byte location BIT_POS modulo 8 3 bit location bit bit string is located at data byte 5 bit 3 Example 2 BIT_POS is set to 16 as 5 bit value for a command that targets bytes 4 7 byte offset 4 command targets ...

Page 467: ...n also generate a script event c Data Consistency As ELISA accesses the message buffers as well as the CPU and the CAN interfaces some mecha nisms were implemented to ensure that data inconsistency is detected To reduce the risk of data inconsistency the application software should not operate any message with the ERQ flag set without ensuring that ELISA is not handling that message The CPU can en...

Page 468: ...eserved for future implementations 0FH 10H write source data to destination data bytes 0 3 WR_DLO DEST PAR 11H write source data to destination data bytes 4 7 WR_DHI DEST PAR 12H copy all source data to destination including DLC WR_DALL DEST PAR 13H write source bit string to destination bit string data bytes 0 3 WR_DBLO DEST PAR 14H write source bit string to destination bit string data bytes 4 7...

Page 469: ...T0 Destination 0 to 255 Number of new source message PAR0 Parameter 0 Do not handle old source 1 Write old source to message buffer Command Set Script Event Code 02H Mnemonic SET_EVT DEST 0 DEST7 to DEST0 Destination 0 to 255 Pointer to first command for script event processing Command Generate Interrupt and Stop Operation Code 03H Mnemonic BREAK 0 0 Remark If the command is executed ELISA generat...

Page 470: ...T2 to DEST0 Destination 0 to 7 Number of counter PAR7 to PAR0 Parameter 0 to 255 Value written to counter Command Decrement Counter and Update CFLG Flag Code 09H Mnemonic DECR_CNT DEST 0 Effect of the DECR_CNT command is as follows DEST2 to DEST0 Destination 0 to 7 number of counter Counter Value Before Executing Command Counter Value After Executing Command CFLG at End of Com mand 0 0 0 1 0 1 n 2...

Page 471: ...ate CFLG Flag Code 0AH Mnemonic TST_BIT DEST PAR Remark The test bit number is set as described in 13 5 2 3 Bit location definition for bit commands DEST5 to DEST0 Destination 0 to 63 Number of source data bit to be tested PAR0 Parameter 0 Test for 0 1 Test for 1 Status of Test Bit CFLG at End of Command 0 0 1 1 Status of Test Bit CFLG at End of Command 0 0 1 1 ...

Page 472: ... as if the CPU sets any bit of the M_STATm register PAR7 to PAR0 Parameter Lower Byte 0 to 255 Bit clear parameter for M_STATm Remark The parameter has the same format as if the CPU clears any bit of the M_STATm register Command Add Value of Source Byte to Temporary Sum Code 0DH Mnemonic ADD_SUM DEST PAR DEST2 DEST1 Destination 0 to 3 Number of temporary sum PAR6 to PAR4 Parameter 0 to 7 Number of...

Page 473: ...Number of source data byte to be copied to destination data byte 1 8 Copy source time stamp byte 0 to destination data byte 1 9 Copy source time stamp byte 1 to destination data byte 1 10 to 14 Setting prohibited 15 Do not copy any data to destination data byte 1 PAR7 to PAR4 Parameter for Destination Data Byte 2 0 to 7 Number of source data byte to be copied to destination data byte 2 8 Copy sour...

Page 474: ...Number of source data byte to be copied to destination data byte 5 8 Copy source time stamp byte 0 to destination data byte 5 9 Copy source time stamp byte 5 to destination data byte 5 10 to 14 Setting prohibited 15 Do not copy any data to destination data byte 5 PAR7 to PAR4 Parameter for Destination Data Byte 6 0 to 7 Number of source data byte to be copied to destination data byte 6 8 Copy sour...

Page 475: ...opy all data including source identifier to destination Command Write Source Data to Destination Bit string Data Bytes 0 to 3 Code 13H Mnemonic WR_DBLO DEST PAR DEST7 to DEST0 Destination 0 to 255 Number of message buffer the command uses as target PAR14 to PAR10 Parameter for Start Position in Source 0 to 31 Start position bit number of bit string in source PAR9 to PAR5 Parameter for Bit string L...

Page 476: ...stination 0 to 255 Number of message buffer the command uses as target PAR14 to PAR10 Parameter for Start Position in Source 0 to 31 Start position bit number of bit string in source PAR9 to PAR5 Parameter for Bit string Length 0 to 31 Length of bit string in bits decremented by 1 Remark A value of 0 means a length of 1 a value of 1 a length of 2 etc PAR4 to PAR0 Parameter for Start Position in De...

Page 477: ... 8 to 14 Setting prohibited 15 Do not copy the destination data byte PAR11 to PAR8 Parameter for Destination Data Byte 1 0 to 7 Number of destination data byte to be copied to source data byte 1 8 to 14 Setting prohibited 15 Do not copy the destination data byte PAR7 to PAR4 Parameter for Destination Data Byte 2 0 to 7 Number of destination data byte to be copied to source data byte 2 8 to 14 Sett...

Page 478: ...umber of destination data byte to be copied to source data byte 5 8 to 14 Setting prohibited 15 Do not copy the destination data byte PAR7 to PAR4 Parameter for Destination Data Byte 6 0 to 7 Number of destination data byte to be copied to source data byte 6 8 to 14 Setting prohibited 15 Do not copy the destination data byte PAR3 to PAR0 Parameter for Destination Data Byte 7 0 to 7 Number of desti...

Page 479: ... decremented by 1 Remark A value of 0 means a length of 1 a value of 1 a length of 2 etc PAR4 to PAR0 Parameter for Start Position in Destination 0 to 7 Start position bit number of bit string in destination byte 0 to 3 Command Get Source Bit string from Destination Bit string Data Bytes 4 to 7 Code 1CH Mnemonic LD_DBHI DEST PAR DEST7 to DEST0 Destination 0 to 255 Number of message buffer the comm...

Page 480: ...r Registers 0 1 and 3 TEP0 TEP1 TEP3 Note The address of an interrupt pending register is calculated according to the following formula effective address PP_BASE address offset 7 6 5 4 3 2 1 0 Address OffsetNote Initial value TEP0 TEP07 TEP06 TEP05 TEP04 TEP03 TEP02 TEP01 TEP00 910H 0000H TEP1 TEP17 TEP16 TEP15 TEP14 TEP13 TEP12 TEP11 TEP10 911H 0000H TEP3 TEP37 TEP36 TEP35 TEP34 TEP33 TEP32 TEP31...

Page 481: ...t 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address OffsetNote Initial value SEPCC CMDC7 CMDC6 CMDC5 CMDC4 CMDC3 CMDC2 CMDC1 CMDC0 SEP7 SEP6 SEP5 SEP4 SEP3 SEP2 SEP1 SEP0 914H 0000H Bit Position Bit Name Function 15 to 8 CMDC7 to CMDC0 Pointer on command list for script event Remark The CMDC7 to CMDC0 bits show the offset number of the command executed last If an error condition occurs the offset valu...

Page 482: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address OffsetNote Initial value EEPS EERC7 EERC6 EERC5 EERC4 EERC3 EERC2 EERC1 EERC0 EPS7 EPS6 EPS5 EPS4 EPS3 EPS2 EPS1 EPS0 916H 00FFH Bit Position Bit Name Function 15 to 8 EERC7 to EERC0 Indicates the ELISA error code Remark The EERC7 to EERC0 bits are read only 7 to 0 EPS7 to EPS0 Indicates the event processing source EERC7 to EERC0 ELISA Error Code 0 No ...

Page 483: ...DECR_CNT or TST_BIT command does meet the criterion to set conditional execution Remarks 1 The execution of commands other than DECR_CNT or TST_BIT does always clear the CFLG bit 2 The value of CFLG bit does only influence the execution of the com mand which is executed directly after the DECR_CNT command or TST_BIT command and for which conditional execution is set by the COND bit 6 TBS Selects t...

Page 484: ...ing Write Bit Position Bit Name Function 14 6 ST_TBS CL_TBS Sets clears the TBS bit 5 CL_ERR Clears the ERR flag 0 No change of ERR flag 1 ERR flag is cleared 0 4 CL_PSE Clears the PSE flag 0 No change of PSE flag 1 PSE flag is cleared 0 3 CL_PTE3 Clears the PTE3 flag 0 No change of PTE3 flag 1 PTE3 flag is cleared 0 2 CL_PTE2 Clears the PTE2 flag 0 No change of PTE2 flag 1 PTE2 flag is cleared 0 ...

Page 485: ...ess PP_BASE address offset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address OffsetNote Initial value ELC ELC15 ELC14 ELC13 ELC12 ELC11 ELC10 ELC9 ELC8 ELC7 ELC6 ELC5 ELC4 ELC3 ELC2 ELC1 ELC0 91AH 0000H Bit Position Bit Name Function 15 to 0 ELC15 to ELC0 Indicates the last processed command by ELISA Remark The ELC shows only the upper 16 bit of the command processed last END EHDL COND CMD4 to CMD0 an...

Page 486: ...TB18 ETB17 ETB16 91EH 0000H when TBS 0 Bit Position Bit Name Function 15 to 8 ETBH ETB31 to ETB24 These bits reflect either the counter 3 or the upper byte of temporary sum 1 7 to 0 ETBH ETB23 to ETB16 These bits reflect either the counter 2 or the lower byte of temporary sum 1 15 to 8 ETBL ETB15 to ETB8 These bits reflect either the counter 1 or the upper byte of temporary sum 0 7 to 0 ETBL ETB7 ...

Page 487: ...solution on chip A D converter Analog inputs 12 channels Separate on chip A D conversion result registers for each analog input 10 bits 12 registers A D conversion trigger modes A D trigger mode A D trigger polling mode Timer trigger mode Successive approximation technique Voltage detection mode ...

Page 488: ...s the output value of the D A converter for comparing with an analog input voltage value When an A D conversion terminates the current contents of the SAR conversion result are stored in an A D conversion result register ADCRm m 0 to 11 When all specified A D conversions terminate there also is an A D conversion termination interrupt INTAD 6 A D conversion result registers n ADCRn n 0 to 11 ADCRn ...

Page 489: ... not using the AVREF pin connect it to AVDD or AVSS Note Note When connecting the AVREF pin to AVSS the power consumption will be reduced 10 AVSS pin The AVSS pin is the ground voltage pin of the A D converter Even if not using A D converter always ensure that this pin has the same DC potential as the VSS5 pin 11 AVDD pin The AVDD pin is the analog power supply pin of A D converter Even if not usi...

Page 490: ...ecutive times and use conversion results with the exception of any abnormal conversion results that are obtained If an A D conversion result from which it is judged that an abnormality occurred in the system is obtained do not perform abnormality processing at once but perform it upon reconfirming the occurrence of an abnormality 2 Be sure that voltages outside the range AVSS to AVREF are not appl...

Page 491: ...2 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value ADSCM0 CE CS 0 MS PLM TRG2 TRG1 TRG0 SANI3 SANI2 SANI1 SANI0 ANIS3 ANIS2 ANIS1 ANIS0 FFFFF200H 0000H Bit position Bit name Function 15 CE Specifies enabling or disabling A D conversion 0 Disable 1 Enable 14 CS Shows status of A D converter This bit is read only 0 Stopped 1 Operating 12 MS Specifies operation mode of A D converter 0 Scan mode 1 Sele...

Page 492: ...number that is set by bits ANIS3 ANIS0 3 to 0 ANIS3 to ANIS0 ANIS3 to ANIS0 specifies the analog input pin in select mode In scan mode it specifies the last analog input pin for which a conversion is issued The range of consecutive conversions is defined by the setting of SANI3 to SANI0 and ANIS3 to ANIS0 which lead to a number of conversions defined by n ANIS3 to ANIS0 SANI3 to SANI0 1 ANIS3 ANIS...

Page 493: ...onversion within 5 µs after post stabilization time the analog circuit turns in low power mode again Writing CE bit must be delayed 5 µs to prevent the analog circuit from illegal action In select poll ing mode stabilization time is required for first conversion only Conversion request during post stabilization time is valid but result can not be guaran teed Remark Power saving functions are only ...

Page 494: ...sion speed and accuracy However the settings modifying the compare time TCMPAD must keep the following relation The conversion time results by the addition of the sample time TSMPAD and the compare time TCMPAD Example Provided that fCPU 16 MHz TSMPAD 2 TSTAGE 10 fCPU The compare time has to be set to Therefore the setting of bits FR2 to FR0 010B will be chosen The sampling time is By this the conv...

Page 495: ...AD of 8 system clocks has to be considered Thus the total time of A D conversion TTOTAL including the trigger setup time is as follows Select mode Scan mode Example Provided that fCPU 16 MHz TSMPAD 2 TSTAGE 10 fCPU N 8 Scan mode is selected The total A D conversion time becomes TTRGAD 8 fCPU TTOTAL TTRGAD TCONV TTOTAL NCHANNEL TTRGAD TCONV NCHANNEL Number of channels to scan TTOTAL NCHANNEL TTRGAD...

Page 496: ...ADETM DETEN DETLH DET ANI3 DET ANI2 DET ANI1 DET ANI0 DET CMP9 DET CMP8 DET CMP7 DET CMP6 DET CMP5 DET CMP4 DET CMP3 DET CMP2 DET CMP1 DET CMP0 FFFFF204H 0000H Bit position Bit name Function 15 DETEN Specifies voltage detection mode 0 Operate in normal mode 1 Operate in voltage detection mode 14 DETLH Sets voltage comparison detection 0 Generate INTDET interrupt if reference voltage value analog i...

Page 497: ...re valid and the upper 6 bits always read 0 Figure 14 5 A D Conversion Result Registers 0 to 11 ADCR0 to ADCR11 Table 14 1 Correspondence between ADCRm m 0 to 11 Register Names and Addresses 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value ADCRm 0 0 0 0 0 0 ADCRm9 ADCRm8 ADCRm7 ADCRm6 ADCRm5 ADCRm4 ADCRm3 ADCRm2 ADCRm1 ADCRm0 see Table 14 1 0000H Register name Address ADCR0 FFFFF210H AD...

Page 498: ... analog input voltage and A D conversion results Figure 14 6 Relationship Between Analog Input Voltages and A D Conversion Results Remark m 0 to 11 Analog Input Pin A D Conversion Result Register ANI0 ADCR0 ANI1 ADCR1 ANI2 ADCR2 ANI3 ADCR3 ANI4 ADCR4 ANI5 ADCR5 ANI6 ADCR6 ANI7 ADCR7 ANI8 ADCR8 ANI9 ADCR9 ANI10 ADCR10 ANI11 ADCR11 1023 1022 1021 3 2 1 0 Input voltage AVREF 1 2048 1 1024 3 2048 2 10...

Page 499: ...nabled status an A D conversion termination interrupt is generated when a specified number of A D conversions have terminated 2 Voltage detection interrupt INTDET In voltage detection mode DETEN bit of ADETM register 1 the value of the ADCRm register of the relevant analog input pin is compared to the reference voltage set in the DETCMP 9 0 bits of the ADETM register and a voltage detection interr...

Page 500: ...nverter 3 When the 10 bit comparison terminates the conversion result is started in the ADCRm register When the specified number of A D conversions have terminated an A D conversion termination interrupt INTAD is generated Notes 1 If the contents of the ADSCM0 register are changed during A D conversion operation the A D conversion operation preceding the change stops and a conversion result is not...

Page 501: ...he conversion timing for the analog input s ANIm To restart the AD conversion after the INTAD interrupt conversion finished CS 0 the CE bit has to be set again to engage the next conversion b A D trigger polling mode In this mode the A D conversion is started by setting the CE bit of the register ADSCM0 This starts the conversion timing for the analog input s ANIm A restart the AD conversion after...

Page 502: ...NIm m 0 to 11 Figure 14 7 Example of Select Mode Operation Timing ANI1 ANI1 Input A D conversion Data 1 ANI1 Data 2 ANI1 Data 3 ANI1 Data 4 ANI1 Data 5 Data 6 ANI1 Data 7 ANI1 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 1 ANI1 Data 2 ANI1 Data 3 ANI1 Data 4 ANI1 Data 6 ANI1 ADCR1 register INTAD interrupt Conversion start ADSCM0 register setting CE bit set CE bit set CE bit set CE bit set...

Page 503: ... there is an A D conversion termination interrupt INTAD Figure 14 8 Example of Scan Mode Operation Timing 4 Channel Scan ANI0 to ANI3 ANI0 Input ANI1 Input ANI2 Input ANI3 Input A D conversion Data 1 ANI0 Data 2 ANI1 Data 3 ANI2 Data 4 ANI3 Data 5 ANI0 Data 6 ANI1 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 1 ANI0 ADCR0 Data 2 ANI1 ADCR1 Data 3 ANI2 ADCR2 Data 4 ANI3 ADCR3 Data 5 ANI0 ADCR0 ADC...

Page 504: ...11 An A D conversion termination interrupt INTAD is generated for each A D conversion termination CS bit 0 To restart A D conversion set the CE bit of the ADSCM0 register This is optimal for an application that reads a result for each A D conversion Remark m 0 to 11 Figure 14 9 Example of Select Mode A D Trigger Select Operation ANI2 Analog input A D conversion result register ANIm ADCRm ANI0 ANI1...

Page 505: ...s is optimal for an application that regularly monitors multiple analog inputs Notes 1 n SANI 3 0 0 to 10 2 m ANIS 3 0 1 to 11 Caution Always set SANI 3 0 ANIS 3 0 Exception When bits SANI 3 0 ANIS 3 0 0 just the analog input ANI0 is scanned Figure 14 10 Example of Scan Mode A D Trigger Scan Operation ANI2 ANI5 Analog input A D conversion result register ANInNote 1 ADCRn ANImNote 2 ADCRm ANI0 ANI1...

Page 506: ...rrespond one to one with ADCRm register An A D conversion termination interrupt INTAD is generated for each A D conversion termination A D conversion operation is repeated until the CE bit 0 CS bit 1 In A D trigger polling mode it is not necessary to set the CE bit of the ADSCM0 register to restart the A D conversion operation Note This is optimal for applications that regularly read A D conversio...

Page 507: ... regularly read A D conversion values Notes 1 n SANI 3 0 0 to 10 2 m ANIS 3 0 1 to 11 3 If the ADCRm register is not read before the next A D conversion has been finished its contents is overwritten Caution Always set SANI 3 0 ANIS 3 0 Exception When bits SANI 3 0 ANIS 3 0 0 just the analog input ANI0 is scanned Figure 14 12 Example of Scan Mode A D Trigger Polling Scan Operation ANI2 to ANI5 Anal...

Page 508: ...ode Taking the interrupt signal as a trigger one analog input at a time is A D converted and the result is stored in one ADCRm register An A D conversion termination interrupt INTAD is generated for each A D conversion which terminates A D conversion CS 0 After A D conversion termination the A D converter changes to trigger wait status CE 1 It per forms A D conversion operation again when the inte...

Page 509: ... the conversion start analog input pin through the conversion termination analog input pin specified by the ADSCM0 register are sequentially selected and A D converted Analog inputs correspond one to one with ADCRm register When all of the specified A D conversions have terminated an A D conversion termination interrupt INTAD is generated CS 0 After all of the specified A D conversions have termin...

Page 510: ...CR1 ADCR2 ADCR3 ADCR4 ADCR5 ADCR11 A D converter 1 CE bit of ADSCM0 1 Enabled 2 INTPE10 TINTCCE10 interrupt generation 3 A D conversion of ANI1 4 Store conversion result in ADCR1 5 A D conversion of ANI2 6 Store conversion result in ADCR2 7 A D conversion of ANI3 8 Store conversion result in ADCR3 9 A D conversion of ANI4 10 Store conversion result in ADCR4 11 INTAD interrupt generation ANI11 INTP...

Page 511: ...tion that trigger input is ignored If conversion operation is suspended a conversion result is not stored in the ADCRm register m 0 to 11 3 When interval conversion time If a timer trigger is input at the same time when the conversion terminates interrupt generation and ADCRm register storage of the actual value are performed correctly 14 9 4 Operation in standby modes 1 HALT mode The A D converte...

Page 512: ...512 Preliminary User s Manual U14913EE1V0UM00 MEMO ...

Page 513: ...put output ports PAH7 S0 to PAH0 S7 PAL15 S8 to PAL0 S23 and PCS2 S24 to PCS4 S26 and PCT0 S27 to PCT4 S31 and PCM0 S32 to PCM1 S33 and P60 S34 to P65 S39 are bitwise switchable 5 The operation with the subsystem clock is not available Table 15 1 Maximum Number of Display Pixels 15 2 LCD Controller Driver Configuration The LCD controller driver consists of the following hardware Table 15 2 LCD Con...

Page 514: ...rcuit Block Diagram Remark fLCD LCD clock frequency Display Data Memory Segment Data Selector Segment Driver Timing Controller Common Driver S0 S20 S39 S10 S30 COM0 COM1 COM2 COM3 LCD Drive Voltage Generator VLCD0 Selector fLCD Prescaler VLCD1 VLCD2 fCKSEL1 Prescaler fLCD 2 9 fLCD 2 8 fLCD 2 fLCD Selector LCDC1 LCDC0 2 LCD display mode register Internal bus 7 6 2 fSUB 2 7 fLCD ...

Page 515: ...be output from the segment pin according to the contents of the display data memory ECOM Common enable signal 0 Common disable 1 Common enable This bit is used for common enabling Before starting LCD make sure to set bit to 1 And in case application requires low power this bit should be disabled ASTOP Driving power supply 0 All analog macro is working 1 LEPSB being used for STOP signal for analog ...

Page 516: ...de before enabling LCD segment mode Remark n 0 to 15 7 6 5 4 3 2 1 0 Address At Reset LSEG0 SEGE7 SEGE6 SEGE5 SEGE4 SEGE3 SEGE2 SEGE1 SEGE0 FFFFF700H 00H 7 6 5 4 3 2 1 0 Address At Reset LSEG1 SEGE15 SEGE14 SEGE13 SEGE12 SEGE11 SEGE10 SEGE9 SEGE8 FFFFF702H 00H 7 6 5 4 3 2 1 0 Address At Reset LSEG2 SEGE23 SEGE22 SEGE21 SEGE20 SEGE19 SEGE18 SEGE17 SEGE16 FFFFF704H 00H 7 6 5 4 3 2 1 0 Address At Res...

Page 517: ...d to Com2 Com3 will be used Address Register Description Name Type 1bit 8bit 16bit Reset 3FFF720 LCD segment register00 SEGREG00 R W Y Y Y 0000H 22 LCD segment register10 SEGREG10 R W Y Y Y 0000H 24 LCD segment register20 SEGREG20 R W Y Y Y 0000H 26 LCD segment register30 SEGREG30 R W Y Y Y 0000H 3FFF730 LCD segment register01 SEGREG01 R W Y Y Y 0000H 32 LCD segment register11 SEGREG11 R W Y Y Y 0...

Page 518: ...of the bit is 1 it is converted to the selection voltage If the value of the bit is 0 it is converted to the non selection voltage and output to a segment pin S0 to S39 S39 to S0 have an alternate function as input output port pins Consequently it is necessary to check what combination of front surface electrodes corresponding to the segment signals and rear surface electrodes corresponding to the...

Page 519: ...Phases on page 519 shows the common signal and segment signal voltages and phases Figure 15 5 Common Signal Waveform T One LCD clock cycle TF Frame frequency Figure 15 6 Common Signal and Segment Signal Voltages and Phases T One LCD clock cycle TF 4 x T COMn Divided by 4 VLC0 VSS VLCD VLC1 VLC2 Selected Not selected Common signal Segment signal VLC0 VSS VLCD VLC0 VSS VLCD T T VLC2 VLC2 VLC1 VLC1 ...

Page 520: ...The µPD703123 Subseries have a split resistor to create an LCD drive voltage and the drive voltage is fixed to 1 3 bias To supply various LCD drive voltages internal VDD or external VLCD supply voltage can be selected Table 15 7 Drive Voltage Supply Bias Method 1 3 Bias Method LCD Drive Voltage VLC0 VLC0 VLC1 2 3 VLC0 VLC2 1 3 VLC0 ...

Page 521: ... source according to Drive Voltage Supply on page 520 By using variable resistors r1 and r2 a non stepwise LCD drive voltage can be supplied Figure 15 7 Example of Connection of LCD Drive Power Supply a To supply LCD drive voltage from VDD b To supply LCD drive voltage from external source VDD2 VSS P ch LIPS 1 VSS VLC2 VLC1 VLC0 R R R R R R VDD2 VSS P ch LIPS 0 VSS VLC2 VLC1 VLC0 R R R R R R VDD r...

Page 522: ...s must be output to pins S8 and S9 as shown in Table 15 8 at the COM0 to COM3 common signal timings Table 15 8 Selection and Non Selection Voltages COM0 to COM3 S Selection NS Non selection From this it can be seen that 0101 must be prepared in the display data memory address H corresponding to S8 Examples of the LCD drive waveforms between S8 and the COM0 and COM1 signals are shown in Fig ure 15 ...

Page 523: ...M2 COM1 COM0 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 0 0 0 1 1 1 0 1 1 1 0 1 1 1 0 1 0 1 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 0 Data memory address LCD panel 1 0 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 1 1 0 0xFFFFF726 0xFFFFF724 0xFFFFF722 0xFFFFF720 0xFFFFF736 0xFFFFF734 0xFFFFF732 0xFFFFF730 ...

Page 524: ...UM00 Figure 15 10 4 Time Division LCD Drive Waveform Examples 1 3 Bias Method TF VLC0 VLC2 COM0 VLCD 0 COM0 to S8 VLCD VLC1 1 3VLCD 1 3VLCD VSS VLC0 VLC2 COM1 VLC1 VSS VLC0 VLC2 COM2 VLC1 VSS VLC0 VLC2 COM3 VLC1 VSS VLCD 0 COM1 to S8 VLCD 1 3VLCD 1 3VLCD VLC0 VLC2 S8 VLC1 VSS ...

Page 525: ...minary User s Manual U14913EE1V0UM00 Chapter 16 Port Functions 16 1 Features Input Output ports 90 Ports alternate as input output pins of other peripheral functions Input or output can be specified in bit units ...

Page 526: ...put output ports named ports P1 through P6 and PAL PAH PDL PCS PCT and PCM The configuration is shown below Port 1 P10 to P17 Port 2 P20 to P27 Port 3 to P35 P30 Port 4 P40 to P45 Port 5 P50 to P55 Port 6 P60 to P65 Port AL Port AH PAL0 to PAL15 PAH0 to PAH7 Port DL Port CS Port CT Port CM PDL0 to PDL15 PCS2 to PCS4 PCT0 PCT4 PCM0 to PCM1 ...

Page 527: ...it RPU input output External interrupt input A Port 4 P40 to P45 6 bit input output Real time pulse unit RPU input output External interrupt input A Port 5 P50 to P55 6 bit input output Real time pulse unit RPU input output External interrupt input A Port 6 P60 to P65 6 bit input output Serial interface input output UART2 External interrupt input External CAN clock B Port AL PAL0 to PAH15 16 bit i...

Page 528: ...P23 Input mode P24 SO1 P24 Input mode P25 SCK1 P25 Input mode P26 RXD0 P26 Input mode P27 TXD0 P27 Input mode Port 3 P30 TIE0 INTPE00 P30 Input mode PMC3 P31 TOE10 INTPE10 P31 Input mode P32 TOE20 INTPE20 P32 Input mode P33 TOE30 INTPE30 P33 Input mode P34 TOE40 INTPE40 P34 Input mode P35 TCLRE0 INTPE50 P35 Input mode Port 4 P40 TIE1 INTPE01 P40 Input mode PMC4 P41 TOE11 INTPE11 P41 Input mode P42...

Page 529: ...G39 P65 Input mode Port CM PCM0 WAIT SEG32 PCM0 Input mode PMCCM PCM1 CLKOUT SEG33 PCM1 Input mode Port CT PCT0 LWR SEG27 PCT0 Input mode PMCCT PCT1 UWR SEG28 PCT1 Input mode PCT2 SEG29 PCT2 Input mode PCT3 SEG30 PCT3 Input mode PCT4 RD SEG31 PCT4 Input mode Port CS PCS2 CS2 SEG24 to PCS4 CS4 SEG26 PCS2 to PCS4 Input mode PMCCS Port DL PDL0 D0 to PDL15 D15 PDL0 to PDL15 Input mode PMCDL Port AL PA...

Page 530: ...ort block diagrams Figure 16 1 Type A Block Diagram Remark N 1 to 5 Port number n 0 to 7 Port pin for port number 0 and 1 n 0 to 5 Port pin for port number 2 to 5 RDPNn PMCNn PMNn PNn WRPMCNn WRPMNn Selector WRPNn Fnc Address Data I O control Internal bus Selector Selector PNn ...

Page 531: ...ons Preliminary User s Manual U14913EE1V0UM00 Figure 16 2 Type B Block Diagram Remark n 0 to 5 Selector Selector Selector Internal bus RDP6 PMC6n PM6n WRPM6 WRPM6 WRP6 P6n P6n LCD Segment enable Segment drive signal Fnc Address ...

Page 532: ...Preliminary User s Manual U14913EE1V0UM00 Figure 16 3 Type C Block Diagram Remark n 0 to 15 Selector Selector Selector Internal bus RDPAL PMCALn PMALn WRPMCAL WRPMAL WRPAL PALn PALn LCD Segment enable Segment drive signal An Address ...

Page 533: ... Functions Preliminary User s Manual U14913EE1V0UM00 Figure 16 4 Type D Block Diagram Remark n 0 to 15 RDPDL PMCDLn PMDLn PDLn WRPMCDL WRPMDL Selector WRPDL Dn Address Data I O control Internal bus Selector Selector PDLn ...

Page 534: ...reliminary User s Manual U14913EE1V0UM00 Figure 16 5 Type E Block Diagram Remark n 2 3 4 Selector Selector Selector Internal bus RDPCS PMCCSn PMCSn WRPMCCS WRPMCS WRPCS PCSn PCSn LCD Segment enable Segment drive signal _CS2 _CS3 _CS4 ...

Page 535: ...minary User s Manual U14913EE1V0UM00 Figure 16 6 Type F Block Diagram Remark n 0 to 4 Selector Selector Selector Internal bus RDPCT PMCCTn PMCTn WRPMCCT WRPMCT WRPCT PCTn PCTn LCD Segment enable Segment drive signal _LWR _UWR _RD Address ...

Page 536: ...Functions Preliminary User s Manual U14913EE1V0UM00 Figure 16 7 Type G Block Diagram Selector Selector Internal bus RDPCM0 PMCCM0 PMCM0 WRPMCCM0 WRPMCM0 WRPCM0 PCM0 PCM0 LCD Segment enable Segment drive signal Address WAIT ...

Page 537: ...ons Preliminary User s Manual U14913EE1V0UM00 Figure 16 8 Type H Block Diagram Selector Selector Selector Internal bus RDPCM1 PMCCM1 PMCM1 WRPMCCM1 WRPMCM1 WRPCM1 PCM1 PCM1 LCD Segment enable Segment drive signal CLKOUT Address ...

Page 538: ... the port 1 mode control register PMC1 a Port 1 mode register PM1 This register can be read or written in 8 or 1 bit units Figure 16 10 Port 1 Mode Register PM1 7 6 5 4 3 2 1 0 Address At Reset P1 P17 P16 P15 P14 P13 P12 P11 P10 FFFFF400H 00H Bit position Bit name Function 7 to 0 P1n n 7 to 0 Input output port Port Alternate Pin Name Remarks Block Type Port 1 P10 CRXD1 Serial interface UART1 FCAN1...

Page 539: ...ut mode 6 PMC16 Specifies operation mode of P16 pin 0 Input output port mode 1 RXD1 input mode 5 PMC15 Specifies operation mode of P15 pin 0 Input output port mode 1 CTXD3 output mode 4 PMC14 Specifies operation mode of P14 pin 0 Input output port mode 1 CRXD3 input mode 3 PMC13 Specifies operation mode of P13 pin 0 Input output port mode 1 CTXD2 output mode 2 PMC12 Specifies operation mode of P12...

Page 540: ... mode control register PMC2 a Port 2 mode register PM2 This register can be read or written in 8 or 1 bit units Figure 16 13 Port 2 Mode Register PM2 7 6 5 4 3 2 1 0 Address At Reset P2 P27 P26 P25 P24 P23 P22 P21 P20 FFFFF402H 00H Bit position Bit name Function 7 to 0 P2n n 7 to 0 Input output port Port Alternate Pin Name Remarks Block Type Port 2 P20 SI0 Serial interface CSI0 CSI1 UART0 input ou...

Page 541: ... mode 6 PMC26 Specifies operation mode of P26 pin 0 Input output port mode 1 RXD0 input mode 5 PMC25 Specifies operation mode of P25 pin 0 Input output port mode 1 SCK1 input output mode 4 PMC24 Specifies operation mode of P24 pin 0 Input output port mode 1 SO1 output mode 3 PMC23 Specifies operation mode of P23 pin 0 Input output port mode 1 SI1 input mode 2 PMC22 Specifies operation mode of P22 ...

Page 542: ...ol register PMC3 a Port 3 mode register PM3 This register can be read or written in 8 or 1 bit units Figure 16 16 Port 3 Mode Register PM3 7 6 5 4 3 2 1 0 Address At Reset P3 0 0 P35 P34 P33 P32 P31 P30 FFFFF404H 00H Bit position Bit name Function 5 to 0 P3n n 5 to 0 Input output port Port Alternate Pin Name Remarks Block Type Port 3 P30 TIE0 INTPE00 Real time pulse unit RPU input or external inte...

Page 543: ...peration mode of P34 pin 0 Input output port mode 1 TOE40 input output mode or external interrupt request INTPE40 input mode 3 PMC33 Specifies operation mode of P33 pin 0 Input output port mode 1 TOE30 input output mode or external interrupt request INTPE30 input mode 2 PMC32 Specifies operation mode of P32 pin 0 Input output port mode 1 TOE20 input output mode or external interrupt request INTPE2...

Page 544: ...ol register PMC4 a Port 4 mode register PM4 This register can be read or written in 8 or 1 bit units Figure 16 19 Port 4 Mode Register PM4 7 6 5 4 3 2 1 0 Address At Reset P4 0 0 P45 P44 P43 P42 P41 P40 FFFFF406H 00H Bit position Bit name Function 5 to 0 P4n n 5 to 0 Input output port Port Alternate Pin Name Remarks Block Type Port 4 P40 TIE1 INTPE01 Real time pulse unit RPU input or external inte...

Page 545: ...peration mode of P44 pin 0 Input output port mode 1 TOE41 input output mode or external interrupt request INTPE41 input mode 3 PMC43 Specifies operation mode of P43 pin 0 Input output port mode 1 TOE31 input output mode or external interrupt request INTPE31 input mode 2 PMC42 Specifies operation mode of P42 pin 0 Input output port mode 1 TOE21 input output mode or external interrupt request INTPE2...

Page 546: ...ol register PMC5 a Port 5 mode register PM5 This register can be read or written in 8 or 1 bit units Figure 16 22 Port 5 Mode Register PM5 7 6 5 4 3 2 1 0 Address At Reset P5 0 0 P55 P54 P53 P52 P51 P50 FFFFF408H 00H Bit position Bit name Function 5 to 0 P5n n 5 to 0 Input output port Port Alternate Pin Name Remarks Block Type Port 5 P50 TIE2 INTPE02 Real time pulse unit RPU input or external inte...

Page 547: ...peration mode of P54 pin 0 Input output port mode 1 TOE42 input output mode or external interrupt request INTPE42 input mode 3 PMC53 Specifies operation mode of P53 pin 0 Input output port mode 1 TOE32 input output mode or external interrupt request INTPE32 input mode 2 PMC52 Specifies operation mode of P52 pin 0 Input output port mode 1 TOE22 input output mode or external interrupt request INTPE2...

Page 548: ...e register PM6 This register can be read or written in 8 or 1 bit units Figure 16 25 Port 6 Mode Register PM6 7 6 5 4 3 2 1 0 Address At Reset P6 0 0 P65 P64 P63 P62 P61 P60 FFFFF40AH 00H Bit position Bit name Function 5 to 0 P6n n 5 to 0 Input output port Port Alternate Pin Name Remarks Block Type Port 6 P60 CCLK SEG34 External CAN clock supply or segment signal output of LCD controller B P61 INT...

Page 549: ...oller mode 1 TXD output mode 4 PMC64 Specifies operation mode of P64 pin 0 Input output port mode or segment signal output of LCD controller mode 1 RXD input mode 3 PMC63 Specifies operation mode of P63 pin 0 Input output port mode or segment signal output of LCD controller mode 1 External interrupt request INT2 input mode 2 PMC62 Specifies operation mode of P62 pin 0 Input output port mode or seg...

Page 550: ...er PMCAL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address At Reset PAL PAL15 PAL14 PAL13 PAL12 PAL11 PAL10 PAL9 PAL8 PAL7 PAL6 PAL5 PAL4 PAL3 PAL2 PAL1 PAL0 FFFFF000H 0000H Bit position Bit name Function 15 to 0 PALn n 15 to 0 Input output port Port Alternate Function Remark Block Type Port AL PAL15 to PAL0 A15 to A0 SEG23 to SEG8 Address bus when memory expanded or segment signal out put of LCD cont...

Page 551: ...eans of the port AH mode control register PMCAH a Port AH mode register PMAH This register can be read written in 16 8 or 1 bit units Figure 16 31 Port AH Mode Register PMAH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address At Reset PAH PAH7 PAH6 PAH5 PAH4 PAH3 PAH2 PAH1 PAH0 FFFFF002H 00H Bit position Bit name Function 7 to 0 PAHn n 7 to 0 Input output port 15 8 Unknown Data Port Alternate Function R...

Page 552: ...nput mode and port mode before enabling LCD segment mode To avoid high cross current and to ensure that LCD is working properly 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address At Reset PMCAH PMCAH7 PMCAH6 PMCAH5 PMCAH4 PMCAH3 PMCAH2 PMCAH1 PMCAH0 FFFFF042H 00H Bit Position Bit Name Function 7 to 0 PMCAHn n 7 to 0 Port Mode Control Specifies operation mode of PAHn pin 0 I O port mode or segment signa...

Page 553: ...L The PMDL register can be read or written in 16 bit units When using the higher 8 bits of the PMDL register as the PMDLH register and the lower 8 bits as the PMDLL register it can be read or written in 8 or 1 bit units Figure 16 34 Port DL Mode Register PMDL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address At Reset PDL PDL15 PDL14 PDL13 PDL12 PDL11 PDL10 PDL9 PDL8 PDL7 PDL6 PDL5 PDL4 PDL3 PDL2 PDL1 ...

Page 554: ...s as the PMCDLL register it can be read or written in 8 or 1 bit units Figure 16 35 Port DL Mode Control Register PMCDL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address At Reset PMCDL PMCDL15 PMCDL14 PMCDL13 PMCDL12 PMCDL11 PMCDL10 PMCDL9 PMCDL8 PMCDL7 PMCDL6 PMCDL5 PMCDL4 PMCDL3 PMCDL2 PMCDL1 PMCDL0 FFFFF044H 0000H Bit Position Bit Name Function 15 to 0 PMCDLn n 15 to 0 Specifies operation mode of P...

Page 555: ...er PMCS In control mode it is set using the port CS mode control register PMCCS a Port CS mode register PMCS This register can be read or written in 8 or 1 bit units Figure 16 37 Port CS Mode Register PMCS 7 6 5 4 3 2 1 0 Address At Reset PCS 0 0 0 PCS4 PCS3 PCS2 0 0 FFFFF008H 00H Bit Position Bit Name Function 7 to 0 PCSn n 4 to 2 Input output port Port Alternate Pin Name Remarks Block Type Port ...

Page 556: ...n Make sure that Port CS is input mode and port mode before enabling LCD segment mode To avoid high cross current and to ensure that LCD is working properly 7 6 5 4 3 2 1 0 Address At Reset PMCCS 0 0 0 PMCCS4 PMCCS3 PMCCS2 0 0 FFFFF048H 00H Bit Position Bit Name Function 7 to 0 PMCCSn n 4 to 2 Specifies operation mode of PCSn pin 0 Input output port mode or segment signal output of LCD controller ...

Page 557: ... a Port CT mode register PMCT This register can be read or written in 8 or 1 bit units Figure 16 40 Port CT Mode Register PMCT 7 6 5 4 3 2 1 0 Address At Reset PCT x x x PCT4 PCT3 PCT2 PCT1 PCT0 FFFFF00AH FFH Bit Position Bit Name Function 7 to 0 PCTn n 4 to 0 Input output port Port Alternate Pin Name Remarks Block type Port CT PCT0 LWR SEG27 Write strobe signal output or segment signal out put of...

Page 558: ...1 0 Address At Reset PMCCT 0 0 0 PMCCT4 PMCCT3 PMCCT2 PMCCT1 PMCCT0 FFFFF04AH 00H Bit Position Bit Name Function 4 PMCCT4 Specifies operation mode of PCT4 pin 0 Input output port mode or segment signal output of LCD controller mode 1 RD output mode 1 PMCCT1 Specifies operation mode of PCT1 pin 0 Input output port mode or segment signal output of LCD controller mode 1 UWR output mode 0 PMCCT0 Speci...

Page 559: ...ntrol mode it is set using the port CM mode control register PMCCM a Port CM mode register PMCM This register can be read or written in 8 or 1 bit units Figure 16 43 Port CM Mode Register PMCM 7 6 5 4 3 2 1 0 Address At Reset PCM 0 0 0 0 0 0 PCM1 PCM0 FFFFF00CH 00H Bit Position Bit Name Function 1 0 PCMn n 2 to 0 Input output port Port Alternate Pin Name Remarks Block Type Port CM PCM0 WAIT SEG32 ...

Page 560: ... is input mode and port mode before enabling LCD segment mode 7 6 5 4 3 2 1 0 Address At Reset PMCCM 0 0 0 0 0 0 PMCCM1 PMCCM0 FFFFF04CH 00H Bit Position Bit Name Function 1 PMCCM1 Specifies operation mode of PCM1 pin 0 Input output port mode or segment signal output of LCD controller mode 1 CLKOUT output mode 0 PMCCM0 Specifies operation mode of PCM0 pin 0 Input output port mode or segment signal...

Page 561: ...3x CVDD CVSS AVDD AVREF and AVSS pins Thus if for example memory is extended externally a pull up or pull down resistor must be attached to PAH PAL PDL PCS PCT and PCM If there are no resistors the external memory that is connected may be destroyed when these pins become high impedance Similarly perform pin processing so that on chip peripheral I O function signal output and output ports are not a...

Page 562: ...lease by the RESET signal 2 Reset at power on A reset operation at power on power supply application must guarantee oscillation stabilization time from power on until reset acknowledgment due to the low level width of the RESET signal Figure 17 2 Reset at power on RESET Internal system reset signal Elimination as noise Reset acknowledgment Reset release Analog delay Analog delay Analog delay Note ...

Page 563: ...e timing are synchronized On a RESET other than this data is maintained in its previous status On Chip Hardware Register Name Initial Value After Reset CPU Program registers General purpose register r0 00000000H General purpose registers r1 to r31 Undefined Program counter PC 00000000H System registers Status save registers during interrupt EIPC EIPSW Undefined Status save registers during NMI FEP...

Page 564: ...564 Preliminary User s Manual U14913EE1V0UM00 MEMO ...

Page 565: ...locks and on chip logic circuits excluding the A D converter and output buffers The regulators output voltage is set to 3 3 V Figure 18 1 Regulator 18 2 Operation The V850E CA1 s regulators operate in every mode STOP IDLE WATCH HALT For stabilization of regulator outputs it is recommended to connect capacitors to the VDD3X pins and also to the CVDD pin Flash Memory Regulator Regulator OSC PLL On C...

Page 566: ...566 Preliminary User s Manual U14913EE1V0UM00 MEMO ...

Page 567: ...neration by comparator The user can define the type of interrupt signal INT or NMI Rising edge or falling edge can be selected External NMI can be passed through from the comparator output pin VCMPOUT Comparator threshold and hysteresis are set by external resistors Easy detection of low voltage operation The figure 19 1 shows a block diagram of the comparator Figure 19 1 Block Diagram of Voltage ...

Page 568: ...s range The I O driver circuits are assumed to have reduced driving capabilities Caution As the clock of the Operating System Timer is derived from the system clock it might be necessary to adapt the operating system timer settings when entering and leaving the low frequency operating mode For easy detection of low voltage operation VDD AVDD 4 V a comparator circuit is integrated in the ATOMIC dev...

Page 569: ... The threshold has to be set to a voltage above 4 5 V to guarantee the frequency change within the time the supply voltage drops below 4 5 V The minimum threshold therefore depends on the maximal speed the supply voltage drops down and it depends on the execution time of the interrupt service routine Ref measure point hysteresis threshold Flag Bit Status Register INT ATOMIC RH RT2 RT1 VCMPOUT VCMP...

Page 570: ...ction VCEN Voltage Comparator Enable Enables or disables internal voltage comparator 0 Disabled 1 Enabled NSOCE NMI Source Selects NMI source 0 NMI from external pin input 1 NMI from internal voltage comparator Note Once set this bit to 0 reset signal only make this bit to 0 EFBK Enable Feedback Enables or disables comparator feedback 0 Disabled 1 Enabled EDN1 EDN0 Edge detect control for NMI EDN1...

Page 571: ...onment and the application using a flash memory Software can be altered after the µPD70F3123 is solder mounted on the target system Small scale production of various models is made easier by differentiating software Data adjustment in starting mass production is made easier Alter the software in the field using the Selfprogramming option 20 1 Features 4 byte 1 word access in 1 clock instruction fe...

Page 572: ... a flash memory is performed using a dedicated programming adapter PA board etc before mounting the µPD70F3123 onto the target system 20 3 Programming Environment The following diagram shows the environment required for writing programs to the flash memory of the µPD70F3123 Figure 20 1 Programming Environment in Conjunction with External Flash Writer A host machine can be used to control the flash...

Page 573: ...h Writer Communication via CSI0 Note The supply of operating clock from the flash writer to the µPD70F3123 is not mandatory Like in normal operating mode the µPD70F3123 may also operate in flash memory programming mode with a target system clock e g a crystal or resonator connected to X1 X2 pins In such case do not connect the CLKOUT signal from the flash writer VPP VDD VSS5n VSS3m RESET SO SI SCK...

Page 574: ...PP0 VPP1 pins have to be connected via a pull down resistor to ground and the voltage regulator µPC29S78 can be removed Figure 20 3 Application Example for Flash Selfprogramming VSS30 VSS31 VSS32 VDD30 VDD31 VDD32 CVDD CVSS VSS52 VSS53 VSS54 VDD52 VDD53 VDD54 VSS50 VSS51 VDD50 VDD51 X1 X2 VCMPIN VCMPOUT µPD76F3123 3 x CVDD3 CLKSEL IC CLKIN 5 V MODE1 MODE2 MODE0 µPC29S78 VIN V PP1 V PP0 5 V PXY 2 4...

Page 575: ...de can be controlled by the flash writer In flash memory programming mode all pins not required for the flash memory programming remain in the same status as immediately after reset 20 6 1 VPP0 VPP1 pins In the normal operation mode 0 V is input to both VPP0 and VPP1 pins In the flash memory program ming mode 7 8 V writing voltage is supplied to both VPP0 and VPP1 pins The following figure shows a...

Page 576: ... writer output to a serial interface pin input which is con nected to another device output conflict of signals may happen To avoid the conflict of signals isolate the connection to the other device or set the other device to the high impedance status Figure 20 5 Conflict between Flash Writer and Other Output Pin Serial Interface Pins Used CSI0 SO0 SI0 SCK0 Output pin Flash writer connection pin I...

Page 577: ...or make the setting so that the input signal to the other device is ignored Figure 20 6 Malfunction of Other Input Pins Flash writer connection pin µPD70F3123 Output pin The other device Input pin In the flash memory programming mode if the signal that the µPD70F3123 outputs affects the other device isolate the signal on the other device side Flash writer connection pin µPD70F3123 Input pin The ot...

Page 578: ...mming may not be performed correctly 20 6 5 MODE pin To switch to the flash memory programming mode change MODE0 through MODE2 accordingly with jumpers etc apply writing voltage to VPP0 VPP1 pins and release the reset 20 6 6 Port pins When the flash memory programming mode is set all the port pins except the pins which communicate with the dedicated flash writer become high impedance status The tr...

Page 579: ... of communication mode In the µPD70F3123 as well as for other V850 family devices a communication system is selected by inputting pulses 16 pulses max to VPP0 pin after switching to the flash memory programming mode The VPP0 pulses are generated by the dedicated flash writer The following table shows the relation between the number of pulses and the communication systems Table 20 1 List of Communi...

Page 580: ...face Figure 20 9 Configuration in Selfprogramming Mode In order to operate flash Selfprogramming flash Selfprogramming libraries are prepared for user Following operations to the flash memory are supported by libraries Initialize Blank Check Erase Write Verify Blank check Vpp Voltage Check Create Signature Check Signature Swap Area Check Area For further details please refer to the following docum...

Page 581: ...areas It is located within the user address space of the flash memory The signature structure was chosen in a way to ensure that no user data can be mistakenly interpreted as a signature This is achieved by a different usage of internal structures of the flash memory 20 9 3 Secure Selfprogramming flow A reprogramming of the flash memory starts with an erase of the upper area After a successful era...

Page 582: ...otblock Size Bootblock Size Bootprogram Bootprogram Bootprogram Application Part 1 Application Part 1 Application Part 1 Application Part 2 Erased Vector Table Signature Bootblock Size Bootprogram 00000000H 00020000H 0003FFFFH Area 0 Area 0 Area 0 Area 1 Area 1 Area 1 Upper Area Lower Area Erase upper Area Copy bootloader to upper area set signature in upper area kill signature in lower area Kill ...

Page 583: ...8 KB are supported It is possible to update the boot program using the secure mechanisms Vector Table Vector Table Vector Table Signature Signature Signature Bootblock Size Bootblock Size Bootblock Size Bootprogram Bootprogram Bootprogram New Application Part 1 New Application Part 2 Erased Erased Erased Vector Table Bootblock Size Bootprogram Application Part 1 00000000H 00020000H 0003FFFFH Area ...

Page 584: ...584 Preliminary User s Manual U14913EE1V0UM00 MEMO ...

Page 585: ...ment data regID System register number vector 5 bit data that specifies the trap vector 00H to 1FH cccc 4 bit data that shows the conditions code sp Stack pointer SP ep Element pointer r30 listX X item register list Register Symbol Explanation R 1 bit data of a code that specifies reg1 or regID r 1 bit data of the code that specifies reg2 w 1 bit data of the code that specifies reg3 d 1 bit displa...

Page 586: ... of calculations n 7FFFFFFFH let it be 7FFFFFFFH n 80000000H let it be 80000000H result Reflects the results in a flag Byte Byte 8 bits Half word Half word 16 bits Word Word 32 bits Addition Subtraction ll Bit concatenation Multiplication Division Remainder from division results AND Logical product OR Logical sum XOR Exclusive OR NOT Logical negation logically shift left by Logical shift left logi...

Page 587: ...V 1 0 0 0 OV 0 No overflow C L 0 0 0 1 CY 1 Carry Lower Less than NC NL 1 0 0 1 CY 0 No carry Not lower Greater than or equal Z E 0 0 1 0 Z 1 Zero Equal NZ NE 1 0 1 0 Z 0 Not zero Not equal NH 0 0 1 1 CY or Z 1 Not higher Less than or equal H 1 0 1 1 CY or Z 0 Higher Greater than N 0 1 0 0 S 1 Negative P 1 1 0 0 S 0 Positive T 0 1 0 1 Always Unconditional SA 1 1 0 1 SAT 1 Saturated LT 0 1 1 0 S xo...

Page 588: ...g3 rrrrr111111iiiii wwwww011000cccc0 if conditions are satisfied then GR reg3 sign extended imm5 else GR reg3 GR reg2 1 1 1 cccc reg1 reg2 reg3 rrrrr111111RRRRR wwwww011001cccc0 if conditions are satisfied then GR reg3 GR reg1 else GR reg3 GR reg2 1 1 1 CMP reg1 reg2 rrrrr001111RRRRR result GR reg2 GR reg1 1 1 1 imm5 reg2 rrrrr010011iiiii result GR reg2 sign extend imm5 1 1 1 CTRET 000001111110000...

Page 589: ...RR iiiiiiiiiiiiiiii iiiiiiiiiiiiiiii GR reg1 imm32 2 2 2 MOVEA imm16 reg1 reg2 rrrrr110001RRRRR iiiiiiiiiiiiiiii GR reg2 GR reg1 sign extend imm16 1 1 1 MOVHI imm16 reg1 reg2 rrrrr110010RRRRR iiiiiiiiiiiiiiii GR reg2 GR reg1 imm16 ll 016 1 1 1 MUL reg1 reg2 reg3 rrrrr111111RRRRR wwwww01000100000 GR reg3 ll GR reg2 GR reg2 GR reg1 1 2 Note 14 2 imm9 reg2 reg3 rrrrr111111iiiii wwwww01001IIII00 GR re...

Page 590: ... adr GR reg1 sign extend disp16 Z flag Not Load memory bit adr bit 3 Store memory bit adr bit 3 1 3 Note 3 3 Note 3 3 Note 3 reg2 reg1 rrrrr111111RRRRR 0000000011100000 adr GR reg1 Z flag Not Load memory bit adr reg2 Store memory bit adr reg2 1 3 Note 3 3 Note 3 3 Note 3 SHL reg1 reg2 rrrrr111111RRRRR 0000000011000000 GR reg2 GR reg2 logically shift left by GR reg1 1 1 1 0 imm5 reg2 rrrrr010110iii...

Page 591: ... of the sub opcode ST W reg2 disp16 reg1 rrrrr111011RRRRR ddddddddddddddd1 Note 8 adr GR reg1 sign extend disp16 Store memory adr GR reg2 Word 1 1 1 STSR regID reg2 rrrrr111111RRRRR 0000000001000000 GR reg2 SR regID 1 1 1 SUB reg1 reg2 rrrrr001101RRRRR GR reg2 GR reg2 GR reg1 1 1 1 SUBR reg1 reg2 rrrrr001100RRRRR GR reg2 GR reg1 GR reg2 1 1 1 SWITCH reg1 00000000010RRRRR adr PC 2 GR reg1 logically...

Page 592: ...f 00 Load sp in ep 10 Load sign expanded 16 bit immediate data bits 47 to 32 in ep 11 Load 32 bit immediate data bits 63 to 32 in ep 17 If imm imm32 n 3 clocks 18 rrrrr Other than 00000 19 ddddddd Higher 7 bits of disp8 20 dddd Higher 4 bits of disp5 21 dddddd Higher 6 bits of disp8 ...

Page 593: ...ous serial interface operation UART0 to UART2 Baud rate generator 330 Continuous transmission operation 323 Receive operation 326 Reception error 327 Transmit operation 322 Asynchronous serial interface status registers 0 to 2 316 Asynchronous serial interface transmission status registers 0 to 2 317 Asynchronous serial interfaces 0 to 2 310 AVDD 47 AVREF 47 AVSS 47 B Baud rate generator CSI0 CSI1...

Page 594: ...ption buffer registers L0 L1 344 Clocked serial interface transmission buffer registers 0 1 347 Clocked serial interface transmission buffer registers L0 L1 348 Clocked serial interfaces 0 1 338 CMD0 CMD1 250 CMSE050 to CMSE052 272 CMSE120 to CMSE122 273 CMSE340 to CMSE342 275 COM0 to COM1 46 CSC0 CSC1 121 CSCE0 to CSCE2 280 CSE0 to CSE2 267 CSI0 CSI1 338 CSIC0 CSIC1 342 CSIM0 CSIM1 341 CVDD 46 CV...

Page 595: ... source address registers 0H to 3H 165 DMA source address registers 0L to 3L 166 DMA trigger factor registers 0 to 3 173 DN 387 388 392 393 405 415 417 421 422 428 449 467 DRST 172 DSA0H to DSA3H 165 DSA0L to DSA3L 166 DTFR0 to DTFR3 173 DWC0 DWC1 138 E ECR 56 Edge detection function 194 EEPS 482 ELC 485 ELISA Command format 465 Condition flag 464 Event processing status register 482 ELISA command...

Page 596: ... set port or control mode 528 G General registers 54 55 H HALT mode 233 234 I ID 206 IDLE Mode 236 IDLE mode 233 Illegal opcode definition 216 IMR0 to IMR3 205 In service priority register 206 Internal peripheral I O area 67 Internal RAM area 66 Internal ROM area 64 Internal voltage comparator control register 570 Interrupt control register 202 Interrupt mask registers 0 to 3 205 Interrupt respons...

Page 597: ...6 Page ROM configuration register 157 PC 54 55 Peripheral I O registers 71 Pin functions 29 34 Pin I O circuits 51 PLL status register 228 PM1 538 PM2 540 PM3 542 PM4 544 PM5 546 PM6 548 PMAH 551 PMAL 550 PMC1 539 PMC2 541 PMC3 543 PMC4 545 PMC5 547 PMC6 549 PMCAH 552 PMCAL 550 PMCCM 560 PMCCS 556 PMCDL 554 PMCM 559 PMCS 555 PMDL 553 Port 1 34 538 Port 2 35 540 Port 3 36 542 Port 4 37 544 Port 5 3...

Page 598: ...81 PRSCM0 PRSCM1 367 PRSM0 PRSM1 366 PSC 240 PSM 242 PSTAT 228 PSW 57 R Reception buffer registers 0 to 2 318 RESET 46 RXB0 to RXB2 318 S Script event pointer and command counter register 481 SEPCC 481 Serial I O shift registers 0 1 351 Serial I O shift registes L0 L1 352 SESE0 to SESE2 268 Single chip mode 58 SIO0 SIO1 351 SIOL0 SIOL1 352 SIRB0 SIRB1 343 SIRBE0 SIRBE1 345 SIRBEL0 SIRBEL1 346 SIRB...

Page 599: ...2 main capture compare registers 0 to 2 263 Timer E sub channel 2 sub capture compare registers 0 to 2 264 Timer E sub channel 3 main capture compare registers 0 to 2 263 Timer E sub channel 3 sub capture compare registers 0 to 2 264 Timer E sub channel 3 4 capture compare control registers 0 to 2 275 Timer E sub channel 4 main capture compare registers 0 to 2 263 Timer E sub channel 4 sub capture...

Page 600: ...600 Appendix B Index Preliminary User s Manual U14913EE1V0UM00 Watchdog timer Operation 307 WDTM 306 WTM 301 X X1 46 X2 46 ...

Page 601: ... 02 2719 5951 Address North America NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Technical Documentation Dept Fax 49 211 6503 274 South America NEC do Brasil S A Fax 55 11 6465 6829 Asian Nations except Philippines NEC Electronics Singapore Pte Ltd Fax 65 250 3583 Japan NEC Semiconductor Technical Hotline Fax 044 548 7900 I ...

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