NEC V850/SB1TM, User Manual

Page: 98 / 515

CHAPTER 3 CPU FUNCTIONS
User’s Manual U13850EJ4V0UM
98
(3/7)
Bit Units for Manipulation Address Function Register Name Symbol R/W
1 Bit 8 Bits 16 Bits 32 Bits
After Reset
FFFFF140H Interrupt control register CSIC4
√ √
FFFFF142H Interrupt control register IEBIC1
√ √
FFFFF144H Interrupt control register IEBIC2
√ √
FFFFF146H Interrupt control register ADIC
√ √
FFFFF148H Interrupt control register DMAIC0
√ √
FFFFF14AH Interrupt control register DMAIC1
√ √
FFFFF14CH Interrupt control register DMAIC2
√ √
FFFFF14EH Interrupt control register DMAIC3
√ √
FFFFF150H Interrupt control register DMAIC4
√ √
FFFFF152H Interrupt control register DMAIC5
√ √
FFFFF154H Interrupt control register WTNIC
√ √
FFFFF156H Interrupt control register KRIC
√ √
47H
FFFFF166H In-service priority register ISPR R
√ √
00H
FFFFF170H Command register PRCMD W
√
FFFFF180H DMA peripheral I/O address register 0 DIOA0
√
FFFFF182H DMA internal RAM address register 0 DRA0
√
FFFFF184H DMA byte count register 0 DBC0
√
Undefined
FFFFF186H DMA channel control register 0 DCHC0
√ √
00H
FFFFF190H DMA peripheral I/O address register 1 DIOA1
√
FFFFF192H DMA internal RAM address register 1 DRA1
√
FFFFF194H DMA byte count register 1 DBC1
√
Undefined
FFFFF196H DMA channel control register 1 DCHC1
√ √
00H
FFFFF1A0H DMA peripheral I/O address register 2 DIOA2
√
FFFFF1A2H DMA internal RAM address register 2 DRA2
√
FFFFF1A4H DMA byte count register 2 DBC2
√
Undefined
FFFFF1A6H DMA channel control register 2 DCHC2
√ √
00H
FFFFF1B0H DMA peripheral I/O address register 3 DIOA3
√
FFFFF1B2H DMA internal RAM address register 3 DRA3
√
Undefined
FFFFF1B4H DMA byte count register 3 DBC3
√
FFFFF1B6H DMA channel control register 3 DCHC3
√ √
00H
FFFFF1C0H DMA peripheral I/O address register 4 DIOA4
√
Undefined
FFFFF1C2H DMA internal RAM address register 4 DRA4
√
FFFFF1C4H DMA byte count register 4 DBC4
√
FFFFF1C6H DMA channel control register 4 DCHC4
√ √
00H
FFFFF1D0H DMA peripheral I/O address register 5 DIOA5
√
Undefined
FFFFF1D2H DMA internal RAM address register 5 DRA5
R/W
√