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NEC V850/SB1TM, User Manual


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CHAPTER  10    SERIAL  INTERFACE  FUNCTION

User’s Manual  U13850EJ4V0UM

309

Figure 10-31.  Example of Slave to Master Communication

(When 9-Clock Wait Is Selected for Both Master and Slave) (1/3)

(a)  Start condition ~ address

IICn

ACKDn

STDn

SPDn

WTIMn

H

H

L

L

H

H

L

ACKEn

MSTSn

STTn

L

L

SPTn

WRELn

INTIICn

TRCn

IICn

ACKDn

STDn

SPDn

WTIMn

ACKEn

MSTSn

STTn

SPTn

WRELn

INTIICn

TRCn

SCLn

SDAn

Processing by master device

Transfer lines

Processing by slave device

1

2

3

4

5

6

7

8

9

4

5

6

3

2

1

AD6 AD5 AD4 AD3 AD2 AD1 AD0

R

D4

D3

D2

D5

D6

D7

IICn 

←

 address

IICn 

←

 FFH Note

Note

IICn 

←

 data

Start condition

Note

To cancel slave wait, write FFH to IICn or set WRELn.

Remark

n = 0, 1

Summary of Contents for V850/SB1TM

Page 1: ...PD703031A PD703035A PD703031AY PD703035AY PD703032A PD703036A PD703032AY PD703036AY PD703033A PD703037A PD703033AY PD703037AY PD70F3032A PD70F3035A PD70F3032AY PD70F3035AY PD70F3033A PD70F3037A PD70F3...

Page 2: ...User s Manual U13850EJ4V0UM 2 MEMO...

Page 3: ...d to VDD or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications gove...

Page 4: ...the quality reliability and safety of NEC semiconductor products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to p...

Page 5: ...Electronics Germany GmbH Duesseldorf Germany Tel 0211 65 03 02 Fax 0211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Italiana s r l Milano Ita...

Page 6: ...ddition of Caution in CHAPTER 18 FLASH MEMORY p 444 Addition of Table 19 5 Acknowledge Signal Output Condition of Control Field p 452 Addition of description 19 1 8 Bit format p 457 Modification of Ca...

Page 7: ...nly Data type Register set Instruction format and instruction set Interrupt and exception Pipeline operation How to Read This Manual It is assumed that the reader of this manual has general knowledge...

Page 8: ...er of 2 address space memory capacity K kilo 2 10 1024 M mega 2 20 1024 2 G giga 2 30 1024 3 Related Documents The related documents indicated in this publication may include preliminary versions Howe...

Page 9: ...Debugger Operation Windows TM Based U14580E SM850 Ver 2 20 or Later System Simulator Operation Windows Based U14782E SM850 Ver 2 00 or Later System Simulator External Part User Open Interface Specific...

Page 10: ...nctions 51 2 2 Pin States 58 2 3 Description of Pin Functions 59 2 4 I O Circuit Types I O Buffer Power Supply and Connection of Unused Pins 69 2 5 I O Circuit of Pins 71 CHAPTER 3 CPU FUNCTIONS 73 3...

Page 11: ...Data space 123 CHAPTER 5 INTERRUPT EXCEPTION PROCESSING FUNCTION 124 5 1 Outline 124 5 1 1 Features 124 5 2 Non Maskable Interrupt 127 5 2 1 Operation 128 5 2 2 Restore 130 5 2 3 NP flag 131 5 2 4 Noi...

Page 12: ...16 Bit Timer TM0 TM1 174 7 1 1 Outline 174 7 1 2 Function 174 7 1 3 Configuration 176 7 1 4 Timer 0 1 control registers 179 7 2 16 Bit Timer Operation 187 7 2 1 Operation as interval timer 16 bits 18...

Page 13: ...isters 246 10 2 3 Operations 249 10 3 I 2 C Bus 252 10 3 1 Configuration 255 10 3 2 I 2 C control register 257 10 3 3 I 2 C bus mode functions 268 10 3 4 I 2 C bus definitions and control methods 269...

Page 14: ...A5 360 12 3 2 DMA internal RAM address registers 0 to 5 DRA0 to DRA5 361 12 3 3 DMA byte count registers 0 to 5 DBC0 to DBC5 366 12 3 4 DMA start factor expansion register DMAS 366 12 3 5 DMA channel...

Page 15: ...ment 425 18 4 Communication System 425 18 5 Pin Connection 428 18 5 1 VPP pin 428 18 5 2 Serial interface pin 428 18 5 3 RESET pin 431 18 5 4 Port pin including NMI 431 18 5 5 Other signal pins 431 18...

Page 16: ...terrupt control block 478 19 4 2 Interrupt source list 479 19 4 3 Communication error source processing list 480 19 5 Interrupt Generation Timing and Main CPU Processing 482 19 5 1 Master transmission...

Page 17: ...18 Internal Peripheral I O Area 88 3 19 External Memory Area When Expanded to 64 K 256 K or 1 MB 89 3 20 External Memory Area When Expanded to 4 MB 90 3 21 Memory Expansion Mode Register MM Format 91...

Page 18: ...essing 146 5 17 RETI Instruction Processing 147 5 18 EP Flag EP 148 5 19 Illegal Op Code 148 5 20 Exception Trap Processing 149 5 21 RETI Instruction Processing 150 5 22 Pipeline Operation at Interrup...

Page 19: ...Counter Mode 197 7 24 Configuration of External Event Counter 198 7 25 Timing of External Event Counter Operation with Rising Edge Specified 198 7 26 Control Register Settings in Square Wave Output Mo...

Page 20: ...0 1 Block Diagram of 3 Wire Serial I O 245 10 2 Serial Operation Mode Registers 0 to 3 CSIM0 to CSIM3 247 10 3 Serial Clock Selection Registers 0 to 3 CSIS0 to CSIS3 248 10 4 CSIMn Setting Operation S...

Page 21: ...Serial Interface Mode 323 10 42 Error Tolerance When k 16 Including Sampling Errors 325 10 43 Format of Transmit Receive Data in Asynchronous Serial Interface 326 10 44 Timing of Asynchronous Serial...

Page 22: ...5 DBC0 to DBC5 366 12 8 DMA Start Factor Expansion Register DMAS 366 12 9 Format of DMA Channel Control Registers 0 to 5 DCHC0 to DCHC5 367 13 1 Block Diagram of RTO 369 13 2 Configuration of Real Tim...

Page 23: ...2 Block Diagram of P70 to P77 and P80 to P83 400 14 33 Port 9 P9 401 14 34 Port 9 Mode Register PM9 402 14 35 Block Diagram of P90 to P96 403 14 36 Port 10 P10 404 14 37 Port 10 Mode Register PM10 405...

Page 24: ...iguration of Lock Address 451 19 9 Bit Format of IEBus 452 19 10 IEBus Controller Block Diagram 453 19 11 IEBus Control Register BCR 456 19 12 IEBus Unit Address Register UAR Format 459 19 13 IEBus Sl...

Page 25: ...nsmission 482 19 31 Master Reception 484 19 32 Slave Transmission 486 19 33 Slave Reception 488 19 34 Master Transmission Interval of Interrupt Occurrence 490 19 35 Master Reception Interval of Interr...

Page 26: ...ons 151 5 4 Description of Key Return Detection Pin 156 6 1 Operating Statuses in HALT Mode 166 6 2 Operating Statuses in IDLE Mode 168 6 3 Operating Statuses in Software STOP Mode 170 7 1 Configurati...

Page 27: ...e Output Buffer Registers Are Manipulated 371 13 3 Operation Mode and Output Trigger of Real Time Output Port 372 14 1 Pin I O Buffer Power Supplies 375 14 2 Port 0 Alternate Function Pins 376 14 3 Po...

Page 28: ...443 19 5 Acknowledge Signal Output Condition of Control Field 444 19 6 Contents of Telegraph Length Bit 445 19 7 Internal Registers of IEBus Controller 455 19 8 Reset Conditions of Flags in ISR Regis...

Page 29: ...5 V I O interface support and ROM correction For V850 SB2 based on the V850 SB1 the peripheral functions of automobile LAN IEBus Inter Equipment Bus are added In addition to high real time response ch...

Page 30: ...ask ROM 128 KB 12 KB 100 pin QFP 14 20 100 pin LQFP 14 14 PD703035A Mask ROM PD70F3035A None Flash memory PD703035AY Mask ROM PD70F3035AY Available Flash memory 256 KB 16 KB 100 pin QFP 14 20 100 pin...

Page 31: ...bus address data multiplex Address bus separate output enabled 3 V to 5 V interface enabled Bus hold function External wait function Internal memory PD703031A 703031AY mask ROM 128 KB RAM 12 KB PD7030...

Page 32: ...controller Internal RAM internal peripheral I O 6 channels Real time output port RTP 8 bits 1 channel or 4 bits 2 channels ROM correction Modifiable 4 points Regulator 4 0 V to 5 5 V input internal 3...

Page 33: ...100 pin plastic LQFP fine pitch 14 14 100 pin plastic QFP 14 20 100 pin plastic LQFP fine pitch 14 14 100 pin plastic QFP 14 20 100 pin plastic QFP 14 20 100 pin plastic LQFP 14 20 100 pin plastic QFP...

Page 34: ...4 15 16 17 18 19 20 21 22 23 24 25 1 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 75 P21 SO2 P23 RXD1 SI3 P24 TXD1 SO3 EVDD EVSS P26 TI2 TO2 P27 TI3 TO3 P30 TI00 P31 TI01 P3...

Page 35: ...1 SI3 P24 TXD1 SO3 EVDD EVSS P26 TI2 TO2 P27 TI3 TO3 P30 TI00 P31 TI01 P33 TI11 SO4 P34 TO0 A13 SCK4 P35 TO1 A14 P36 TI4 TO4 A15 P37 TI5 TO5 IC VPP Note 1 P100 RTP0 KR0 A5 P101 RTP1 KR1 A6 P102 RTP2 K...

Page 36: ...ata DSTB Data strobe SCK0 to SCK4 Serial clock EVDD Power supply for port SCL0 SCL1 Serial clock EVSS Ground for port SDA0 SDA1 Serial data HLDAK Hold acknowledge SI0 to SI4 Serial input HLDRQ Hold re...

Page 37: ...TM1 8 bit timer TM2 to TM7 TO0 TO1 DMAC 6 ch Watch timer P80 to P83 P90 to P96 EVSS DSTB RD P93 R W WRH P92 LBEN WRL P90 RTPTRG A13 to A15 P34 to P36 A1 to A12 P100 to P107 P110 to P113 SO2 SI2 SDA1...

Page 38: ...mask ROM PD70F3033A 70F3033AY 256 KB flash memory PD703030A 703030AY 384 KB mask ROM PD703032A 703032AY 512 KB mask ROM PD70F3032A 70F3032AY 512 KB flash memory ROM can be accessed by the CPU in one...

Page 39: ...rial interfaces UART0 UART1 clocked serial interfaces CSI0 to CSI3 and an 8 16 bit variable length serial interface CSI4 These plus the I 2 C bus interfaces I 2 C0 I 2 C1 comprise five channels Two of...

Page 40: ...al interface Port 2 8 bit I O Serial interface timer I O Port 3 8 bit I O Timer I O external address bus serial interface Port 4 8 bit I O External address data bus Port 5 8 bit I O Port 6 6 bit I O E...

Page 41: ...parate output enabled 3 V to 5 V interface enabled Bus hold function External wait function Internal memory PD703034A 703034AY mask ROM 128 KB RAM 12 KB PD703035A 703035AY mask ROM 256 KB RAM 16 KB PD...

Page 42: ...annels Real time output port RTP 8 bits 1 channel or 4 bits 2 channels ROM correction Modifiable 4 points Regulator 4 0 V to 5 5 V input internal 3 0 V Key return function 4 to 8 selecting enabled fal...

Page 43: ...3035AYGF xxx 3BA 100 pin plastic QFP 14 20 Mask ROM 256 KB PD703036AGF xxx 3BA Note 100 pin plastic QFP 14 20 Mask ROM 384 KB PD703036AYGF xxx 3BA Note 100 pin plastic QFP 14 20 Mask ROM 384 KB PD7030...

Page 44: ...16 17 18 19 20 21 22 23 24 25 1 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 75 P21 SO2 P23 RXD1 SI3 P24 TXD1 SO3 EVDD EVSS P26 TI2 TO2 P27 TI3 TO3 P30 TI00 P31 TI01 P33 TI1...

Page 45: ...P24 TXD1 SO3 EVDD EVSS P26 TI2 TO2 P27 TI3 TO3 P30 TI00 P31 TI01 P33 TI11 SO4 P34 TO0 A13 SCK4 P35 TO1 A14 P36 TI4 TO4 A15 P37 TI5 TO5 IC VPP Note 1 P100 RTP0 KR0 A5 P101 RTP1 KR1 A6 P102 RTP2 KR2 A7...

Page 46: ...0 to SCK4 Serial clock EVDD Power supply for port SCL0 SCL1 Serial clock EVSS Ground for port SDA0 SDA1 Serial data HLDAK Hold acknowledge SI0 to SI4 Serial input HLDRQ Hold request SO0 to SO4 Serial...

Page 47: ...it timer TM2 to TM7 TO0 TO1 DMAC 6 ch Watch timer P80 to P83 P90 to P96 EVSS DSTB RD P93 R W WRH P92 LBEN WRL P90 RTPTRG A13 to A15 P34 to P36 A1 to A12 P100 to P107 P110 to P113 SO2 SI2 SDA1 Note 3 C...

Page 48: ...mask ROM PD70F3035A 70F3035AY 256 KB flash memory PD703036A 703036AY 384 KB mask ROM PD703037A 703037AY 512 KB mask ROM PD70F3037A 70F3037AY 512 KB flash memory ROM can be accessed by the CPU in one...

Page 49: ...serial interfaces UART0 UART1 clocked serial interfaces CSI0 to CSI3 and an 8 16 bit variable length serial interface CSI4 These plus the I 2 C bus interfaces I 2 C0 I 2 C1 comprise five channels Two...

Page 50: ...ddress bus serial interface Port 4 8 bit I O External address data bus Port 5 8 bit I O Port 6 6 bit I O External address bus Port 7 8 bit input A D converter analog input Port 8 4 bit input Port 9 7...

Page 51: ...RESET 3 0 V EVDD 5 5 V Caution The electrical specifications in the case of 3 0 V to up to 4 0 V are different from those for 4 0 V to 5 5 V Differences of pins between the V850 SB1 and V850 SB2 are s...

Page 52: ...t Input output mode can be specified in 1 bit units INTP6 P10 SI0 SDA0 P11 SO0 P12 SCK0 SCL0 P13 SI1 RXD0 P14 SO1 TXD0 P15 I O Yes Port 1 6 bit I O port Input output mode can be specified in 1 bit uni...

Page 53: ...units TI5 TO5 P40 AD0 P41 AD1 P42 AD2 P43 AD3 P44 AD4 P45 AD5 P46 AD6 P47 I O No Port 4 8 bit I O port Input output mode can be specified in 1 bit units AD7 P50 AD8 P51 AD9 P52 AD10 P53 AD11 P54 AD12...

Page 54: ...WRH P93 DSTB RD P94 ASTB P95 HLDAK P96 I O No Port 9 7 bit I O port Input output mode can be specified in 1 bit units HLDRQ P100 RTP0 A5 KR0 P101 RTP1 A6 KR1 P102 RTP2 A7 KR2 P103 RTP3 A8 KR3 P104 RT...

Page 55: ...strobe signal output P94 AVDD Positive power supply for A D converter and alternate function port AVREF Input Reference voltage input for A D converter AVSS Ground potential for A D converter and alte...

Page 56: ...utput Yes Real time output port P106 A11 KR6 P107 A12 KR7 RTPTRG Input Yes RTP external trigger input P06 INTP5 R W Output No External read write status output P92 WRH RXD0 P13 SI1 RXD1 Input Yes Seri...

Page 57: ...nal count clock input for TM5 P37 TO5 TO0 TO1 Pulse signal output for TM0 TM1 P34 A13 SCK4 P35 A14 TO2 Pulse signal output for TM2 P26 TI2 TO3 Pulse signal output for TM3 P27 TI3 TO4 Pulse signal outp...

Page 58: ...Z Held Held Held Held Held A16 to A21 Hi Z Hi Z Hi Z Held Hi Z Held LBEN UBEN Hi Z Hi Z Hi Z Held Hi Z Held R W Hi Z Hi Z Hi Z H Hi Z H DSTB WRL WRH RD Hi Z Hi Z Hi Z H Hi Z H ASTB Hi Z Hi Z Hi Z H Hi...

Page 59: ...EGP0 and EGN0 registers a Port mode P00 to P07 can be set in 1 bit units as input or output pins according to the contents of the port 0 mode register PM0 b Control mode i NMI Non maskable Interrupt...

Page 60: ...SI0 SI1 Serial Input 0 1 input These are the serial receive data input pins of CSI0 and CSI1 ii SO0 SO1 Serial Output 0 1 output These are the serial transmit data output pins of CSI0 and CSI1 iii SC...

Page 61: ...al Output 2 3 output These are the serial transmit data output pins of CSI2 and CSI3 iii SCK2 SCK3 Serial Clock 2 3 3 state I O These are the serial clock I O pins of CSI2 and CSI3 iv SDA1 Serial Data...

Page 62: ...to A15 Address 13 to 15 output These comprise the address bus that is used for external access These pins operate as the A13 to A15 bit address output pins within a 22 bit address The output changes...

Page 63: ...l expansion mode P50 to P57 can be set as AD8 to AD15 according to the contents of the memory expansion register MM i AD8 to AD15 Address Data 8 to 15 3 state I O These comprise the multiplexed addres...

Page 64: ...ion faults Also do not apply voltage that is outside the range for AVSS and AVREF to pins that are being used as inputs for the A D converter If it is possible for noise above the AVREF range or below...

Page 65: ...inactive v ASTB Address Strobe output This is an output pin for the external address bus s latch strobe signal Output becomes active low level in synchronization with the falling edge of the clock du...

Page 66: ...mprise a real time output port ii A5 to A12 Address 5 to 12 output These comprise the address bus that is used for external access These pins operate as A5 to A12 bit address output pins within a 22 b...

Page 67: ...put is asynchronous input for a signal that has a constant low level width regardless of the operating clock s status When this signal is input a system reset is executed as the first priority ahead o...

Page 68: ...ept for the alternate function ports of the bus interface 24 VDD Power Supply These are the positive power supply pins All VDD pins should be connected to a positive power source 25 VSS Ground These a...

Page 69: ...CK1 ASCK0 EVDD 10 A P20 SI2 SDA1 10 A P21 SO2 26 P22 SCK2 SCL1 P23 SI3 RXD1 10 A P24 SO3 TXD1 26 P25 SCK3 ASCK1 10 A P26 P27 TI2 TO2 TI3 TO3 EVDD 8 A P30 P31 TI00 TI01 P32 P33 TI10 SI4 TI11 SO4 P34 TO...

Page 70: ...03 RTP0 A5 KR0 to RTP3 A8 KR3 P104 RTP4 A9 KR4 IERX P105 RTP5 A10 KR5 IETX P106 P107 RTP6 A11 KR6 RTP7 A12 KR7 EVDD 10 A P110 A1 WAIT P111 to P113 A2 to A4 EVDD 5 A Input Individually connect to EVDD...

Page 71: ...hat can be set for high impedance output both P ch and N ch off Type 8 A Type 5 Type 9 Pullup enable Input enable IN OUT Data Output disable N ch P ch P ch VDD VDD IN OUT Output disable N ch Data P ch...

Page 72: ...anual U13850EJ4V0UM 72 2 2 Type 10 A Type 26 Type 16 Pullup enable IN OUT Data Open drain Output disable N ch P ch P ch VDD VDD Pullup enable IN OUT Data Open drain Output disable N ch P ch P ch VDD V...

Page 73: ...tion time V850 SB1 50 ns 20 MHz internal operation V850 SB2 79 ns 12 58 MHz internal operation Address space 16 MB linear Thirty two 32 bit general purpose registers Internal 32 bit architecture Five...

Page 74: ...cture Figure 3 1 CPU Register Set r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 Zero Register Reserved for Address Register Stac...

Page 75: ...r0 Zero register Always holds 0 r1 Assembler reserved register Working register for generating 32 bit immediate r2 Address data variable register when r2 is not used by the real time OS r3 Stack point...

Page 76: ...nterrupt or NMI occurs this register will contain information referencing the interrupt source The higher 16 bits of this register are called FECC to which exception code of NMI is set The lower 16 bi...

Page 77: ...sts can be accepted when this bit is sets ID Indicates that accepting external interrupt request is disabled SAT This flag is set if the result of executing saturated operation instruction overflows I...

Page 78: ...ruction processing written in the internal ROM is started However external expansion mode that connects external device to external memory area is enabled by setting in the memory expansion mode regis...

Page 79: ...support up to 4 GB of linear address space data space during operand addressing data access When referencing instruction addresses linear address space program space of up to 16 MB is supported The CP...

Page 80: ...se the higher 8 bits of a 32 bit CPU address are ignored and the CPU address is only seen as a 24 bit external physical address the physical location xx000000H is equally referenced by multiple addres...

Page 81: ...ses Caution No instruction can be fetched from the 4 KB area of 00FFF000H to 00FFFFFFH because this area is defined as peripheral I O area Therefore do not execute any branch operation instructions in...

Page 82: ...ap xxFFFFFFH Internal peripheral I O area Internal RAM area Reserved On chip flash memory ROM area Internal peripheral I O area Internal RAM area External memory area On chip flash memory ROM area Sin...

Page 83: ...ited area Figure 3 10 Internal ROM Area 128 KB x x 0 F F F F F H x x 0 2 0 0 0 0 H x x 0 1 F F F F H x x 0 0 0 0 0 0 H Access prohibited area Internal ROM b V850 SB1 PD703033A 703033AY 70F3033A 70F303...

Page 84: ...F F H x x 0 6 0 0 0 0 H x x 0 5 F F F F H x x 0 0 0 0 0 0 H Access prohibited area Internal ROM b V850 SB1 PD703032A 703032AY 70F3032A 70F3032AY V850 SB2 PD703037A 703037AY 70F3037A 70F3037AY 512 KB a...

Page 85: ...ption Source 00000000H RESET 000001D0H INTTM6 00000010H NMI 000001E0H INTTM7 00000020H INTWDT 000001F0H INTIIC0 Note INTCSI0 00000040H TRAP0n n 0 to F 00000200H INTSER0 00000050H TRAP1n n 0 to F 00000...

Page 86: ...area Figure 3 14 Internal RAM Area 12 KB x x F F E F F F H x x F F C 0 0 0 H x x F F B F F F H x x F F 8 0 0 0 H Access prohibited area Internal RAM b V850 SB1 PD703033A 703033AY 70F3033A 70F3033AY V...

Page 87: ...x x F F E F F F H x x F F A 0 0 0 H x x F F 9 F F F H x x F F 8 0 0 0 H Access prohibited area Internal RAM b V850 SB1 PD703032A 703032AY 70F3032A 70F3032AY V850 SB2 PD703037A 703037AY 70F3037A 70F30...

Page 88: ...the peripheral I O area is referenced accessed in byte units the register at the next lowest even address 2n will be accessed 2 If a register that can be accessed in byte units is accessed in half wo...

Page 89: ...ed when the external expansion mode is specified In the area of other than the physical external memory the image of the physical external memory can be seen The internal RAM area and internal periphe...

Page 90: ...register MM The address bus A1 to A15 is set to multiplexed output with data bus D1 to D15 though separate output is also available by setting the memory address output mode register MAM see the User...

Page 91: ...r bits 4 to 7 are fixed to 0 Figure 3 21 Memory Expansion Mode Register MM Format After reset 00H R W Address FFFFF04CH Symbol 7 6 5 4 3 2 1 0 MM 0 0 0 0 MM3 MM2 MM1 MM0 MM3 P95 and P96 operation mode...

Page 92: ...output mode register MAM an in circuit emulator is not available Also setting the MAM register by software cannot switch to the separate bus For details refer to the relevant User s Manual of in circ...

Page 93: ...are valid Therefore a continuous 16 MB space starting from address 00000000H unconditionally corresponds to the memory map of the program space 2 Data space For the efficient use of resources to be p...

Page 94: ...External memory External memory Internal ROM xxFFFFFFH xxFFF400H xxFFF3FFH xxFFF000H xxFFEFFFH xxFFB000H xxFFAFFFH xxFF8000H xxFF7FFFH xx100000H xx0FFFFFH xx040000H xx03FFFFH xx800000H xx7FFFFFH xx00...

Page 95: ...rs 0 1 IICCL0 IICCL1 None Available None Available Slave address registers 0 1 SVA0 SVA1 None Available None Available IIC shift registers 0 1 IIC0 IIC1 None Available None Available IIC function expa...

Page 96: ...r PM6 3FH FFFFF032H Port 9 mode register PM9 7FH FFFFF034H Port 10 mode register PM10 FFH FFFFF036H Port 11 mode register PM11 1FH FFFFF040H Port alternate function control register PAC FFFFF04CH Memo...

Page 97: ...C5 FFFFF10EH Interrupt control register PIC6 FFFFF118H Interrupt control register WTNIIC FFFFF11AH Interrupt control register TMIC00 FFFFF11CH Interrupt control register TMIC01 FFFFF11EH Interrupt con...

Page 98: ...s register 0 DRA0 FFFFF184H DMA byte count register 0 DBC0 Undefined FFFFF186H DMA channel control register 0 DCHC0 00H FFFFF190H DMA peripheral I O address register 1 DIOA1 FFFFF192H DMA internal RAM...

Page 99: ...ter 10 PRM10 FFFFF218H 16 bit timer mode control register 1 TMC1 FFFFF21AH Capture compare control register 1 CRC1 FFFFF21CH Timer output control register 1 TOC1 FFFFF21EH Prescaler mode register 11 P...

Page 100: ...e connection only TM67 R FFFFF28CH 16 bit compare register 67 during cascade connection only CR67 0000H FFFFF28EH Timer clock selection register 61 TCL61 R W FFFFF290H 8 bit counter 7 TM7 R FFFFF292H...

Page 101: ...control register 1 BRGC1 R W 00H FFFFF316H Transmission shift register 1 TXS1 W FFFFF318H Reception buffer register 1 RXB1 R FFH FFFFF31EH Baud rate generator mode control register 10 BRGMC10 FFFFF32...

Page 102: ...FFFFF3C0H A D converter mode register 1 ADM1 FFFFF3C2H Analog input channel specification register ADS R W FFFFF3C4H A D conversion result register ADCR 0000H FFFFF3C6H A D conversion result register...

Page 103: ...SST instruction Bit manipulation instruction SET1 CLR1 NOT1 instruction 5 Return the PSW NP bit to 0 interrupt disable canceled 6 Insert the NOP instructions 2 or 5 instructions 7 If necessary enable...

Page 104: ...llowing cancellation of STOP IDLE mode rX Value to be written to PSW rY Value to be written back to PSW rD Value to be set to PSC When saving the value of PSW the value of PSW prior to setting the NP...

Page 105: ...located with status flags showing the operating state of the entire system This register can be read written in 8 or 1 bit units Figure 3 26 System Status Register SYS After reset 00H R W Address FFFF...

Page 106: ...ntrol Pins External Bus Interface Function Corresponding Port pins Address data bus AD0 to AD7 Port 4 P40 to P47 Address data bus AD8 to AD15 Port 5 P50 to P57 Address bus A1 to A4 Port 11 P110 to P11...

Page 107: ...3 2 1 0 SYC 0 0 0 0 0 0 0 BIC BIC Bus interface control 0 DSTB R W LBEN UBEN signal outputs 1 RD WRL WRH UBEN signal outputs 4 3 Bus Access 4 3 1 Number of access clocks The number of basic clocks ne...

Page 108: ...data External data bus a Access to even address 0 7 0 7 8 15 Byte data External data bus b Access to odd address 2 Halfword access 16 bits In halfword access to external memory data is dealt with as i...

Page 109: ...emory Block Block 15 Block 14 Block 13 Block 12 Block 11 Block 10 Block 9 Block 8 Block 7 Block 6 Block 5 Block 4 Block 3 Block 2 Block 1 Block 0 Internal peripheral I O area Internal RAM area Externa...

Page 110: ...ss FFFFF060H Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DWC Number of wait states to be inserted 0 0 0 0 1 1 1 0 2 1 1 3 n Blocks into which wait states are inserted 0 Blocks 0 1 1 Blocks 2 3 2 Bloc...

Page 111: ...WAIT pin are alternate function pins the wait function by the WAIT pin cannot be used when using a separate bus programmable wait can be used however Similarly a separate bus cannot be used when the...

Page 112: ...blocks 1 Bus cycle control register BCC This register can be read written in 16 bit units Figure 4 9 Bus Cycle Control Register BCC After reset AAAAH R W Address FFFFF062H Symbol 15 14 13 12 11 10 9 8...

Page 113: ...inactive high indicating that the request for the bus is cleared these pins are driven again During bus hold period the internal operation continues until the next external memory access The bus hold...

Page 114: ...DAK 1 8 Clears bus cycle start request pending 9 Start of bus cycle Nomal status Bus hold status Normal status 4 7 3 Operation in power save mode In the STOP or IDLE mode the system clock is stopped C...

Page 115: ...ignals Set these modes by using the BIC bit of the system control register SYC see Figure 4 1 Figure 4 11 Memory Read 1 4 a 0 wait T1 T2 T3 CLKOUT output A16 to A21 output AD0 to AD15 input output Add...

Page 116: ...ut A16 to A21 output AD0 to AD15 input output Address Address ASTB output R W output DSTB RD output UBEN LBEN output WAIT input WRH WRL output T3 Data H A1 to A15 output Address Remarks 1 indicates th...

Page 117: ...output A1 to A15 output AD0 to AD15 input output Address Address ASTB output R W output DSTB RD output UBEN LBEN output WAIT input WRH WRL output H TI Data A16 to A21 output Address Remarks 1 indicat...

Page 118: ...output A1 to A15 output AD0 to AD15 input output Address Address ASTB output R W output DSTB RD output UBEN LBEN output WAIT input WRH WRL output T3 Data TI H A16 to A21 output Address Remarks 1 indic...

Page 119: ...utput R W output DSTB output UBEN LBEN output WAIT input RD output WRH WRL output H A1 to A15 output Address Note AD0 to AD7 output invalid data when odd address byte data is accessed AD8 to AD15 outp...

Page 120: ...TB output UBEN LBEN output WAIT input RD output WRH WRL output T3 DataNote Address H A1 to A15 output Address Note AD0 to AD7 output invalid data when odd address byte data is accessed AD8 to AD15 out...

Page 121: ...s Address Data Address ASTB output Undefined Address Note 1 Note 2 Notes 1 If HLDRQ signal is inactive high level at this sampling timing bus hold state is not entered 2 If transferred to bus hold sta...

Page 122: ...access instruction fetch branch and instruction fetch continuous in that order The instruction fetch cycle may be inserted in between the read access and write access in read modify write access No in...

Page 123: ...ory 2 A prefetch operation straddling over the on chip peripheral I O area invalid fetch does not take place if a branch instruction exists at the upper limit address of the internal RAM area 4 10 2 D...

Page 124: ...e exception or by generation of an exception event fetching of an illegal op code 5 1 1 Features Interrupts Non maskable interrupts 2 sources Maskable interrupts the number of maskable interrupt sourc...

Page 125: ...PIC4 6 INTP5 INTP5 pin Pin 00E0H 000000E0H nextPC PIC5 7 INTP6 INTP6 pin Pin 00F0H 000000F0H nextPC PIC6 8 INTWTNI Watch timer prescaler WT 0140H 00000140H nextPC WTNIIC 9 INTTM00 INTTM00 TM0 0150H 00...

Page 126: ...MA2 transfer end DMA2 02E0H 000002E0H nextPC DMAIC2 35 INTDMA3 DMA3 transfer end DMA3 02F0H 000002F0H nextPC DMAIC3 36 INTDMA4 DMA4 transfer end DMA4 0300H 00000300H nextPC DMAIC4 37 INTDMA5 DMA5 tran...

Page 127: ...the non maskable interrupt INTWDT only in the state that the WDTM4 bit of the watchdog timer mode register WDTM is set to 1 While the service routine of the non maskable interrupt is being executed P...

Page 128: ...exception code 0010H to the higher half word FECC of ECR 4 Sets the NP and ID bits of PSW and clears the EP bit 5 Loads the handler address 00000010H 00000020H of the non maskable interrupt routine to...

Page 129: ...quest NMI request PSW NP 1 NMI request pending because PSW NP 1 Pending NMI request processed b If a new NMI request is generated twice while an NMI service routine is executing Main routine NMI reque...

Page 130: ...of PSW is 1 2 Transfers control back to the address of the restored PC and PSW How the RETI instruction is processed is shown below Figure 5 3 RETI Instruction Processing PSW EP RETI instruction PC PS...

Page 131: ...31 8 7 6 5 4 3 2 1 0 PSW 0 NP EP ID SAT CY OV S Z NP NMI servicing state 0 No NMI interrupt servicing 1 NMI interrupt currently servicing 5 2 4 Noise eliminator of NMI pin NMI pin noise is eliminated...

Page 132: ...is specified by using the EGP0 and EGN0 registers When using P00 as an output port set the NMI valid edge to detects neither rising nor falling edge Figure 5 5 Rising Edge Specification Register 0 EGP...

Page 133: ...y interrupts with the same priority level cannot be nested To use multiple interrupts it is necessary to save EIPC and EIPSW to memory or a register before executing the EI instruction and restore EIP...

Page 134: ...accepted CPU processing Mask Yes No PSW ID 0 Priority higher than that of interrupt currently serviced Interrupt request pending PSW NP PSW ID Interrupt request pending No No No No 1 0 1 0 INT input Y...

Page 135: ...W is 0 2 Transfers control to the address of the restored PC and PSW The processing of the RETI instruction is shown below Figure 5 8 RETI Instruction Processing RETI instruction Restores original pro...

Page 136: ...on bit xxPRn When two or more interrupts having the same priority level specified by xxPRn are generated at the same time interrupts are serviced in order depending on the priority level allocated to...

Page 137: ...held pending even if interrupts are enabled because its priority is the same as that of g Interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of...

Page 138: ...ervicing of p Servicing of q Servicing of r EI If levels 3 to 0 are acknowledged Interrupt request j is held pending because its priority is lower than that of i k that occurs after j is acknowledged...

Page 139: ...t control register can be read written in 8 or 1 bit units Caution If the following three conditions conflict interrupt servicing is executed twice However when DMA is not used interrupt servicing is...

Page 140: ...upt mask flag 0 Enables interrupt servicing 1 Disables interrupt servicing pending xxPRn2 xxPRn1 xxPRn0 Interrupt priority specification bit 0 0 0 Specifies level 0 highest 0 0 1 Specifies level 1 0 1...

Page 141: ...TMPR61 TMPR60 FFFFF12CH TMIC7 TMIF7 TMMK7 0 0 0 TMPR72 TMPR71 TMPR70 FFFFF12EH CSIC0 CSIF0 CSMK0 0 0 0 CSPR02 CSPR01 CSPR00 FFFFF130H SERIC0 SERIF0 SERMK0 0 0 0 SERPR02 SERPR01 SERPR00 FFFFF132H CSIC...

Page 142: ...y n not acknowledged 1 Interrupt request with priority n acknowledged Remark n 0 to 7 priority level 5 3 6 Maskable interrupt status flag The interrupt disable status flag ID of the PSW controls the e...

Page 143: ...noise eliminator that functions via an analog delay Therefore a signal input to each pin is not detected as an edge unless it maintains its input level for a certain period An edge is detected after a...

Page 144: ...nput within these 3 clocks an interrupt request may occur Therefore be careful of the following things when using the interrupt and DMA functions When using the interrupt function after the sampling c...

Page 145: ...gister 0 EGP0 and the validity of the falling edge is controlled by falling edge specification register 0 EGN0 Refer to Figures 5 5 and 5 6 for details of EGP0 and EGN0 After reset the valid edge of t...

Page 146: ...rocessing and transfers control to the handler routine 1 Saves the restored PC to EIPC 2 Saves the current PSW to EIPSW 3 Writes an exception code to the lower 16 bits EICC of ECR interrupt source 4 S...

Page 147: ...f PSW is 1 2 Transfers control to the address of the restored PC and PSW The processing of the RETI instruction is shown below Figure 5 17 RETI Instruction Processing PSW EP RETI instruction PC PSW EI...

Page 148: ...is considered as an exception trap Illegal op code exception Occurs if the sub op code field of an instruction to be executed next is not a valid op code 5 5 1 Illegal op code definition An illegal op...

Page 149: ...anual U13850EJ4V0UM 149 How the exception trap is processed is shown below Figure 5 20 Exception Trap Processing Exception trap ILGOP occurs EIPC EIPSW ECR EICC PSW EP PSW ID PC Restored PC PSW Except...

Page 150: ...it of PSW is 1 2 Transfers control to the address of the restored PC and PSW The processing of the RETI instruction is shown below Figure 5 21 RETI Instruction Processing RETI instruction Jump to PC P...

Page 151: ...hat allows the nesting of interrupts If a higher priority interrupt is generated and acknowledged it will be allowed to stop a current interrupt service routine in progress Execution of the original r...

Page 152: ...gister EI instruction enables interrupt acknowledgement DI instruction disables interrupt acknowledgement Restores saved value to EIPSW Restores saved value to EIPC RETI instruction Saves EIPC to memo...

Page 153: ...et to 7 by the xxPRn0 to xxPRn2 bits Priorities of maskable interrupts High Level 0 Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Low Interrupt servicing that has been suspended as a result...

Page 154: ...necessary for external interrupts except when In IDLE STOP mode External bus is accessed Two or more interrupt request non sample instructions are executed in succession Access to interrupt control re...

Page 155: ...wever the following instructions are not included IDLE STOP mode setting instructions EI and DI instructions RETI instruction LDSR instruction vs PSW register Instruction that accesses interrupt contr...

Page 156: ...e 5 23 Key Return Mode Register KRM After reset 00H R W Address FFFFF3D0H 7 6 5 4 3 2 1 0 KRM KRM7 KRM6 KRM5 KRM4 0 0 0 KRM0 KRMn Key return mode control 0 Does not detect key return signal 1 Detects...

Page 157: ...5 INTERRUPT EXCEPTION PROCESSING FUNCTION User s Manual U13850EJ4V0UM 157 Figure 5 24 Key Return Block Diagram INTKR Key return mode register KRM KRM7 KRM6 KRM5 KRM4 0 0 0 KRM0 KR7 KR6 KR5 KR4 KR3 KR2...

Page 158: ...he main oscillator is stopped by inputting a reset or executing a STOP instruction the oscillation stabilization time is secured after the stop mode is canceled This oscillation stabilization time is...

Page 159: ...ck Generator fXT fXT fXX 8 fXX STOP MCK FRC Prescaler Prescaler X2 X1 XT2 XT1 IDLE Main system clock oscillator Subsystem clock oscillator IDLE control IDLE control Selector Clock supplied to watch ti...

Page 160: ...0 bits of PCC register is disabled 6 3 1 Control registers 1 Processor clock control register PCC This is a specific register It can be written to only when a specified combination of sequences is use...

Page 161: ...um number of the following instructions is required before sub clock operation after the CK2 bit is set CPU clock frequency before setting sub clock frequency 2 Therefore insert the wait described abo...

Page 162: ...fter reset C0H R W Address FFFFF070H 7 6 5 4 3 2 1 0 PSC DCLK1 DCLK0 0 0 0 IDLE STP 0 DCLK1 DCLK0 Specification of CLKOUT pin s operation 0 0 Output enabled 0 1 Setting prohibited 1 0 Setting prohibit...

Page 163: ...Time Selection Register OSTS After reset 04H R W Address FFFFF380H 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 Selection of oscillation stabilization time fXX OSTS2 OSTS1 OSTS0 Clock 20 MHz Note...

Page 164: ...nceled there is no need for the oscillator to wait for the oscillation stabilization time so normal operation can be resumed quickly When the power saving control register PSC s IDLE bit is set to 1 t...

Page 165: ...ng via either the main clock or sub clock The operating statuses in the HALT mode are listed in Table 6 1 2 Cancellation of HALT mode HALT mode can be canceled by an NMI request an unmasked maskable i...

Page 166: ...pped 8 bit timer TM4 Operating Operates when fXT is selected for count clock 8 bit timer TM5 Operating Operates when fXT is selected for count clock 8 bit timer TM6 Operating Stopped 8 bit timer TM7 O...

Page 167: ...ng INTP0 to INTP3 Operating INTP4 and INTP5 Operating Stopped External interrupt request INTP6 Operating Operation when sampling clock fXT is selected Key return function Operating AD0 to AD15 High im...

Page 168: ...nterrupt request or a RESET input Table 6 2 Operating Statuses in IDLE Mode 1 2 IDLE Mode Settings When Sub Clock Exists When Sub Clock Does Not Exist CPU Stopped ROM correction Stopped Clock generato...

Page 169: ...ists When Sub Clock Does Not Exist External bus interface Stopped NMI Operating INTP0 to INTP3 Operating INTP4 and INTP5 Stopped External interrupt request INTP6 Operates when fXT is selected for samp...

Page 170: ...e interrupt an unmasked interrupt request or a RESET input When the STOP mode is canceled an oscillation stabilization time is secured Table 6 3 Operating Statuses in Software STOP Mode 1 2 STOP Mode...

Page 171: ...tput Operates when INTTM4 or INTTM5 has been selected when TM4 or TM5 is operating Stopped Port function Held External bus interface Stopped NMI Operating INTP0 to INTP3 Operating INTP4 and INTP5 Stop...

Page 172: ...pt is input the counter watchdog timer starts counting and the count time is the length of time that must elapse for stabilization of the oscillator s clock output Oscillation stabilization time WDT c...

Page 173: ...egister is 1 during interrupt request servicing DI instruction set by software If the power save mode is released by an interrupt request with a priority the same as or lower than the interrupt reques...

Page 174: ...ator and support of edge specifications Timer output operated by match detection 1 each TOn When using the P34 TO0 and P35 TO1 pins as TO0 and TO1 timer outputs set the value of port 3 P3 to 0 port mo...

Page 175: ...tch Match Clear 16 bit timer mode control register n TMCn TOn INTTMn1 INTTMn0 3 Timer output control register n TOCn fXX 2 Selector Selector Selector Selector PRMn2 Prescaler mode register n1 PRMn1 No...

Page 176: ...ntrol registers 0 1 TOC0 TOC1 Prescaler mode registers n0 n1 PRMn0 PRMn1 1 16 bit timer registers 0 1 TM0 TM1 TMn is a 16 bit read only register that counts count pulses The counter is incremented in...

Page 177: ...e 7 2 When the valid edge for TIn1 pin is specified as the capture trigger refer to Table 7 3 Table 7 2 Valid Edge of TIn0 Pin and Capture Trigger of CRn0 ESn01 ESn00 Valid Edge of TIn0 Pin CRn0 Captu...

Page 178: ...ter When the capture trigger is specified as the valid edge of TIn0 the relationship between the TIn0 valid edge and the CRn1 capture trigger is as follows Table 7 4 TIn0 Pin Valid Edge and CRn1 Captu...

Page 179: ...de registers n0 n1 PRMn0 PRMn1 1 16 bit timer mode control registers 0 1 TMC0 TMC1 TMCn specifies the operation mode of the 16 bit timer and the clear mode output timing and overflow detection of 16 b...

Page 180: ...n and CRn0 or match between TMn and CRn1 0 1 1 Match between TMn and CRn0 match between TMn and CRn1 or valid edge of TIn0 1 0 0 Clears and starts at valid edge of TIn0 Match between TMn and CRn0 or m...

Page 181: ...ers 0 1 CRC0 CRC1 After reset 00H R W Address FFFFF20AH FFFFF21AH 7 6 5 4 3 2 1 0 CRCn 0 0 0 0 0 CRCn2 CRCn1 CRCn0 n 0 1 CRCn2 Selects operation mode of CRn1 0 Operates as compare register 1 Operates...

Page 182: ...Rn TOCn1 TOEn n 0 1 OSPTn Controls output trigger of one shot pulse by software 0 No one shot pulse trigger 1 Uses one shot pulse trigger OSPEn Controls one shot pulse output operation 0 Successive pu...

Page 183: ...egister 00 PRM00 After reset 00H R W Address FFFFF206H 7 6 5 4 3 2 1 0 PRM00 ES011 ES010 ES001 ES000 0 0 PRM01 PRM00 ES011 ES010 Selects valid edge of TI01 0 0 Falling edge 0 1 Rising edge 1 0 Setting...

Page 184: ...y the valid edge of TI0n to clear and start the timer and as a capture trigger 2 Before setting data to PRM0n always stop the timer operation 3 If the 16 bit timer TM0 operation is enabled by specifyi...

Page 185: ...ge of TI11 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges ES101 ES100 Selects valid edge of TI10 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1...

Page 186: ...y the valid edge of TI1n to clear and start the timer and as a capture trigger 2 Before setting data to PRM1n always stop the timer operation 3 If the 16 bit timer TM1 operation is enabled by specifyi...

Page 187: ...unting At the same time an interrupt request signal INTTMn0 is generated The count clock of the 16 bit timer event counter can be selected by bits 0 and 1 PRMn0 and PRMn1 of prescaler mode register n0...

Page 188: ...11 Timing of Interval Timer Operation TMn count value CRn0 0000H 0001H N N N N N N N 0000H 0001H 0000H 0001H Count start Clear Clear Interrupt acknowledgement Interrupt acknowledgement INTTMn0 TOn Int...

Page 189: ...tput Operation a 16 bit timer mode control registers 0 1 TMC0 TMC1 TMCn3 TMCn2 TMCn1 OVFn TMCn 0 0 0 0 1 1 0 0 Clears and starts on match between TMn and CRn0 b Capture compare control registers 0 1 C...

Page 190: ...using bits 6 and 7 ESn10 and ESn11 of prescaler mode register n0 PRMn0 The rising edge falling edge or both the rising and falling edges can be selected The valid edge is detected through sampling at...

Page 191: ...connected to ports 2 n 0 1 Figure 7 15 Timing of Pulse Width Measurement with Free Running Counter and One Capture Register with Both Edges Specified t Value loaded to CRn1 TIn0 pin input TMn count va...

Page 192: ...e specified by bits 4 and 5 ESn00 and ESn01 and bits 6 and 7 ESn10 and ESn11 of PRMn0 respectively The rising falling or both rising and falling edges can be specified The valid edge is detected throu...

Page 193: ...e Specified Count clock TMn TIn0 CRn1 INTTMn1 n 1 n n 1 n 2 n 3 n Rising edge detection Remark n 0 1 Figure 7 18 Timing of Pulse Width Measurement with Free Running Counter with Both Edges Specified t...

Page 194: ...id edge of TIn0 is detected through sampling at a count clock cycle selected by prescaler mode register n0 n1 PRMn0 PRMn1 and the capture operation is not performed until the valid level is detected t...

Page 195: ...e measured by clearing 16 bit timer register n TMn once and then resuming counting after loading the count value of TMn to 16 bit capture compare register n1 CRn1 See Figure 7 22 The edge is specified...

Page 196: ...0 0 0 1 1 1 CRn0 as capture register Captures to CRn0 at edge reverse to valid edge of TIn0 CRn1 as capture register Remark 0 1 When these bits are reset to 0 or set to 1 other functions can be used a...

Page 197: ...ster n0 PRMn0 The rising falling or both the rising and falling edges can be specified The valid edge is detected through sampling at a count clock cycle of fXX 2 and the capture operation is not perf...

Page 198: ...t Counter Operation with Rising Edge Specified TIn0 pin input TMn count value CRn0 INTTMn0 0001H 0000H N 1 N N 0003H 0002H 0005H 0004H 0001H 0000H 0003H 0002H Caution Read TMn when reading the count v...

Page 199: ...CRCn 0 0 0 0 0 0 1 0 1 1 CRn0 as compare register c 16 bit timer output control registers 0 1 TOC0 TOC1 OSPTn OSPEn TOCn4 LVSn LVRn TOCn1 TOEn TOCn 0 0 0 0 0 1 0 1 1 1 Enables TOn output Reverses out...

Page 200: ...ut control register n TOCn as shown in Figure 7 28 and by setting bit 6 OSPTn of TOCn by software By setting OSPTn to 1 the 16 bit timer event counter is cleared and started and its output is asserted...

Page 201: ...ter CRn1 as compare register c 16 bit timer output control registers 0 1 TOC0 TOC1 OSPTn OSPEn TOCn4 LVSn LVRn TOCn1 TOEn TOCn 0 0 1 1 0 1 0 1 1 1 Enables TOn output Reverses output on match between T...

Page 202: ...bit timer output control register n TOCn as shown in Figure 7 30 and by using the valid edge of the TIn0 pin as an external trigger The valid edge of the TIn0 pin is specified by bits 4 and 5 ESn00 a...

Page 203: ...0 CRn0 as compare register CRn1 as compare register c 16 bit timer output control registers 0 1 TOC0 TOC1 OSPTn OSPEn TOCn4 LVSn LVRn TOCn1 TOEn TOCn 0 0 1 1 0 1 0 1 1 1 Enables TOn output Reverses ou...

Page 204: ...fied Count clock TMn count value 0000H 0001H N 1 M 2 N 2 M 1 M 1 M Value to set CRn1 N Value to set CRn0 M TIn0 pin input INTTMn1 INTTMn0 TOn pin output Sets 08H to TMCn TMn count starts 0000H N M 2 N...

Page 205: ...pulse count operation is disabled when these registers are used as event counters 3 Setting compare register during timer count operation If the value to which the current value of 16 bit capture comp...

Page 206: ...Cn3 of 16 bit timer mode control register n to 0 0 Set the valid edge by using bits 4 and 5 ESn00 and ESn01 of prescaler mode register n0 PRMn0 6 Re triggering one shot pulse a One shot pulse output b...

Page 207: ...6 bit capture compare registers n0 and n1 CRn0 CRn1 are used as capture registers if the read period and capture trigger input conflict the capture trigger has priority The read data of CRn0 and CRn1...

Page 208: ...iting 16 bit timer capture compare registers n0 and n1 CRn0 CRn1 if the value is close to or larger than the timer value the match interrupt request generation or clear operation may not be performed...

Page 209: ...Mode using timer alone individual mode The timer operates as an 8 bit timer event counter It can have the following functions Interval timer External event counter Square wave output PWM output 2 Mode...

Page 210: ...connecting in cascade Registers 8 bit compare registers 2 to 7 CR20 to CR70 16 bit compare registers 23 45 67 CR23 CR45 CR67 Only when connecting in cascade Timer outputs TO2 to TO5 Control registers...

Page 211: ...d CRn0 match in the clear and start mode that occurs when TMn and CRn0 match Caution When connected in cascade these registers become 00H even when TCEn in the lower timers TM2 TM4 TM6 is cleared Rema...

Page 212: ...mer n Timer clock selection registers n0 n1 TCLn0 TCLn1 8 bit timer mode control register n TMCn 1 Timer clock selection registers 20 to 71 and 21 to 71 TCL20 to TCL70 and TCL21 to TCL71 These registe...

Page 213: ...edge 0 0 1 0 fXX 4 200 ns 318 ns 0 0 1 1 fXX 8 400 ns 636 ns 0 1 0 0 fXX 16 800 ns 1 3 s 0 1 0 1 fXX 32 1 6 s 2 5 s 0 1 1 0 fXX 128 6 4 s 10 2 s 0 1 1 1 fXX 512 25 6 s 40 7 s 1 0 0 0 Setting prohibite...

Page 214: ...edge 0 0 1 0 fXX 4 200 ns 318 ns 0 0 1 1 fXX 8 400 ns 636 ns 0 1 0 0 fXX 16 800 ns 1 3 s 0 1 0 1 fXX 32 1 6 s 2 5 s 0 1 1 0 fXX 128 6 4 s 10 2 s 0 1 1 1 fXT Sub clock 30 5 s 30 5 s 1 0 0 0 Setting pr...

Page 215: ...prohibited 0 0 1 0 fXX 4 200 ns 318 ns 0 0 1 1 fXX 8 400 ns 636 ns 0 1 0 0 fXX 16 800 ns 1 3 s 0 1 0 1 fXX 32 1 6 s 2 5 s 0 1 1 0 fXX 64 3 2 s 5 1 s 0 1 1 1 fXX 128 6 4 s 10 2 s 1 0 0 0 Setting prohib...

Page 216: ...e operating mode of 8 bit counter n TMn 3 Selects the individual mode or cascade connection mode 4 Sets the state of the timer output flip flop 5 Controls the timer flip flop or selects the active lev...

Page 217: ...when n 2 4 6 1 Cascade connection mode connection to lower timer LVSm LVRm Setting state of timer output flip flop 0 0 Not change 0 1 Reset timer output flip flop to 0 1 0 Set timer output flip flop...

Page 218: ...d by bit 0 TCLn3 in timer clock selection register n1 TCLn1 n 2 to 7 Setting method 1 Set each register TCLn0 TCLn1 Selects the count clock CRn0 Compare value TMCn Selects the clear and start mode whe...

Page 219: ...imer Operation 2 3 When CRn0 00H Remark n 2 to 7 When CRn0 FFH 01H FEH FFH 00H FEH FFH 00H FFH FFH FFH Count clock TMn CRn0 TCEn INTTMn TOn Interrupt acknowledgement Interval time t Interrupt acknowle...

Page 220: ...Operation 3 3 Operated by CRn0 transition M N Remark n 2 to 7 Operated by CRn0 transition M N Remark n 2 to 7 Count clock CRn0 TCEn INTTMn TOn TMn 00H FFH M M 00H 00H N N M CRn0 transition TMn overfl...

Page 221: ...is incremented The edge setting can be selected to be either a rising or falling edge If the total of TMn and the value of 8 bit compare register n CRn0 match TMn is cleared to 0 and the interrupt req...

Page 222: ...k CRn0 Compare value TMCn Clear and start mode when TMn and CRn0 match LVSn LVRn Setting State of Timer Output Flip Flop 1 0 High level output 0 1 Low level output Inversion of timer output flip flop...

Page 223: ...re register n CRn0 are output from TOn Set the width of the active level of the PWM pulse in CRn0 The active level can be selected by bit 1 TMCn1 in TMCn The count clock can be selected by bits 0 to 2...

Page 224: ...ounting starts When counting stops set TCEn to 0 PWM output operation 1 When counting starts the PWM output output from TOn outputs the inactive level until an overflow occurs 2 When the overflow occu...

Page 225: ...Inactive level Active level 01H FFH 00H 01H 02H N N 1 FFH 00H 01H 02H M 00H N When CRn0 0 Count clock TMn CRn0 TCEn INTTMn TOn Inactive level Inactive level 00H 01H FFH 00H 01H 02H N N 1 N 2 FFH 00H 0...

Page 226: ...ransition N M M 1 M N M H M 2 02H 01H 00H FFH M 1 M M 2 When the CRn0 value changes from N to M after TMn overflows INTTMn N 1 02H 01H 00H FFH N N 2 TMn CRn0 TCEn TOn Count clock CRn0 transition N M N...

Page 227: ...TM3 cascade connection 1 Setting registers TCL20 TCL21 Select the count clock for TM2 setting not necessary for TM3 because of cascade connection CR20 CR30 Compare value 00H to FFH can be set for com...

Page 228: ...below Figure 7 46 Cascade Connection Mode with 16 Bit Resolution N 1 N 00H 01H TMn Count clock Enable operation starting count 00H FFH FFH 01H 00H FFH 00H 00H N 01H 00H A 00H TMn 1 01H M M 1 02H 00H 0...

Page 229: ...n counting continues overflows and counting starts again from 0 Consequently when the value M after CRn0 changes is less than the value N before the change the timer must restart after CRn0 changes n...

Page 230: ...ram of Watch Timer fW 210 Selector 11 bit prescaler fW 28 fW 27 fW 26 fW 25 fW 24 5 bit counter INTWTN INTWTNI WTNM0 WTNM1 WTNM3 WTNM4 WTNM5 WTNM6 WTNM7 Watch timer mode control register WTNM fXX Inte...

Page 231: ...ed in advance Table 8 1 Interval Time of Interval Timer Interval Time fXT 32 768 kHz 2 4 1 fW 488 s 2 5 1 fW 977 s 2 6 1 fW 1 95 ms 2 7 1 fW 3 91 ms 2 8 1 fW 7 81 ms 2 9 1 fW 15 6 ms 2 10 1 fW 31 2 ms...

Page 232: ...bit memory manipulation instruction RESET input clears WTNM to 00H Figure 8 2 Watch Timer Mode Control Register WTNM After reset 00H R W Address FFFFF360H 7 6 5 4 3 2 1 0 WTNM WTNM7 WTNM6 WTNM5 WTNM4...

Page 233: ...clears WTNCS to 00H Caution Do not change the count clock during a watch timer operation Figure 8 3 Watch Timer Clock Selection Register WTNCS After reset 00H R W Address FFFFF364H 7 6 5 4 3 2 1 0 WTN...

Page 234: ...15 6 ms may occur at this time Setting the WTNM0 bit to 0 can clear the interval timer However an error up to 0 5 sec may occur after a watch timer overflow INTWTN because the 5 bit counter is also cl...

Page 235: ...timer interrupt INTWTNI nT nT Remark fW Watch timer clock frequency fW 32 768 kHz n Interval timer operation counts 8 4 3 Cautions It takes some time to generate the first watch timer interrupt reque...

Page 236: ...r WDTM to select the watchdog timer mode or the interval timer mode Figure 9 1 Block Diagram of Watchdog Timer Internal bus OSTS0 OSTS1 OSTS2 OSTS WDTM4 RUN WDTM WDCS WDCS0 WDCS1 WDCS2 3 INTWDTNote 1...

Page 237: ...XX 1 6 ms 2 6 ms 2 16 fXX 3 3 ms 5 2 ms 2 17 fXX 6 6 ms 10 4 ms 2 18 fXX 13 1 ms 20 8 ms 2 19 fXX 26 2 ms 41 6 ms 2 20 fXX 52 4 ms 83 3 ms 2 22 fXX 209 7 ms 333 4 ms Note Only for the V850 SB1 2 Inter...

Page 238: ...r WDTM 1 Oscillation stabilization time selection register OSTS This register selects the oscillation stabilization time after a reset is applied or the STOP mode is released until the oscillation is...

Page 239: ...hdog Timer Clock Selection Register WDCS After reset 00H R W Address FFFFF382H 7 6 5 4 3 2 1 0 WDCS 0 0 0 0 0 WDCS2 WDCS1 WDCS0 Watchdog timer interval timer overflow time fXX WDCS2 WDCS1 WDCS0 Clock...

Page 240: ...r Note 1 0 Disable count 1 Clear count and start counting WDTM4 Operating mode selection for the watchdog timer Note 2 0 Interval timer mode If an overflow occurs a maskable interrupt INTWDTM is gener...

Page 241: ...tops running in the STOP mode and IDLE mode Consequently set RUN to 1 and clear the watchdog timer before entering the STOP mode or IDLE mode Do not set the watchdog timer when operating the HALT mode...

Page 242: ...P mode and IDLE mode Therefore after the RUN bit of WDTM register is set to 1 and the interval timer is cleared before entering the STOP mode IDLE mode execute the STOP instruction Cautions 1 Once bit...

Page 243: ...80H 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection fXX OSTS2 OSTS1 OSTS0 Clock 20 MHz Note 12 58 MHz 0 0 0 2 14 fXX 819 2 s 1 3 ms 0 0 1 2 16 fXX 3 3 ms 5 2...

Page 244: ...ial I O or I 2 C can be used as a serial interface 10 2 3 Wire Serial I O CSI0 to CSI3 CSIn n 0 to 3 has the following two modes 1 Operation stop mode This mode is used when serial transfers are not p...

Page 245: ...llows When n 0 or 3 TM2 When n 1 or 2 TM3 1 Serial I O shift registers 0 to 3 SIO0 to SIO3 SIOn is an 8 bit register that performs parallel serial conversion and serial transmit receive shift operatio...

Page 246: ...ial operation mode register n CSIMn Serial clock selection register n CSISn 1 Serial operation mode registers 0 to 3 CSIM0 to CSIM3 CSIMn is used to enable or disable serial interface channel n s seri...

Page 247: ...On write Normal output 1 Receive only mode SIOn read Port function SCLn2 SCLn1 SCLn0 Clock selection 0 0 0 External clock input SCKn 0 0 1 at n 0 3 Output of TO2 at n 1 2 Output of TO3 0 1 0 fXX 8 0 1...

Page 248: ...l clock CSISn can be set by an 8 bit memory manipulation instruction RESET input clears these registers to 00H Figure 10 3 Serial Clock Selection Registers 0 to 3 CSIS0 to CSIS3 After reset 00H R W Ad...

Page 249: ...SCKn pin are also used as I O ports they can be used as normal I O ports as well a Register settings Operation stop mode are set via the CSIEn bit of serial operation mode register n CSIMn Figure 10 4...

Page 250: ...CSIM0 FFFFF2A2H CSIM1 FFFFF2B2H CSIM2 FFFFF2C2H CSIM3 FFFFF2D2H 7 6 5 4 3 2 1 0 CSIMn CSIEn 0 0 0 0 MODEn SCLn1 SCLn0 n 0 to 3 SIOn operation enable disable specification CSIEn Shift register operati...

Page 251: ...I3 DI2 DI1 DI0 INTCSIn Serial clock 1 SO0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 2 3 4 5 6 7 8 Transfer completion Transfer starts in synchronization with the serial clock s falling edge c Transfer start A s...

Page 252: ...when serial transfers are not performed It can therefore be used to reduce power consumption 2 I 2 C bus mode multimaster support This mode is used for 8 bit data transfers with several devices via tw...

Page 253: ...ime correction circuit ACK detector Wake up controller ACK detector Stop condition detector Serial clock counter Interrupt request signal generator Serial clock controller Serial clock wait controller...

Page 254: ...tion example is shown below Figure 10 8 Serial Bus Configuration Example Using I 2 C Bus SDA SCL SDA VDD VDD SCL SDA SCL Slave CPU3 Address 3 SDA SCL Slave IC Address 4 SDA SCL Slave IC Address N Mast...

Page 255: ...n n 0 1 Write and read operations to IICn are used to control the actual transmit and receive operations IICn is set by an 8 bit memory manipulation instruction RESET input clears IIC0 and IIC1 to 00H...

Page 256: ...WTIMn bit Bit 3 of IIC control register n IICCn SPIEn bit Bit 4 of IIC control register n IICCn Remark n 0 1 8 Serial clock controller In master mode this circuit generates the clock output via the SC...

Page 257: ...also used IIC shift registers 0 1 IIC0 IIC1 Slave address registers 0 1 SVA0 SVA1 1 IIC control registers 0 1 IICC0 IICC1 IICCn is used to enable disable I 2 C operations set wait timing and set othe...

Page 258: ...de cases in which a locally irrelevant extension code has been received The SCLn and SDAn lines are set to high impedance The following flags are cleared STDn ACKDn TRCn COIn EXCn MSTSn STTn SPTn The...

Page 259: ...ode After output of eight clocks clock output is set to low level and wait is set Slave mode After input of eight clocks the clock is set to low level and wait is set for master device 1 Interrupt req...

Page 260: ...Next after the rated amount of time has elapsed SCLn is changed to low level When bus is not used This trigger functions as a start condition reserve flag When set it releases the bus and then automat...

Page 261: ...STTn SPTn can be set only when in master mode Note When WTIMn has been set to 0 if SPTn is set during the wait period that follows output of eight clocks note that a stop condition will be generated...

Page 262: ...0 Condition for setting MSTSn 1 When a stop condition is detected When ALDn 1 Cleared by LRELn 1 When IICEn changes from 1 to 0 When RESET is input When a start condition is generated ALDn Detection o...

Page 263: ...address SVAn set at the rising edge of the eighth clock TRCn Detection of transmit receive status 0 Receive status other than transmit status The SDAn line is set for high impedance 1 Transmit status...

Page 264: ...as detected This indicates that the address transfer period is in effect Condition for clearing STDn 0 Condition for setting STDn 1 When a stop condition is detected At the rising edge of the next byt...

Page 265: ...0 SCLn line was detected at low level 1 SCLn line was detected at high level Condition for clearing CLDn 0 Condition for setting CLDn 1 When the SCLn line is at low level When IICEn 0 When RESET is i...

Page 266: ...et the IICCEn1 and IICCEn0 bits in combination with the SMCn CLn1 and CLn0 bits of IIC clock selection register n IICCLn and the CLXn bit of IIC function expansion register n IICXn see 10 3 2 6 I 2 Cn...

Page 267: ...fXX 12 4 0 MHz to 4 19 MHz x x 0 1 0 x fXX 24 4 0 MHz to 8 38 MHz x x 0 1 1 0 fXX 48 8 0 MHz to 16 67 MHz 0 1 0 1 1 1 fXX 36 12 0 MHz to 13 4 MHz 1 0 0 1 1 1 fXX 54 16 0 MHz to 20 0 MHz Note n 0 TM2 o...

Page 268: ...dress Register n SVAn 10 3 3 I 2 C bus mode functions 1 Pin configuration The serial clock pin SCLn and serial data bus pin SDAn are configured as follows n 0 1 SCLn This pin is used for serial clock...

Page 269: ...he start condition data and stop condition output via the I 2 C bus s serial data bus is shown below Figure 10 17 I 2 C Bus s Serial Data Transfer Timing 1 to 7 8 9 1 to 7 8 9 1 to 7 8 9 SCL SDA Start...

Page 270: ...The 7 bits of data that follow the start condition are defined as an address An address is a 7 bit data segment that is output in order to select one of the slave devices that are connected to the ma...

Page 271: ...ess data the master device sends 1 bit that specifies the transfer direction When this transfer direction specification bit has a value of 0 it indicates that the master device is transmitting data to...

Page 272: ...data was received When the receiving device sets the SDAn line to low level during the ninth clock the ACK signal becomes active normal receive response When bit 2 ACKEn of IIC control register n IICC...

Page 273: ...When 9 clock wait is selected ACK signal is automatically output at the falling edge of the SCLn s eighth clock if ACKEn has already been set to 1 5 Stop condition When the SCLn pin is at high level c...

Page 274: ...for both the master and slave devices the next data transfer can begin n 0 1 Figure 10 23 Wait Signal 1 2 a When master device has a nine clock wait and slave device has an eight clock wait master tra...

Page 275: ...according to previously set ACKE value Transfer lines Remarks 1 ACKEn Bit 2 of IIC control register n IICCn WRELn Bit 5 of IIC control register n IICCn 2 n 0 1 A wait may be automatically generated d...

Page 276: ...Data Stop normal transmission reception 1 When WTIMn 0 SPTn 1 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 5 1 IICSn 10XXX110B 2 IICSn 10XXX000B 3 IICSn 10XXX000B WTIMn 0 4 IICSn 10XXXX00B...

Page 277: ...00B WTIMn 1 3 IICSn 10XXXX00B WTIMn 0 4 IICSn 10XXX110B WTIMn 0 5 IICSn 10XXX000B WTIMn 1 6 IICSn 10XXXX00B 7 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 W...

Page 278: ...2 3 4 5 1 IICSn 1010X110B 2 IICSn 1010X000B 3 IICSn 1010X000B WTIMn 1 4 IICSn 1010XX00B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 SPTn 1 S...

Page 279: ...AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 0001X110B 2 IICSn 0001X000B 3 IICSn 0001X000B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn...

Page 280: ...CSn 0001X110B 2 IICSn 0001X000B 3 IICSn 0001X110B 4 IICSn 0001X000B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 after restart match with SVA...

Page 281: ...0B 2 IICSn 0001X000B 3 IICSn 0010X010B 4 IICSn 0010X000B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 after restart extension code reception...

Page 282: ...AK SP 1 2 3 4 1 IICSn 0001X110B 2 IICSn 0001X000B 3 IICSn 00000X10B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 after restart mismatch with...

Page 283: ...D7 to D0 AK SP 1 2 3 4 1 IICSn 0010X010B 2 IICSn 0010X000B 3 IICSn 0010X000B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 ST AD6 to AD0 RW AK...

Page 284: ...0B 2 IICSn 0010X000B 3 IICSn 0001X110B 4 IICSn 0001X000B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 after restart match with SVAn ST AD6 to...

Page 285: ...010X000B 3 IICSn 0010X010B 4 IICSn 0010X000B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 after restart extension code reception ST AD6 to AD...

Page 286: ...4 1 IICSn 0010X010B 2 IICSn 0010X000B 3 IICSn 00000X10B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 after restart mismatch with address not...

Page 287: ...ion of slave address data 1 When WTIMn 0 ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 2 3 4 1 IICSn 0101X110B Example when ALDn is read during interrupt servicing 2 IICSn 0001X000B 3 IICSn 0001X00...

Page 288: ...s read during interrupt servicing 2 IICSn 0010X000B 3 IICSn 0010X000B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 2 When WTIMn 1 ST AD6 to AD0 RW AK D7 to...

Page 289: ...1 2 1 IICSn 01000110B Example when ALDn is read during interrupt servicing 2 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 n 0 1 b When arbitration loss occurs during transmissi...

Page 290: ...CSn 10001110B 2 IICSn 01000000B Example when ALDn is read during interrupt servicing 3 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 n 0 1 2 When WTIMn 1 ST AD6 to AD0 RW AK D7 t...

Page 291: ...01000110B Example when ALDn is read during interrupt servicing 3 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 X don t care Dn D6 to D0 n 0 1 2 Extension code ST AD6 to AD0 RW A...

Page 292: ...d only when SPIEn 1 X don t care Dn D6 to D0 n 0 1 f When arbitration loss occurs due to low level data when attempting to generate a restart condition When WTIMn 1 STTn 1 ST AD6 to AD0 RW AK D7 to D0...

Page 293: ...3 IICSn 01000001B Remark Always generated Generated only when SPIEn 1 X don t care n 0 1 h When arbitration loss occurs due to low level data when attempting to generate a stop condition When WTIMn 1...

Page 294: ...ave address register n SVAn neither INTIICn nor a wait occurs Remarks 1 The numbers in the table indicate the number of the serial clock s clock signals Interrupt requests and wait control are both sy...

Page 295: ...sion error is judged as having occurred when the compared data values do not match n 0 1 10 3 9 Extension code 1 When the higher 4 bits of the receive address are either 0000 or 1111 the extension cod...

Page 296: ...clocks is adjusted until the data differs This kind of operation is called arbitration n 0 1 When one of the master devices loses in arbitration an arbitration loss flag ALDn in IIC status register n...

Page 297: ...tension code transmission During data transmission During ACK signal transfer period after data transmission When restart condition is detected during data transfer When stop condition is detected dur...

Page 298: ...ave function is a function that generates an interrupt request INTIICn when a local address and extension code have been received This function makes processing more efficient by preventing unnecessar...

Page 299: ...ted when a stop condition is detected writing to IIC shift register n IICn causes the master s address transfer to start At this point IICCn s bit 4 SPIEn should be set n 0 1 When STTn has been set th...

Page 300: ...access IICn IIC shift register n STTn Bit 1 of IIC control register n IICCn STDn Bit 1 of IIC status register n IICSn SPDn Bit 0 of IIC status register n IICSn Remark n 0 1 Communication reservations...

Page 301: ...MSTSn 0 Communication reservation Note Generate start condition Sets STT flag communication reservation Gets wait period set by software see Table 10 7 Confirmation of communication reservation Clear...

Page 302: ...rst generate a stop condition to release the bus then perform master device communication When using multiple masters it is not possible to perform master device communication when the bus has not bee...

Page 303: ...n H IICEn SPIEn WTIMn 1 Start IICn write transfer Start IICn write transfer WRELn 1 Start reception Generate stop condition no slave with matching address Generate restart condition or stop condition...

Page 304: ...low Chart IICCn H IICEn 1 WRELn 1 Start reception Detect restart condition or stop condition START ACKEn 0 Data processing Data processing LRELn 1 No Yes No No No No No No No Yes No Yes Yes Yes Yes Ye...

Page 305: ...device transmits the TRCn bit bit 3 of IIC status register n IICSn that specifies the data transfer direction and then starts serial communication with the slave device IIC bus shift register n IICn s...

Page 306: ...H L L L L H H H L L ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCLn SDAn Processing by master device Transfer lines Processing by sla...

Page 307: ...L L L L H H H H L L L L L ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCLn SDAn Processing by master device Transfer lines Processing...

Page 308: ...ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCLn SDAn Processing by master device Transfer lines Processing by slave device 1 2 3 4 5 6...

Page 309: ...SPDn WTIMn H H L L H H L ACKEn MSTSn STTn L L SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCLn SDAn Processing by master device Transfer lines Processi...

Page 310: ...L L L H H H L L L L L ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCLn SDAn Processing by master device Transfer lines Processing by s...

Page 311: ...H L L L H H ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn SCLn SDAn Processing by master device Transfer lines Processing by slave device...

Page 312: ...electable baud rates In addition a baud rate based on divided clock input to the ASCKn pin can also be defined The UARTn baud rate generator can also be used to generate a MIDI standard baud rate 31 2...

Page 313: ...al data Writing data to TXSn starts the transmit operation TXSn can be written to by an 8 bit memory manipulation instruction It cannot be read from RESET input sets these registers to FFH Caution Do...

Page 314: ...perations based on the values set to asynchronous serial interface mode register n ASIMn During a receive operation it performs error checking such as for parity errors and sets various values to asyn...

Page 315: ...unction 0 1 UARTn mode receive only Serial function Port function 1 0 UARTn mode transmit only Port function Serial function 1 1 UARTn mode transmit and receive Serial function Serial function PS1n PS...

Page 316: ...error flag 0 No parity error 1 Parity error Transmit data parity does not match FEn Framing error flag 0 No framing error 1 Framing error Note 1 Stop bit not detected OVEn Overrun error flag 0 No ove...

Page 317: ...g prohibited 0 0 0 0 1 0 0 0 fSCK 8 8 0 0 0 0 1 0 0 1 fSCK 9 9 0 0 0 0 1 0 1 0 fSCK 10 10 0 0 0 0 1 0 1 1 fSCK 11 11 0 0 0 0 1 1 0 0 fSCK 12 12 0 0 0 0 1 1 0 1 fSCK 13 13 0 0 0 0 1 1 1 0 fSCK 14 14 0...

Page 318: ...n2 TPSn1 TPSn0 8 bit counter source clock selection m 0 0 0 0 External clock ASCKn 0 0 0 1 fXX 0 0 0 1 0 fXX 2 1 0 0 1 1 fXX 4 2 0 1 0 0 fXX 8 3 0 1 0 1 fXX 16 4 0 1 1 0 fXX 32 5 0 1 1 1 at n 0 TM3 ou...

Page 319: ...as ordinary ports a Register settings Operation stop mode settings are made via bits TxEn and RXEn of asynchronous serial interface mode register n ASIMn Figure 10 37 ASIMn Setting Operation Stop Mod...

Page 320: ...PS0n CLn SLn ISRMn 0 n 0 1 TXEn RXEn Operation mode RXDn Pxx pin function TXDn Pxx pin function 0 1 UARTn mode receive only Serial function Port function 1 0 UARTn mode transmit only Port function Se...

Page 321: ...op bit not detected OVEn Overrun error flag 0 No overrun error 1 Overrun error Note 2 Next receive operation was completed before data was read from receive buffer register Notes 1 Even if a stop bit...

Page 322: ...CK 10 10 0 0 0 0 1 0 1 1 fSCK 11 11 0 0 0 0 1 1 0 0 fSCK 12 12 0 0 0 0 1 1 0 1 fSCK 13 13 0 0 0 0 1 1 1 0 fSCK 14 14 0 0 0 0 1 1 1 1 fSCK 15 15 0 0 0 1 0 0 0 0 fSCK 16 16 1 1 1 1 1 1 1 1 fSCK 255 255...

Page 323: ...1 1 fXX 4 2 0 1 0 0 fXX 8 3 0 1 0 1 fXX 16 4 0 1 1 0 fXX 32 5 0 1 1 1 at n 0 TM3 output at n 1 TM2 output 1 0 0 0 fXX 64 6 1 0 0 1 fXX 128 7 1 0 1 0 fXX 256 8 1 0 1 1 fXX 512 9 1 1 0 0 1 1 0 1 1 1 1...

Page 324: ...xample of the baud rate tolerance Table 10 9 Relationship Between Main Clock and Baud Rate fXX 8 MHz fXX 12 58 MHz fXX 16 MHz Note fXX 20 MHz Note Baud Rate bps k m Error k m Error k m Error k m Error...

Page 325: ...speed clock clock cycle T enabling normal reception START D0 D7 P STOP Low speed clock clock cycle T enabling normal reception START D0 D7 P STOP 32T 64T 256T 288T 320T 352T Ideal sampling point 304T...

Page 326: ...D6 D7 Start bit Parity bit Stop bit 1 data frame Start bit 1 bit Character bits 7 bits or 8 bits Parity bit Even parity odd parity zero parity or no parity Stop bit s 1 bit or 2 bits When 7 bits is se...

Page 327: ...including a parity bit and a parity error is generated when the result is an odd number ii Odd parity During transmission The number of bits in transmit data including a parity bit is controlled so t...

Page 328: ...re 10 44 Timing of Asynchronous Serial Interface Transmit Completion Interrupt TxDn output D0 D1 D2 D6 D7 Parity STOP START INTSTn a Stop bit length 1 TxDn output D0 D1 D2 D6 D7 Parity START INTSTn b...

Page 329: ...ted the receive data in the shift register is transferred to receive buffer register n RXBn and a receive completion interrupt INTSRn occurs Even if an error has occurred the receive data in which the...

Page 330: ...eceive Error Causes Receive Error Cause ASISn Value Parity error Parity specification at transmission and receive data parity do not match 04H Framing error Stop bit is not detected 02H Overrun error...

Page 331: ...transmit shift register n TXSn and receive buffer register n RXBn are stopped and their values immediately before the clock stopped are hold The TXDn pin output holds the data immediately before the c...

Page 332: ...serial I O mode the processing time of data transfer is shortened MSB and LSB can be switched for the first bit of data to be transferred in serial The 3 wire variable length serial I O mode is usefu...

Page 333: ...SIO4 is set by a 16 bit memory manipulation instruction The serial operation starts when data is written to or read from SIO4 while the bit 7 CSIE4 of variable length serial control register 4 CSIM4 i...

Page 334: ...ter regardless of whether MSB or LSB is set for the first transfer bit Any data can be set to the unused higher bits however in this case the received data after a serial transfer operation becomes 0...

Page 335: ...al Control Register 4 CSIM4 After reset 00H R W Address FFFFF2E2H 7 6 5 4 3 2 1 0 CSIM4 CSIE4 0 0 0 0 MODE4 0 SCL4 SIO4 operation enable disable specification CSIE4 Shift register operation Serial cou...

Page 336: ...Variable Length Serial Setting Register 4 CSIB4 After reset 00H R W Address FFFFF2E4H 7 6 5 4 3 2 1 0 CSIB4 0 CMODE DMODE DIR BSEL3 BSEL2 BSEL1 BSEL0 CMODE DMODE SCK4 active level SI4 interrupt timing...

Page 337: ...nipulation instruction RESET input clears BRGCN4 to 00H Figure 10 52 Baud Rate Generator Source Clock Selection Register 4 BRGCN4 After reset 00H R W Address FFFFF2E6H 7 6 5 4 3 2 1 0 BRGCN4 0 0 0 0 0...

Page 338: ...0 3 0 1 1 fSCK 6 3 1 1 1 1 1 1 0 fSCK 252 126 1 1 1 1 1 1 1 fSCK 254 127 The baud rate transmit receive clock that is generated is obtained by dividing the main clock Generation of baud rate transmit...

Page 339: ...e SI4 SO4 and SCK4 can be used as normal I O ports a Register settings Operation stop mode is set via CSIE4 bit of variable length serial control register 4 CSIM4 While CSIE4 0 SIO4 operation stop sta...

Page 340: ...I O mode is set via variable length serial control register 4 CSIM4 Figure 10 55 CSIM4 Setting 3 Wire Variable Length Serial I O Mode After reset 00H R W Address FFFFF2E2H 7 6 5 4 3 2 1 0 CSIM4 CSIE4...

Page 341: ...IR BSEL3 BSEL2 BSEL1 BSEL0 CMODE DMODE SCK4 active level SI4 interrupt timing SO4 output timing 0 0 Low level Rising edge of SCK4 Falling edge of SCK4 0 1 Low level Falling edge of SCK4 Rising edge of...

Page 342: ...an change the attribute of the serial clock SCK4 and the phases of serial data SI4 and SO4 Figure 10 57 Timing of 3 Wire Variable Length Serial I O Mode SCK4 CMODE 0 SIO4 write SO4 DMODE 1 INTCSI4 SCK...

Page 343: ...ransmit transmit and receive mode MODE4 0 Transfer starts when writing to SIO4 Receive only mode Transfer starts when reading from SIO4 Caution After data has been written to SIO4 transfer will not st...

Page 344: ...er input ADTRG rising edge falling edge or both rising and falling edges can be specified 2 Software start Conversion is started by setting A D converter mode register 1 ADM1 One analog input channel...

Page 345: ...EF AVSS INTAD 4 ADS3 ADS2 ADS1 ADS0 ADCS TRG FR2 FR1 FR0 EGA1 EGA0 ADPS Selector Sample hold circuit AVSS Voltage comparator Tap selector ADTRG Edge detector Controller A D conversion result register...

Page 346: ...loaded to this register from the successive approximation register The higher 10 bits of this register holds the result of the A D conversion the lower 6 bits are fixed to 0 This register is read usi...

Page 347: ...of the absolute maximum ratings is input to a channel the conversion value of the channel is undefined and the conversion values of the other channels may also be affected 7 AVREF pin This pin inputs...

Page 348: ...ersion time of the input analog signal to be converted into a digital signal starting or stopping the conversion and an external trigger ADM is set by a 1 bit or 8 bit memory manipulation instruction...

Page 349: ...g prohibited 6 7 3 3 s 1 0 1 1 60 fXX 30 fXX Setting prohibited Setting prohibited 1 1 0 0 48 fXX 24 fXX Setting prohibited Setting prohibited 1 1 0 1 36 fXX 18 fXX Setting prohibited Setting prohibit...

Page 350: ...2 ADS1 ADS0 Analog Input Channel Specification 0 0 0 0 ANI0 0 0 0 1 ANI1 0 0 1 0 ANI2 0 0 1 1 ANI3 0 1 0 0 ANI4 0 1 0 1 ANI5 0 1 1 0 ANI6 0 1 1 1 ANI7 1 0 0 0 ANI8 1 0 0 1 ANI9 1 0 1 0 ANI10 1 0 1 1 A...

Page 351: ...If the analog input voltage is less than 1 2 AVREF the MSB is reset 6 Next bit 8 of the SAR is automatically set and the analog input voltage is compared again Depending on the value of bit 9 to which...

Page 352: ...on result Conversion result A D conversion is successively executed until bit 7 ADCS of A D converter mode register 1 ADM1 is reset to 0 by software If ADM1 and the analog input channel specification...

Page 353: ...0 5 INT Function that returns integer of value in VIN Analog input voltage AVREF AVREF pin voltage ADCR Value of the A D conversion result register ADCR The relationship between the analog input volta...

Page 354: ...og input pin specified by the analog input channel specification register ADS into a digital signal When the A D conversion has been completed the result of the conversion is stored in the A D convers...

Page 355: ...INTAD is generated Once A D conversion has been started and completed the next conversion is started immediately A D conversion is repeated until new data is written to ADS If ADS is rewritten during...

Page 356: ...LT mode At this time the current consumption of the A D converter can be reduced by stopping the conversion by resetting the bit 7 ADCS of A D converter mode register 1 ADM1 to 0 To reduce the current...

Page 357: ...11 The analog input ANI0 to ANI11 pins are multiplexed with port pins To execute A D conversion with any of ANI0 to ANI11 selected do not execute an instruction that inputs data to the port during con...

Page 358: ...t flag may be set immediately before ADS is rewritten If ADIF is read immediately after ADS has been rewritten it may be set despite the fact that conversion of the newly selected analog input signal...

Page 359: ...VDD pin as shown in Figure 11 11 Figure 11 11 Handling of AVDD Pin AVREF VDD VSS AVDD AVSS Main power supply Back up capacitor 9 Reading out A D converter result register ADCR A write operation to A D...

Page 360: ...t Request After a DMA transfer has occurred a specified number of times and the TCn bit in the corresponding DMA channel control register DCHCn has been set to 1 a DMA transfer completion interrupt re...

Page 361: ...A 70F3033AY V850 SB2 PD703035A 703035AY 70F3035A 70F3035AY 16 KB 16 KB xxFFB000H to xxFFEFFFH V850 SB1 PD703030A 703030AY V850 SB2 PD703036A 703036AY 20 KB 12 KB xxFFA000H to xxFFBFFFH xxFFE000H to xx...

Page 362: ...and Internal RAM 12 KB xxFFFFFFH xxFFC000H xxFFBFFFH xxFFF000H xxFFEFFFH xxFF8000H xxFF7FFFH Access prohibited area Expansion ROM area Internal peripheral I O area Internal RAM area DRAn setting value...

Page 363: ...2 4 Correspondence Between DRAn Setting Value and Internal RAM 16 KB xxFFFFFFH xxFFB000H xxFFAFFFH xxFFF000H xxFFEFFFH xxFF8000H xxFF7FFFH Access prohibited area Expansion ROM area Internal peripheral...

Page 364: ...0H xxFFEFFFH xxFF8000H xxFF7FFFH Access prohibited area Expansion ROM area Internal peripheral I O area Internal RAM area DRAn setting value 0FFFH 2000H 0000H 3FFFH xxFFC000H xxFFBFFFH 8 KB usable for...

Page 365: ...Between DRAn Setting Value and Internal RAM 24 KB xxFFFFFFH xxFF9000H xxFF8FFFH xxFFF000H xxFFEFFFH xxFF8000H xxFF7FFFH Access prohibited area Expansion ROM area Internal peripheral I O area Internal...

Page 366: ...written in 8 bit units Figure 12 7 Format of DMA Byte Count Registers 0 to 5 DBC0 to DBC5 After reset Undefined R W Address DBC0 FFFFF184H DBC3 FFFFF1B4H DBC1 FFFFF194H DBC4 FFFFF1C4H DBC2 FFFFF1A4H D...

Page 367: ...H 7 6 5 4 3 2 1 0 DCHCn TCn 0 DDADn TTYPn1 TTYPn0 TDIRn DSn ENn n 0 to 5 TCn DMA transfer completed not completed Note 1 0 Not completed 1 Completed DDADn Internal RAM address count direction control...

Page 368: ...ternal RAM Note 3 0 From internal RAM to peripheral I Os 1 From peripheral I Os to internal RAM DSn Control of transfer data size for DMA transfer Note 3 0 8 bit transfer 1 16 bit transfer ENn Control...

Page 369: ...t called a real time output port Because RTO can output signals without jitter it is suitable for controlling a stepping motor The real time output port can be set in port mode or real time output por...

Page 370: ...as shown in Figure 13 2 If an operation mode of 4 bits 2 channels is specified data can be individually set to RTBL and RTBH The data of both the registers can be read all at once by specifying the ad...

Page 371: ...sing the following two types of registers Real time output port mode register RTPM Real time output port control register RTPC 1 Real time output port mode register RTPM This register selects real tim...

Page 372: ...3 2 1 0 RTPC RTPOE RTPEG BYTE EXTR 0 0 0 0 RTPOE Control of operation of real time output port 0 Disables operation Note 1 Enables operation RTPEG Valid edge of RTPTRG 0 Falling edge 1 Rising edge BY...

Page 373: ...egister RTPM is output from the bits of RTP0 to RTP7 The bits specified in the port mode by RTPM output 0 If the real time output operation is disabled by clearing RTPOE to 0 RTP0 to RTP7 output 0 reg...

Page 374: ...er registers RTBH and RTBL 3 Enable the real time output operation Set RTPOE to 1 4 Set the output latch of ports P100 to P107 to 0 and the next output to RTBH and RTBL until the selected transfer tri...

Page 375: ...I O port for which I O settings can be controlled in 1 bit units A pull up resistor can be connected in 1 bit units software pull up function When using P00 to P04 as the NMI or INTP0 to INTP3 pins n...

Page 376: ...NMI and INTP0 to INTP6 are specified via rising edge specification register 0 EGP0 and falling edge specification register 0 EGN0 A pull up resistor can be connected in 1 bit units when specified via...

Page 377: ...ination is not performed when these pins are used as an ordinary input port 3 Control registers a Port 0 mode register PM0 PM0 can be read written in 8 1 bit units Figure 14 2 Port 0 Mode Register PM0...

Page 378: ...g edge 1 Interrupt request signal occurs at rising edge Remark n 0 Control of NMI pin n 1 to 7 Control of INTP0 to INTP6 pins d Falling edge specification register 0 EGN0 EGN0 can be read written in 8...

Page 379: ...to P07 P ch WRPM WRPORT RD WRPU VDD P00 NMI P01 INTP0 P02 INTP1 P03 INTP2 P04 INTP3 P05 INTP4 ADTRG P06 INTP5 RTPTRG P07 INTP6 Selector PU0n PU0 Output latch P0n PM0n PM0 Internal bus Remarks 1 PU0 Pu...

Page 380: ...he P1 register is read the pin levels at that time are read Writing to P1 writes the values to that register This does not affect the input pins In output mode When the P1 register is read the P1 regi...

Page 381: ...specified via pull up resistor option register 1 PU1 Clear the P1 and PM1 registers to 0 when using alternate function pins as outputs The ORed result of the port output and the alternate function pi...

Page 382: ...rain output Note Bit 3 is fixed as a normal output 3 Block diagram Port 1 Figure 14 11 Block Diagram of P10 to P12 P14 and P15 P ch WRPM WRPF WRPORT RD WRPU VDD VDD Selector PF1n PF1 PM1n PM1 PU1n PU1...

Page 383: ...e 14 12 Block Diagram of P13 P ch WRPM WRPORT RD WRPU VDD Selector Output latch P13 PM13 PM1 PU13 PU1 Internal bus Alternate function P13 SI1 RxD0 Remark PU1 Pull up resistor option register 1 PM1 Por...

Page 384: ...1 Outputs 1 Remark In input mode When the P2 register is read the pin levels at that time are read Writing to P2 writes the values to that register This does not affect the input pins In output mode W...

Page 385: ...hile in output mode A pull up resistor can be connected in 1 bit units when specified via pull up resistor option register 2 PU2 When using the alternate function as TI2 and TI3 pins noise elimination...

Page 386: ...0 PU2 PU27 PU26 PU25 PU24 PU23 PU22 PU21 PU20 PU2n Control of on chip pull up resistor connection n 0 to 7 0 Do not connect 1 Connect c Port 2 function register PF2 PF2 can be read written in 8 1 bit...

Page 387: ...n PF2 PM2n PM2 PU2n PU2 P ch N ch Internal bus Output latch P2n Alternate function P20 SI2 SDA1Note P21 SO2 P22 SCK2 SCL1Note P24 SO3 TxD1 P25 SCK3 ASCK1 Note The SDA1 SCL1 pins apply only to the PD70...

Page 388: ...Diagram of P23 P26 and P27 P ch WRPM WRPORT RD WRPU VDD Selector Output latch P13 PM13 PM1 PU13 PU1 Internal bus Alternate function P13 SI1 RxD0 Remarks 1 PU2 Pull up resistor option register 2 PM2 Po...

Page 389: ...data In output mode n 0 to 7 0 Outputs 0 1 Outputs 1 Remark In input mode When the P3 register is read the pin levels at that time are read Writing to P3 writes the values to that register This does n...

Page 390: ...or port 0 When using the alternate function as A13 to A15 pins set the pin functions via the memory address output mode register MAM At this time be sure to set the PM3 registers PM34 PM35 PM36 and th...

Page 391: ...al output N ch open drain output n 3 4 0 Normal output 1 N ch open drain output 3 Block diagram Port 3 Figure 14 23 Block Diagram of P30 to P32 and P35 to P37 P ch WRPM WRPORT RD WRPU VDD Selector Out...

Page 392: ...WRPF WRPORT RD WRPU VDD VDD Selector PF3n PF3 PM3n PM3 PU3n PU3 P ch N ch Internal bus Output latch P3n Alternate function P33 TI11 SO4 P34 TO0 A13 SCK4 Remarks 1 PU3 Pull up resistor option register...

Page 393: ...in levels at that time are read Writing to P4 and P5 writes the values to those registers This does not affect the input pins In output mode When the P4 and P5 registers are read their values are read...

Page 394: ...can be read by reading the P4 and P5 registers while in output mode A software pull up function is not implemented When using the alternate function as AD0 to AD15 set the pin functions via the memory...

Page 395: ...lock diagram Ports 4 and 5 Figure 14 27 Block Diagram of P40 to P47 and P50 to P57 WRPM WRPORT RD Selector Output latch mn PMmn PMm Internal bus Pmn ADx Remarks 1 PMm Port m mode register RD Port m re...

Page 396: ...de When the P6 register is read the pin levels at that time are read Writing to P6 writes the values to that register This does not affect the input pins In output mode When the P6 register is read th...

Page 397: ...output latch values can be read by reading the P6 register while in output mode A software pull up function is not implemented When using the alternate function as A16 to A21 set the pin functions via...

Page 398: ...EJ4V0UM 398 3 Block diagram Port 6 Figure 14 30 Block Diagram P60 to P65 WRPM WRPORT RD Selector Output latch P6n PM6n PM6 Internal bus P6n Ax Remarks 1 PM6 Port 6 mode register RD Port 6 read signal...

Page 399: ...P71 P70 P7n Pin level n 0 to 7 0 1 Read pin level of bit n After reset Undefined R Address FFFFF010H 7 6 5 4 3 2 1 0 P8 0 0 0 0 P83 P82 P81 P80 P8n Pin level n 0 to 3 0 1 Read pin level of bit n Ports...

Page 400: ...P7 and P8 Data cannot be written to P7 or P8 A software pull up function is not implemented Values read from pins specified as analog inputs are undefined values Do not read values from P7 or P8 duri...

Page 401: ...P9 register is read the pin levels at that time are read Writing to P9 writes the values to that register This does not affect the input pins In output mode When the P9 register is read the P9 registe...

Page 402: ...gister output latch values can be read by reading the P9 register while in output mode A software pull up function is not implemented When using the P9 for control signals in expansion mode set the pi...

Page 403: ...rt 9 Figure 14 35 Block Diagram of P90 to P96 WRPM WRPORT RD Selector Output latch P9n PM9n PM9 Internal bus P90 LBEN WRL P91 UBEN P92 R W WRH P93 DSTB RD P94 ASTB P95 HLDAK P96 HLDRQ Remarks 1 PM9 Po...

Page 404: ...uts 1 Remark In input mode When the P10 register is read the pin levels at that time are read Writing to P10 writes the values to that register This does not affect the input pins In output mode When...

Page 405: ...bit units when specified via pull up resistor option register 10 PU10 When using the alternate function as A5 to A12 pins see the pin functions via the memory address output mode register MAM At this...

Page 406: ...PU106 PU105 PU104 PU103 PU102 PU101 PU100 PU10n Control of on chip pull up resistor connection n 0 to 7 0 Do not connect 1 Connect c Port 10 function register PF10 PF10 can be read written in 8 1 bit...

Page 407: ...nal bus Output latch P10n Alternate function P100 RTP0 A5 KR0 P101 RTP1 A6 KR1 P102 RTP2 A7 KR2 P103 RTP3 A8 KR3 P104 RTP4 A9 KR4 IERXNote P105 RTP5 A10 KR5 IETXNote P106 RTP6 A11 KR6 P107 RTP7 A12 KR...

Page 408: ...0 0 0 Undefined P113 P112 P111 P110 P11n Control of output data in output mode n 0 to 3 0 Outputs 0 1 Outputs 1 Remark In input mode When the P11 register is read the pin levels at that time are read...

Page 409: ...ion register 11 PU11 The on off of wait function can be switched with a port alternate function control register PAC When using the alternate function as A1 to A4 pins set the pin functions via the me...

Page 410: ...4 3 2 1 0 PU11 0 0 0 0 PU113 PU112 PU111 PU110 PU11n Control of on chip pull up resistor connection n 0 to 3 0 Do not connect 1 Connect c Port alternate function control register PAC PAC can be read w...

Page 411: ...Block Diagram of P110 to P113 P ch WRPM WRPORT RD WRPU VDD Selector PU11n PU11 Output latch P11n PM11n PM11 Internal bus P110 A1 WAIT P111 A2 P112 A3 P113 A4 Remarks 1 PU11 Pull up resistor option reg...

Page 412: ...t PM02 1 Setting not needed for P02 P03 INTP2 Input PM03 1 Setting not needed for P03 P04 INTP3 Input PM04 1 Setting not needed for P04 INTP4 Input P05 ADTRG Input PM05 1 Setting not needed for P05 IN...

Page 413: ...24 TXD1 Output PM24 0 P24 0 Input PM25 1 Setting not needed for P25 SCK3 Output PM25 0 P25 0 P25 ASCK1 Input PM25 1 Setting not needed for P25 TI2 Input PM26 1 Setting not needed for P26 P26 TO2 Outpu...

Page 414: ...MM P60 to P65 A16 to A21 Output Setting not needed for PM60 to PM65 Setting not needed for P60 to P65 Refer to Figure 3 21 MM P70 to P77 ANI0 to ANI7 Input None Setting not needed for P70 to P77 P80...

Page 415: ...nput PM106 PM107 1 Setting not needed for P106 and P107 A1 Output PM110 0 P110 0 Refer to Figure 3 22 MAM P110 WAIT Input PM110 1 Setting not needed for P110 WAC 1 PAC P111 to P113 A2 to A4 Output PM1...

Page 416: ...related malfunction of the RESET pin 15 2 Pin Operations During the system reset period high impedance is set at almost all pins all pins except for RESET X2 XT2 REGC AVREF VDD VSS AVDD AVSS BVDD BVS...

Page 417: ...r 3 0 V V850 SB2 Refer to 2 4 I O Circuit Types I O Buffer Power Supply and Connection of Unused Pins for the power supply corresponding to each pin Figure 16 1 Regulator A D converter 4 5 V to 5 5 V...

Page 418: ...ruction bugs found in the mask ROM can be avoided and program flow can be changed by using the ROM correction function Up to four correction addresses can be specified Cautions 1 The ROM correction fu...

Page 419: ...matches the fetch address n 0 to 3 Whether match detection by a comparator is enabled or disabled can be set for each channel CORCN can be set by a 1 bit or 8 bit memory manipulation instruction Figur...

Page 420: ...address At this time the program can judge the following cases by reading CORRQ Reset input CORRQ 00H ROM correction generation CORRQn bit 1 n 0 to 3 Branch to 00000000H by user program CORRQ 00H Fig...

Page 421: ...ing on the product set the correction address within following ranges PD703031A 703031AY 703034A 703034AY 128 KB 00000000H to 0001FFFEH PD703033A 703033AY 703035A 703035AY 256 KB 00000000H to 0003FFFE...

Page 422: ...ddress of the internal RAM that stores the correction code of channel n should be preset before the instruction that makes the program jump to this address is stored in the internal ROM Executed by a...

Page 423: ...on the target system on board The dedicated flash programmer is connected to the target system to perform writing The following can be considered as the development environment and the applications us...

Page 424: ...to xx01FFFFH 128 KB is erased Area 1 The area of xx020000H to xx03FFFFH 128 KB is erased Area 2 The area of xx040000H to xx05FFFFH 128 KB is erased Area 3 The area of xx060000H to xx07FFFFH 128 KB is...

Page 425: ...lash programmer UART0 or CSI0 is used for the interface between the dedicated flash programmer and the V850 SB1 or V850 SB2 to perform writing erasing etc A dedicated program adapter FA Series require...

Page 426: ...erial clock Up to 1 MHz MSB first Figure 18 4 Communication with Dedicated Flash Programmer CSI0 HS V850 SB1 V850 SB2 RESET VSS VDD VPP Dedicated flash programmer SO0 SI0 VPP VDD GND RESET SI SO SCK0...

Page 427: ...DD I O VDD voltage generation voltage monitoring VDD GND Ground VSS CLK Note Output Clock output to V850 SB1 V850 SB2 X1 RESET Output Reset signal RESET SI RxD Input Receive signal SO0 TxD0 SO TxD Out...

Page 428: ...owledge the output high impedance status 18 5 1 VPP pin In the normal operation mode 0 V is input to the VPP pin In the flash memory programming mode a 7 8 V write voltage is supplied to the VPP pin T...

Page 429: ...late the connection to the other device or set the other device to the output high impedance status Figure 18 6 Conflict of Signals Serial Interface Input Pin V850 SB1 V850 SB2 Other device Output pin...

Page 430: ...so that the input signal to the other device is ignored Figure 18 7 Malfunction of Other Device V850 SB1 V850 SB2 Pin In the flash memory programming mode if the signal the V850 SB1 or V850 SB2 output...

Page 431: ...ignals In the flash memory programming mode the signal the reset signal generator outputs conflicts with the signal the dedicated flash programmer outputs Therefore isolate the signals on the reset si...

Page 432: ...8 6 1 Flash memory control The following shows the procedure for manipulating the flash memory Figure 18 9 Procedure for Manipulating Flash Memory Supplies RESET pulse Switch to flash memory programmi...

Page 433: ...set the V850 SB1 or V850 SB2 in the flash memory programming mode When switching modes set the VPP pin before releasing reset When performing on board writing change modes using a jumper etc Figure 18...

Page 434: ...CSI0 HS V850 SB1 and V850 SB2 perform slave operation MSB first 8 UART0 Communication rate 9600 bps at reset LSB first Others RFU Setting prohibited Caution When UART is selected the receive clock is...

Page 435: ...setting and control Status read out command Acquires the status of operations Oscillating frequency setting command Sets the oscillation frequency Erasing time setting command Sets the erasing time o...

Page 436: ...nication between one unit and plural units can be performed as follows Group unit broadcasting communication Broadcasting communication to group units All unit broadcasting communication Broadcasting...

Page 437: ...m one unit to plural units takes precedence over normal communication communication from one unit to another 2 Priority by master address If the communication type is the same communication with the l...

Page 438: ...plural slave units exist the slave units do not return an acknowledge signal during communication Whether broadcasting communication or normal communication is to be executed is selected by broadcast...

Page 439: ...complete the unit starts outputting the broadcasting bit in synchronization with the completion of the start bit output by the other unit The units other than the one that has started communication de...

Page 440: ...the data on the bus as a result of comparison it is assumed that the master has lost in arbitration As a result the master stops transmission and enters the reception status Because the IEBus is confi...

Page 441: ...e address is FFFH All unit broadcasting communication If slave address is other than FFFH Group unit broadcasting communication Remark The group No during group unit broadcasting communication is the...

Page 442: ...and locks Note 2 1 0 1 1 Writes data and locks Note 2 1 1 0 0 Undefined 1 1 0 1 Undefined 1 1 1 0 Writes command 1 1 1 1 Writes data Notes 1 The telegraph length bit of the telegraph length field and...

Page 443: ...s lock address lower 8 bits 0 0 0 1 Reads lock address higher 4 bits Moreover units for which lock is not set by the master unit reject acknowledgement and do not output an acknowledge bit when the co...

Page 444: ...eived Control Data Communication Target SLVRQ Slave Specification 1 No Specification 0 Lock Status LOCK Lock 1 Unlock 0 Master Unit Identification Match with PAR Lock Request Unit 1 Other 0 Slave Tran...

Page 445: ...ter unit and the synchronization signals of bits are output by the master unit When the slave unit detects that the parity is even it outputs the acknowledge signal and starts outputting the data fiel...

Page 446: ...configuration of the data field is as shown below Figure 19 6 Data Field Data field number specified by telegraph length field MSB LSB One data ACK Parity Control bit 8 bits ACK Parity Following the...

Page 447: ...g broadcasting communication the slave unit judges that reception has not been performed correctly and stops reception b When master receives data When the master unit reads data from a slave unit the...

Page 448: ...the following cases and transmission is stopped If the parity of the control bit is incorrect If control bit 3 is 1 write operation when the slave reception enable flag ENSLVRX is not set 1 Note If t...

Page 449: ...the IEBus data register DR and no more data can be received Note Note In this case when the communication executed is individual communication if the maximum number of transmit bytes is within the va...

Page 450: ...er DR Bit 2 Meaning 0 Unit is not locked 1 Unit is locked Bit 3 Meaning 0 Fixed to 0 Bit 4 Note 3 Meaning 0 Slave transmission is stopped 1 Slave transmission is ready Bit 5 Meaning 0 Fixed to 0 Bit 7...

Page 451: ...than the one that has locked the unit does not receive broadcasting communication A unit is locked or unlocked as follows a Locking If the communication frame is completed without succeeding to trans...

Page 452: ...to the maximum number of transfer bytes without being output 19 1 8 Bit format The format of the bits constituting the communication frame of the IEBus is shown below Figure 19 9 Bit Format of IEBus...

Page 453: ...ator Contention detection ACK generation Parity generation error detection TX RX Interrupt controller Interrupt control block INT request CPU interface block Internal registers handler DMA transfer IE...

Page 454: ...registers refer to 19 3 Internal Registers of IEBus Controller d Bit processing block This block generates and disassembles bit timing and mainly consists of a bit sequence ROM 8 bit preset timer and...

Page 455: ...unit address register UAR FFFFF3E4H IEBus slave address register SAR R W FFFFF3E6H IEBus partner address register PAR R 0000H FFFFF3E8H IEBus control data register CDR FFFFF3EAH IEBus telegraph lengt...

Page 456: ...IEBus is operating as the master writing to the BCR register including bit manipulation instructions is disabled until either the end of that communication or frame or until communication is stopped b...

Page 457: ...should be resent by software following a loss in arbitration When resending the master request in this case set 1 the MSTRQ flag after securing the required wait period This flag is unable to be set...

Page 458: ...and communication continued when the control data of a slave status request is returned even if the ENSLVTX flag is in the reset status e Slave reception enable flag ENSLVRX Bit 3 Set reset condition...

Page 459: ...mat 15 0 14 0 13 0 12 0 UAR 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF3E2H After reset 0000H R W R W 3 IEBus slave address register SAR During master request the value of this register is reflected in th...

Page 460: ...a of the higher 4 bits to DR Sets the partner address 12 bits to bits 11 to 0 Figure 19 14 IEBus Partner Address Register PAR Format 15 0 14 0 13 0 12 0 PAR 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF3E6H...

Page 461: ...0 1 Undefined 1 1 1 0 Writes command 1 1 1 1 Writes data Cautions 1 Because the slave unit must judge whether the received data is a command or data it must read the value of this register after compl...

Page 462: ...an the unit that sent the lock request ACK returned 5 If 6H control data was received in the locked state from other than the unit that sent the lock request ACK not returned In all of the above cases...

Page 463: ...EBus unit is the communication target The STATUSF flag bit 4 of the ISR register is set and the status interrupt INTIE2 generated however if a slave status or lock address request is acknowledged Note...

Page 464: ...ter transmission slave transmission The data of this register is reflected in the data transmitted in the telegraph length field and indicates the number of bytes of the transmit data This register mu...

Page 465: ...20H 32 bytes 1 1 1 1 1 1 1 1 FFH 255 bytes 0 0 0 0 0 0 0 0 00H 256 bytes Cautions 1 If the master issues a request 0H 4H 5H or 6H to transmit a slave status and lock address higher 4 bits lower 8 bits...

Page 466: ...ster value However when the last byte and 32nd byte the last byte of 1 communication frame is stored in the shift register INTIE1 is not issued b When reception unit One byte of the data received by t...

Page 467: ...st flag SLVRQ Bit 6 A flag indicating whether there has been a slave request from the master Set reset conditions Set When the unit is requested as a slave if the received slave address and unit UAR m...

Page 468: ...forming broadcasting communication The contents of the flag are updated in the broadcast field of each frame Except for initialization reset by system reset the set reset conditions vary depending on...

Page 469: ...ontrol field Reset When the communication enable flag is cleared When the communication end flag is set after receipt of a lock release 3H 6H AH BH in the control field Caution Lock specification rele...

Page 470: ...each flag satisfying the reset conditions in Table 19 8 Table 19 8 Reset Conditions of Flags in ISR Register Flag Name Reset Condition Processing Example IEERR STARTF STATUSF Byte write operation of I...

Page 471: ...nication end flag 0 Communication does not end after the number of bytes set in the telegraph length field have been transferred 1 Communication ends after the number of bytes set in the telegraph len...

Page 472: ...om the unit requesting a lock Reset By software c Status transmission flag STATUSF Bit 4 A flag indicating that the transmission status is either the master to slave status or the lock address higher...

Page 473: ...a slave unit A NACK reception error only occurs in individual communication ACK and NACK are not discriminated in broadcasting communication Remark An interrupt is generated if NACK is received in a...

Page 474: ...starts in the overrun state the cause of the overrun NACK is not returned in the ACK period of the slave address control or telegraph length field the DR register is not updated If the next communica...

Page 475: ...e 19 25 IEBus Slave Status Register SSR Format After reset 41H R Address FFFFF3F2H 7 6 5 4 3 2 1 0 SSR 0 1 0 STATSLV 0 STATLOCK STATRX STATTX STATSLV Slave transmission status flag 0 Slave transmissio...

Page 476: ...Format After reset 01H R Address FFFFF3F4H 7 6 5 4 3 2 1 0 SCR Bit 7 6 5 4 3 2 1 0 Setting value Remaining number of communication data bytes 0 0 0 0 0 0 0 1 01H 1 byte 0 0 0 0 0 0 1 0 02H 2 bytes 0...

Page 477: ...ed when 1 byte has been communicated regardless of whether ACK or NACK When the count value has reached 00H the frame end flag ENDFRAM is set The maximum number of transfer bytes of the preset value o...

Page 478: ...5 of the above interrupt requests are assigned to the interrupt status register ISR For details refer to Table 19 9 Interrupt Source List The configuration of the interrupt control block is illustrate...

Page 479: ...Contention judgment If loses remaster processing Communication preparation processing Interrupt always occurs if loses in contention during master request Start interrupt Slave Slave address Slave re...

Page 480: ...Reception stops INTIE2 occurs NACK is returned To start bit waiting status Transmission stops INTIE2 occurs To start bit waiting status Individual communication Software processing Error processing su...

Page 481: ...INTIE2 does not occur NACK is returned Data is retransmitted from other unit Remark Data cannot be received until overrun status is cleared Transmission stops INTIE2 occurs To start bit waiting statu...

Page 482: ...mode 1 1 Interrupt INTIE2 occurrence Judgment of occurrence of error Error processing Judgment of slave request Slave reception processing See 19 5 1 1 Slave reception processing Judgment of contentio...

Page 483: ...s received from the slave in the data field an interrupt INTIE1 is not issued to the CPU and the same data is retransmitted by hardware If the transmit data is not written in time during the period of...

Page 484: ...t Broad casting M address P S address P A Control A P Telegraph length A P Data 1 Approx 390 s mode 1 Data 1 P A Data 2 P A Data n 1 P A Data n P A 2 1 1 Interrupt INTIE2 occurrence Judgment of occurr...

Page 485: ...ve If the receive data is not read in time until the next data is received the hardware automatically transmits NACK 2 Frame end processing The vector interrupt processing in 2 judges whether the data...

Page 486: ...dgment of slave request 2 Interrupt INTIE2 occurrence Judgment of occurrence of error Error processing Judgment of end of communication End of communication processing Judgment of end of frame Frame e...

Page 487: ...e period of writing the next data a communication error interrupt occurs due to occurrence of underrun and communication is abnormally ended 2 Frame end processing The vector interrupt processing in 2...

Page 488: ...4 s mode 1 Broad casting Telegraph length 1 Interrupt INTIE2 occurrence Judgment of occurrence of error Error processing Judgment of slave request Slave processing 2 Interrupt INTIE2 occurrence Judgme...

Page 489: ...ield an interrupt INTIE1 is not issued to the CPU and the same data is retransmitted from the master If the receive data is not read in time until the next data is received NACK is automatically trans...

Page 490: ...the following interrupt does not occur in that communication frame 1 Master transmission Figure 19 34 Master Transmission Interval of Interrupt Occurrence Start bit T t1 T Broad casting Master address...

Page 491: ...d of frame Communication start interrupt T T T T T A T t4 t4 t5 t2 A P T A t3 Remarks 1 T Timing error P Parity error A ACK error Data set interrupt INTIE1 2 End of frame occurs at the end of 32 byte...

Page 492: ...ss Control Data Telegraph length Remarks 1 T Timing error P Parity error A ACK error U Underrun error Data set interrupt INTIE1 2 End of frame occurs at the end of 32 byte data IEBus at 6 29 MHz Item...

Page 493: ...rts Broad casting Master address Slave address Control Data Telegraph length Remarks 1 T Timing error P Parity error A ACK error O Overrun error Data set interrupt INTIE1 2 End of frame occurs at the...

Page 494: ...utput clock selection register 4 BRG 338 BRGCN4 Baud rate generator source clock selection register 4 BRG 337 BRGMC00 Baud rate generator mode control register 00 BRG 318 BRGMC01 Baud rate generator m...

Page 495: ...ode register 1 CSI 247 CSIM2 Serial operation mode register 2 CSI 247 CSIM3 Serial operation mode register 3 CSI 247 CSIM4 Variable length serial control register 4 CSI 335 CSIS0 Serial clock selectio...

Page 496: ...ress register 3 DMAC 361 DRA4 DMA internal RAM address register 4 DMAC 361 DRA5 DMA internal RAM address register 5 DMAC 361 DWC Data wait control register BCU 111 ECR Interrupt source register CPU 76...

Page 497: ...375 P1 Port 1 Port 380 P2 Port 2 Port 384 P3 Port 3 Port 389 P4 Port 4 Port 393 P5 Port 5 Port 393 P6 Port 6 Port 396 P7 Port 7 Port 399 P8 Port 8 Port 399 P9 Port 9 Port 401 P10 Port 10 Port 404 P11...

Page 498: ...ister 0 Port 377 PU1 Pull up resistor option register 1 Port 381 PU2 Pull up resistor option register 2 Port 386 PU3 Pull up resistor option register 3 Port 390 PU10 Pull up resistor option register 1...

Page 499: ...gister 50 RPU 212 TCL51 Timer clock selection register 51 RPU 212 TCL60 Timer clock selection register 60 RPU 212 TCL61 Timer clock selection register 61 RPU 212 TCL70 Timer clock selection register 7...

Page 500: ...t control register INTC 139 to 141 TMIC6 Interrupt control register INTC 139 to 141 TMIC7 Interrupt control register INTC 139 to 141 TOC0 16 bit timer output control register 0 RPU 182 TOC1 16 bit tim...

Page 501: ...ines refer to Table B 2 This column shows instruction operations refer to Table B 3 This column shows flag statuses refer to Table B 4 Operand Op Code Operation Flag OV S Z SAT Table B 1 Symbols in Op...

Page 502: ...memory a b Reads data of size b from address a store memory a b c Writes data b of size c to address a load memory bit a b Reads bit b from address a store memory bit a b c Writes c to bit b of addre...

Page 503: ...1 Overflow NV 1000 OV 0 No overflow C L 0001 CY 1 Carry Lower Less than NC NL 1001 CY 0 No carry No lower Greater than or equal Z E 0010 Z 1 Zero Equal NZ NE 1010 Z 0 Not zero Not equal NH 0011 CY OR...

Page 504: ...rrrrr0111ddddddd adr ep zero extend disp7 Store memory adr GR reg2 Byte SST H reg2 disp8 ep rrrrr1001ddddddd Note 1 adr ep zero extend disp8 Store memory adr GR reg2 Halfword SST W reg2 disp8 ep rrrrr...

Page 505: ...RRRR result GR reg2 GR reg1 CMP imm5 reg2 rrrrr010011iiiii result GR reg2 sign extend imm5 Arithmetic operation SETF cccc reg2 rrrrr1111110cccc 0000000000000000 if conditions are satisfied then GR reg...

Page 506: ...101iiiii GR reg2 GR reg2 arithmetically shift right by zero extend imm5 0 JMP reg1 00000000011RRRRR PC GR reg1 JR disp22 0000011110dddddd ddddddddddddddd0 Note 1 PC PC sign extend disp22 JARL disp22 r...

Page 507: ...FH RETI 0000011111100000 0000000101000000 if PSW EP 1 then PC EIPC PSW EIPSW else if PSW NP 1 then PC FEPC PSW FEPSW else PC EIPC PSW EIPSW R R R R R HALT 0000011111100000 0000000100100000 Stops DI 00...

Page 508: ...ss match detection method 295 Address space 79 ADIC 139 to 141 ADM1 348 ADM2 350 ADS 350 ADTRG 59 Analog input channel specification register 350 ANI0 to ANI11 64 Arbitration 296 ASCK0 60 ASCK1 61 ASI...

Page 509: ...ters 0 to 5 366 DMA channel control registers 0 to 5 367 DMA internal RAM address registers 0 to 5 361 DMA peripheral I O address registers 0 to 5 360 DMAIC0 to DMAIC5 139 to 141 DMA start factor expa...

Page 510: ...trol register 139 Interrupt controller 38 48 Interrupt request signal generator 256 Interrupt source register 76 Interrupt status saving register 76 Interrupt exception processing function 124 Interva...

Page 511: ...Port 3 389 Port 3 function register 391 Port 3 mode register 390 Port 4 393 Port 4 mode register 394 Port 5 393 Port 5 mode register 394 Port 6 396 Port 6 mode register 397 Port 7 399 Port 8 399 Port...

Page 512: ...face function 244 Serial operation mode registers 0 to 3 247 SERIC0 SERIC1 139 to 141 SI0 SI1 60 SI2 SI3 61 SI4 62 Single chip mode 78 SIO0 to SIO3 245 SIO4 333 Slave address registers 0 1 268 SO latc...

Page 513: ...4 336 VDD 68 VPP 68 VSS 68 W WAIT 67 Wait function 110 Wake up controller 255 Wake up function 298 Watch timer clock selection register 233 Watch timer function 230 Watch timer mode control register 2...

Page 514: ...User s Manual U13850EJ4V0UM 514 MEMO...

Page 515: ...86 2 2719 5951 Address North America NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Technical Documentation Dept Fax 49 211 6503...

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