CHAPTER 3 CPU FUNCTIONS
User’s Manual U13850EJ4V0UM
76
3.2.2 System register set
System registers control the status of the CPU and hold interrupt information.
Table 3-2. System Register Numbers
No.
System Register Name
Usage
Operation
0
EIPC
1
EIPSW
Interrupt status saving registers
These registers save the PC and PSW when an
exception or interrupt occurs. Because only one set of
these registers is available, their contents must be
saved when multiple interrupts are enabled.
2
FEPC
3
FEPSW
NMI status saving registers
These registers save PC and PSW when NMI occurs.
4
ECR
Interrupt source register
If exception, maskable interrupt, or NMI occurs, this
register will contain information referencing the
interrupt source. The higher 16 bits of this register are
called FECC, to which exception code of NMI is set.
The lower 16 bits are called EICC, to which exception
code of exception/interrupt is set.
5
PSW
Program status word
A program status word is a collection of flags that
indicate program status (instruction execution result)
and CPU status.
6 to 31
Reserved
To read/write these system registers, specify a system register number indicated by the system register load/store
instruction (LDSR or STSR instruction).
(1) Interrupt source register (ECR)
Figure 3-3. Interrupt Source Register (ECR)
After reset: 00000000H
Symbol
31
16
15
0
ECR
FECC
EICC
FECC
Exception code of NMI (For exception code, refer to
Table 5-1
.)
EICC
Exception code of exception/interrupt
