CHAPTER 9 WATCHDOG TIMER
User’s Manual U13850EJ4V0UM
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(3) Watchdog timer mode register (WDTM)
This register sets the operating mode of the watchdog timer, and enables and disables counting.
WDTM is set by an 8-/1-bit memory manipulation instruction.
RESET input clears WDTM to 00H.
Figure 9-4. Watchdog Timer Mode Register (WDTM)
After reset: 00H
R/W
Address: FFFFF384H
<7>
6
5
4
3
2
1
0
WDTM
RUN
0
0
WDTM4
0
0
0
0
RUN
Operating mode selection for the watchdog timer
Note 1
0
Disable count
1
Clear count and start counting
WDTM4
Operating mode selection for the watchdog timer
Note 2
0
Interval timer mode
(If an overflow occurs, a maskable interrupt INTWDTM is generated.)
1
Watchdog timer mode 1
(If an overflow occurs, a non-maskable interrupt INTWDT is generated.)
Notes 1.
Once RUN is set (1), the register cannot be cleared (0) by software. Therefore, when the count starts,
the count cannot be stopped except by RESET input.
2.
Once WDTM4 is set (1), the register cannot be cleared (0) by software.
Caution If RUN is set (1) and the watchdog timer is cleared, the actual overflow time may be up to 2
10
/f
XX
seconds less than the set time.
