APPENDIX A MIPS III INSTRUCTION SET DETAILS
524
Preliminary User’s Manual S15543EJ1V0UM
MACC
Multiply and Accumulate (3/5)
MACC
Operation:
32, sat=0, hi=0, us=0 (MACC instruction)
T:
temp1
←
GPR[rs] * GPR[rt]
temp2
←
temp1 + (HI || LO)
LO
←
temp2
63..32
HI
←
temp2
31..0
GPR[rd]
←
LO
32, sat=0, hi=0, us=1 (MACCU instruction)
T:
temp1
←
(0 || GPR[rs]) * (0 || GPR[rt])
temp2
←
temp1 + ((0 || HI) || (0 || LO))
LO
←
temp2
63..32
HI
←
temp2
31..0
GPR[rd]
←
LO
32, sat=0, hi=1, us=0 (MACCHI instruction)
T:
temp1
←
GPR[rs] * GPR[rt]
temp2
←
temp1 + (HI || LO)
LO
←
temp2
63..32
HI
←
temp2
31..0
GPR[rd]
←
HI
32, sat=0, hi=1, us=1 (MACCHIU instruction)
T:
temp1
←
(0 || GPR[rs]) * (0 || GPR[rt])
temp2
←
temp1 + ((0 || HI) || (0 || LO))
LO
←
temp2
63..32
HI
←
temp2
31..0
GPR[rd]
←
HI
32, sat=1, hi=0, us=0 (MACCS instruction)
T:
temp1
←
GPR[rs] * GPR[rt]
temp2
←
saturation(temp1 + (HI || LO))
LO
←
temp2
63..32
HI
←
temp2
31..0
GPR[rd]
←
LO
32, sat=1, hi=0, us=1 (MACCUS instruction)
T:
temp1
←
(0 || GPR[rs]) * (0 || GPR[rt])
temp2
←
saturation(temp1 + ((0 || HI) || (0 || LO)))
LO
←
temp2
63..32
HI
←
temp2
31..0
GPR[rd]
←
LO