APPENDIX A MIPS III INSTRUCTION SET DETAILS
Preliminary User’s Manual S15543EJ1V0UM
479
DMACC
Doubleword Multiply and Accumulate (3/3)
DMACC
Operation:
64, sat=0, us=0 (DMACC instruction)
T:
temp1
←
((GPR[rs]
31
)
32
|| GPR [rs]) * ((GPR[rt]
31
)
32
|| GPR [rt])
temp2
←
temp1 + LO
LO
←
temp2
GPR[rd]
←
LO
64, sat=0, us=1 (DMACCU instruction)
T:
temp1
←
(0
32
|| GPR [rs]) * (0
32
|| GPR [rt])
temp2
←
temp1 + LO
LO
←
temp2
GPR[rd]
←
LO
64, sat=1, us=0 (DMACCS instruction)
T:
temp1
←
((GPR[rs]
31
)
32
|| GPR [rs]) * ((GPR[rt]
31
)
32
|| GPR [rt])
temp2
←
saturation(temp1 + LO)
LO
←
temp2
GPR[rd]
←
LO
64, sat=1, us=1 (DMACCUS instruction)
T:
temp1
←
(0
32
|| GPR [rs]) * (0
32
|| GPR [rt])
temp2
←
saturation(temp1 + LO)
LO
←
temp2
GPR[rd]
←
LO
Exceptions:
Reserved instruction exception (32-bit user mode/supervisor mode)