CHAPTER 3 SYSTEM CONTROLLER
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Preliminary User’s Manual S15543EJ1V0UM
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66-MHz IBUS clock rate
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Supports 266-MB/sec (32 bits @66 MHz) bursts on IBUS.
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Support endian conversion between memory and IBUS slave I/F
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Support endian conversion between SyaAD bus and IBUS master I/F
3.1.4 UART
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Universal Asynchronous Receiver/Transmitter
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Modem control functions
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Even, odd or no parity bit generation
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Fully prioritized interrupt control
3.1.5 EEPROM
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165/250-kHz clock rate (Depend on CPU clock rate ; 66/100 MHz)
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Support only 3.3-V EEPROM (Recommended National Semiconductor’s “NM93C46”)
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Support Micro Wire interface for Serial EEPROM
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Support auto-load function for two addresses of MAC at system boot
3.1.6 Timer
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Two 32-bit loadable general-purpose timers generating interrupt to CPU
3.1.7 Interrupt controller
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Generates NMI and INT
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All interrupt causing events maskable
3.1.8 DSU (Deadman’s SW Unit)
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Deadman’s SW Unit generates cold reset to CPU