APPENDIX A MIPS III INSTRUCTION SET DETAILS
Preliminary User’s Manual S15543EJ1V0UM
525
MACC
Multiply and Accumulate (4/5)
MACC
32, sat=1, hi=1, us=0 (MACCHIS instruction)
T:
temp1
←
GPR[rs] * GPR[rt]
temp2
←
saturation(temp1 + (HI || LO))
LO
←
temp2
63..32
HI
←
temp2
31..0
GPR[rd]
←
HI
32, sat=1, hi=1, us=1 (MACCHIUS instruction)
T:
temp1
←
(0 || GPR[rs]) * (0 || GPR[rt])
temp2
←
saturation(temp1 + ((0 || HI) || (0 || LO)))
LO
←
temp2
63..32
HI
←
temp2
31..0
GPR[rd]
←
HI
64, sat=0, hi=0, us=0 (MACC instruction)
T:
temp1
←
((GPR[rs]
31
)
32
|| GPR[rs]) * ((GPR[rt]
31
)
32
|| GPR[rt])
temp2
←
temp1 + (HI
31..0
|| LO
31..0
)
LO
←
((temp2
63
)
32
|| temp2
63..32
)
HI
←
((temp2
31
)
32
|| temp2
31..0
)
GPR[rd]
←
LO
64, sat=0, hi=0, us=1 (MACCU instruction)
T:
temp1
←
(0
32
|| GPR[rs]) * (0
32
|| GPR[rt])
temp2
←
temp1 + (HI
31..0
|| LO
31..0
)
LO
←
((temp2
63
)
32
|| temp2
63..32
)
HI
←
((temp2
31
)
32
|| temp2
31..0
)
GPR[rd]
←
LO
64, sat=0, hi=1, us=0 (MACCHI instruction)
T:
temp1
←
((GPR[rs]
31
)
32
|| GPR[rs]) * ((GPR[rt]
31
)
32
|| GPR[rt])
temp2
←
temp1 + (HI
31..0
|| LO
31..0
)
LO
←
((temp2
63
)
32
|| temp2
63..32
)
HI
←
((temp2
31
)
32
|| temp2
31..0
)
GPR[rd]
←
HI
64, sat=0, hi=1, us=1 (MACCHIU instruction)
T:
temp1
←
(0
32
|| GPR[rs]) * (0
32
|| GPR[rt])
temp2
←
temp1 + (HI
31..0
|| LO
31..0
)
LO
←
((temp2
63
)
32
|| temp2
63..32
)
HI
←
((temp2
31
)
32
|| temp2
31..0
)
GPR[rd]
←
HI