User’s Manual U17307EJ2V0UM
60
CHAPTER 7 NOTES ON TARGET SYSTEMS
This chapter explains the basic notes on the target system for rewriting the flash memory in the microcontroller
using the FPL2.
CPU Pin
Design Proposal
Do not connect the RESET signal generator on the target system to the RESET signal of the FPL2. Otherwise,
a signal conflict will occur. To avoid the conflict, isolate the RESET signal generator from the RESET signal of
the FPL2.
Do not generate RESET while the FPL2 is connected. This must be especially noted in a system that uses an
external watchdog timer.
RESET
Connect the RESET signal of the FPL2 at a point where the status of the programmer RESET signal and that of
the CPU RESET pin are the same.
Correct connection:
CPU
FPL2 RESET
RESET
Avoid the following RESET signal connection.
•
Connection to a point where the target CPU RESET rise time is slower than the FPL2 RESET rise time.
Incorrect connection:
CPU
OC
FPL2 RESET
RESET
It takes time for the CPU RESET pin to go high after the FPL2 RESET level goes from low to high.
