1 - 16
• Study of S/G clamp responsiveness
The clamp responsiveness is determined by the response time (80nsec Typ.) of the comparator
(IC202, IC203) and the responsiveness of the drive circuit that gives the clamp potential to the
video. The responsiveness of the drive circuit is explained below.
The transistor turns ON when the comparator output is Lo. At this time, the transistor's base
voltage is 2.9V due to the voltage dividing of R1 and R2. [ =4.7k
Ω
x 5V / (4.7k
Ω
+3.3k
Ω
) ]
When V
EB
= 0.6V, the emitter's voltage is 3.5V, and a 15mA emitter current flows when the
transistor is ON [(5.0V - 3.5V)/100
Ω
]. When this is expressed as an equivalence circuit, it is as
shown on the right.
The capacitor C1 is charged with a constant current, so as shown below, the clamp voltage
output's step response is a linear response instead of a primary response. (As an image, this
is not a phase control such as with a servo, and instead is equivalent to speed control. Thus,
the response is fast.)
When Q = C • EV, then
∆
t = (C/I) •
∆
V
= (0.1
µ
F/15mA) •
∆
V
= 6.7
µ
•
∆
V
(Example)
If the minimum value of the H-SYNC width is 0.5
µ
sec, the maximum voltage fluctuation width
that can be compensated at 0.5
µ
sec is 0.075V according to the above formula. For CRT
(FHX7120), this is 0.079V which is approximately the same.
Study of S/G circuit fluctuation and input signal fluctuation
The A5V power voltage is 5V
±
0.1V and the voltage dividing resistor has a
±
1% fluctuation,
so the slice level - clamp level is within the following range.
(Slice level - clamp level) Max.
0.118V=390x1.01x5.1/((12000+120+4700))x0.99+390x1.01)
(Slice level - clamp level) Typ.
0.113V=390x5/(12000+120+390+4700)
(Slice level - clamp level) Min.
0.109V=390x0.99x4.9/((12000+120+4700))x1.01+390x0.99)
The S/G synchronizing signal amplitude has a 0.25V to 0.35V amplitude fluctuation. However,
the (slice level - clamp level) Max. = 0.118V is smaller than this, there are no problems design-
wise.
C1
A5V
10K
Ω
100
Ω
104
+
-
3.3K
Ω
4.7K
Ω
15mA
At comparator output Lo : 2.9V
At comparator output Lo : 3.5V
R1
R2
C1
10K
Ω
104
A5V
15mA
On / Off control
FB
80nsec delay
IC202, IC203
Q204, Q207
Clamp voltage output
Clamp voltage output
Summary of Contents for NEC MultiSync LCD1550X LCD1550X LCD1550X
Page 88: ...SCHEMATIC DIAGRAM POWER LCD1550X Normal Power Save 1ch Pin 4 2ch Pin 1 3ch Pin 2 4ch Pin 5...
Page 89: ...SCHEMATIC DIAGRAM PWB MAIN POWER LCD1550X...
Page 90: ...SCHEMATIC DIAGRAM PWB MAIN INPUT LCD1550X...
Page 91: ...SCHEMATIC DIAGRAM PWB MAIN SYNC LCD1550X...
Page 92: ...SCHEMATIC DIAGRAM PWB MAIN TMDS LCD1550X...
Page 96: ...SCHEMATIC DIAGRAM PWB MAIN ASIC LCD1550X...
Page 97: ...SCHEMATIC DIAGRAM INVERTER LCD1550X 1ch Q701 B 2ch Q702 B...
Page 98: ...SCHEMATIC DIAGRAM PWB SW LCD1550X...
Page 100: ...SCHEMATIC DIAGRAM POWER LCD1550X...
Page 101: ...SCHEMATIC DIAGRAM PWB MAIN POWER LCD1550X...
Page 102: ...SCHEMATIC DIAGRAM PWB MAIN INPUT LCD1550X...
Page 103: ...SCHEMATIC DIAGRAM PWB MAIN SYNC LCD1550X...
Page 104: ...SCHEMATIC DIAGRAM PWB MAIN TMDS LCD1550X...
Page 105: ...SCHEMATIC DIAGRAM PWB MAIN MC LCD1550X...
Page 106: ...SCHEMATIC DIAGRAM PWB MAIN ASIC LCD1550X...
Page 107: ...SCHEMATIC DIAGRAM INVERTER LCD1550X...
Page 108: ...SCHEMATIC DIAGRAM PWB SW LCD1550X...
Page 127: ...16 Document No VSPF A028 Bave Average brightness of 1 to 9 10 50 90 90 10 50 5 1 2 3 6 9 8 7 4...
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