1 - 15
1.4.4
Sync On Green synchronization separating circuit
Description of operations
The Green signal with 1V
P-P
sync is input into FET (Q202, Q208) of the source follower circuit.
This is because it is led in directly from the Green signal line's 75
Ω
terminator, so the input
impedance is increased as high as possible, to reduce the effect of noise even if a slight pat-
tern in led in. A source follower circuit FET (Q202, Q208) with small input capacity (2SK360 is
Typ. 2.5pF) for higher harmonics (VHF) is used to avoid damping of the signal waveform
caused by the input capacity. A grade E which I
DSS
is between 6 and 10mA is used so that the
FET operation point is V
GS
= -0.3V and I
D
= 5mA. With this, the bias voltage on the + polarity
side of C210 and C242 is 2.8V.
(A voltage value that does not cause a reverse polarity when the polar capacitor C210 and
C242 are in the steady state or power save state is selected.)
The input signal C-cut at 47
µ
F is compared at the clamp level voltage (1.36V) and bottom
clamp comparator (IC202, IC203).
If the input signal sync (negative polarity) is lower than the clamp level voltage, the transistor
(Q204, Q207) turns ON during the sync interval, and the input signal sync is raised by charging
C202 and C236. The input signal is sync clamped with this operation. Next, the clamped input
signal and voltage (1.48V) are compared at the slice comparator (IC202, IC203) to separate
the composite sync from the video. The voltage is set so that the slice level is applied at the
center of the analog sync (0.3V
P-P
).
LC1550X has two analog inputs DCI-I(A) and D-SUB, and has the LAST DETECT function as
one of the VIDEO DETECT functions. The displayed and selected signals and the signals not
displayed or selected must be judged, so there are two Sync On Green synchronization sepa-
rating circuits.
Video input cutoff frequency
f
ch
= 1/2
π
CR = 1/2
π
· 10
µ
F · 100k
Ω
/ / 100k
Ω
=0.32Hz << 50Hz
A5V
+
-
+
-
NJM319V
47
µ
100
Ω
10
µ
472
104
Video input
(Green) 1V
P-P
Composite sync output
10
µ
220
Ω
560
Ω
1K
Ω
100K
Ω
100K
Ω
2SK360
104
1.36V (clamp level)
1.48V (slice level)
5mA
105
+
For slicing
S/G Sep. circuit
15mA
Q202 ,Q208
Q204, Q207
C202, C236
C210, C242
5.6K
Ω
150
Ω
1.48V
220
Ω
10K
Ω
1.36V
2.2K
Ω
3.3K
Ω
4.7K
Ω
470
Ω
10K
Ω
2.8V
2.5V
2.36V
1.66V
As comparator decoupling
capacity is large.
Input capacity
must be small.
For bottom
clamp
f characteristics
must be good.
Summary of Contents for NEC MultiSync LCD1550X LCD1550X LCD1550X
Page 88: ...SCHEMATIC DIAGRAM POWER LCD1550X Normal Power Save 1ch Pin 4 2ch Pin 1 3ch Pin 2 4ch Pin 5...
Page 89: ...SCHEMATIC DIAGRAM PWB MAIN POWER LCD1550X...
Page 90: ...SCHEMATIC DIAGRAM PWB MAIN INPUT LCD1550X...
Page 91: ...SCHEMATIC DIAGRAM PWB MAIN SYNC LCD1550X...
Page 92: ...SCHEMATIC DIAGRAM PWB MAIN TMDS LCD1550X...
Page 96: ...SCHEMATIC DIAGRAM PWB MAIN ASIC LCD1550X...
Page 97: ...SCHEMATIC DIAGRAM INVERTER LCD1550X 1ch Q701 B 2ch Q702 B...
Page 98: ...SCHEMATIC DIAGRAM PWB SW LCD1550X...
Page 100: ...SCHEMATIC DIAGRAM POWER LCD1550X...
Page 101: ...SCHEMATIC DIAGRAM PWB MAIN POWER LCD1550X...
Page 102: ...SCHEMATIC DIAGRAM PWB MAIN INPUT LCD1550X...
Page 103: ...SCHEMATIC DIAGRAM PWB MAIN SYNC LCD1550X...
Page 104: ...SCHEMATIC DIAGRAM PWB MAIN TMDS LCD1550X...
Page 105: ...SCHEMATIC DIAGRAM PWB MAIN MC LCD1550X...
Page 106: ...SCHEMATIC DIAGRAM PWB MAIN ASIC LCD1550X...
Page 107: ...SCHEMATIC DIAGRAM INVERTER LCD1550X...
Page 108: ...SCHEMATIC DIAGRAM PWB SW LCD1550X...
Page 127: ...16 Document No VSPF A028 Bave Average brightness of 1 to 9 10 50 90 90 10 50 5 1 2 3 6 9 8 7 4...
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