NEC Mu754202, Datasheet

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30
µ
PD754202, 754202(A)
Table 9-1. Hardware Status After Reset (1/3)
Hardware
RESET signal generation RESET signal generation
in the standby mode in operation
Program counter (PC) Sets the low-order 3 bits of Sets the low-order 3 bits of
program memory’s address program memory’s address
0000H to the PC10-PC8 and the 0000H to the PC10-PC8 and the
contents of address 0001H to contents of address 0001H to
the PC7-PC0. the PC7-PC0.
PSW Carry flag (CY) Held Undefined
Skip flag (SK0-SK2) 0 0
Interrupt status flag (IST0, IST1) 0 0
Bank enable flag (MBE, RBE) Sets the bit 6 of program Sets the bit 6 of program
memory’s address 0000H to memory’s address 0000H to
the RBE and bit 7 to the MBE. the RBE and bit 7 to the MBE.
Stack pointer (SP) Undefined Undefined
Stack bank select register (SBS) 1000B 1000B
Data memory (RAM) Held Undefined
General-purpose register (X, A, H, L, D, E, B, C) Held Undefined
Bank select register (MBS, RBS) 0, 0 0, 0
Basic interval Counter (BT) Undefined Undefined
timer/watchdog Mode register (BTM) 0 0
timer Watchdog timer enable flag (WDTM) 0 0
Timer counter Counter (T0) 0 0
(T0) Modulo register (TMOD0) FFH FFH
Mode register (TM0) 0 0
TOE0, TOUT F/F 0, 0 0, 0
Timer counter Counter (T1) 0 0
(T1) Modulo register (TMOD1) FFH FFH
Mode register (TM1) 0 0
TOE1, TOUT F/F 0, 0 0, 0
Timer counter Counter (T2) 0 0
(T2) Modulo register (TMOD2) FFH FFH
High-level period setting modulo FFH FFH
register (TMOD2H)
Mode register (TM2) 0 0
TOE2, TOUT F/F 0, 0 0, 0
REMC, NRZ, NRZB 0, 0, 0 0, 0, 0