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CHAPTER 4 PORT FUNCTIONS

Preliminary User’s Manual U14581EJ3V0UM00

4.2.3 Port 2

Port 2 is an 8-bit output only port with output latch. P20 to P27 pins go into a high-impedance state when the ENn

of port mode control register (PMC) is set to 0 and the port mode register 2 (PM2) is set to 1.

Alternate functions include meter control PWM output.

RESET input sets port 2 to high-impedance state.

Figure 4-4 shows a block diagram of port 2.

Figure 4-4. P20 to P27 Block Diagram

P20/SM11 to P23/SM14
P24/SM21 to P27/SM24

PORT

Output latch

(P20 to P27)

Selector

Decoder

PM20 to PM27

Alternate
functions

Internal bus

DIRn1 DIRn0

MODn ENn

PM: Port mode register

RD: Port 2 read signal

WR: Port 2 write signal

Caution

When PM2 is set to 0, read operation is enabled. When PM2 is set to 1, read operation is disabled.

Remark

n = 1, 2

Summary of Contents for mPD780851

Page 1: ...minary User s Manual Printed in Japan µPD780852 Subseries 8 Bit Single Chip Microcontrollers µPD780851 A µPD780852 A µPD78F0852 Document No U14581EJ3V0UM00 3rd edition Date Published October 2000 J CP K 2000 ...

Page 2: ...2 Preliminary User s Manual U14581EJ3V0UM00 MEMO ...

Page 3: ... 143 CHAPTER 11 CLOCK OUTPUT CONTROLLER 149 CHAPTER 12 A D CONVERTER 153 CHAPTER 13 SERIAL INTERFACE UART 169 CHAPTER 14 SERIAL INTERFACE SIO2 187 CHAPTER 15 SERIAL INTERFACE SIO3 201 CHAPTER 16 LCD CONTROLLER DRIVER 207 CHAPTER 17 SOUND GENERATOR 223 CHAPTER 18 METER CONTROLLER DRIVER 231 CHAPTER 19 INTERRUPT FUNCTIONS 241 CHAPTER 20 STANDBY FUNCTION 263 CHAPTER 21 RESET FUNCTION 271 CHAPTER 22 µ...

Page 4: ...anging description of supply voltage in 1 8 Outline of Function p 107 Changing 6 4 4 Port mode register 4 PM4 p 111 Changing Figure 6 11 Capture Register Data Retention Timing p 211 Adding Caution 3 to Figure 16 4 LCD Display Control Register LCDC Format p 278 Adding Note to Table 22 3 Transmission Method List The mark shows major revised points ...

Page 5: ...ing bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor devices on it 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs can be cause ...

Page 6: ...arties arising from the use of these circuits software and information While NEC endeavours to enhance the quality reliability and safety of NEC semiconductor products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC semiconductor products cu...

Page 7: ...C Electronics Germany GmbH Duesseldorf Germany Tel 0211 65 03 02 Fax 0211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Italiana s r l Milano Italy Tel 02 66 75 41 Fax 02 66 75 42 99 NEC Electronics Germany GmbH Benelux Office Eindhoven The Netherlands Tel 040 2445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 0...

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Page 9: ...d microcontrollers To understand the functions of the µPD780851 A 780852 A and 78F0852 in general Read this manual in the order of the CONTENTS How to read register formats The name of a bit whose number is enclosed in square is reserved for the RA78K 0 and is defined for the CC78K 0 by the header file sfrbit h To learn the detailed functions of a register whose register name is known See APPENDIX...

Page 10: ...U11801E Structured Assembly Language U11789J U11789E CC78K0 C Compiler Operation U11517J U11517E Language U11518J U11518E CC78K0 C Compiler Application Note Programming Know how U13034J U13034E IE 78K0 NS U13731J U13731E IE 780852 NS EM4 To be prepared To be prepared SM78K0 System Simulator WindowsTM Base Reference U10181J U10181E SM78K Series System Simulator External Part User Open U10092J U1009...

Page 11: ...or Device C11531J C11531E NEC Semiconductor Device Reliability Quality Control System C10983J C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge ESD C11892J C11892E Semiconductor Device Quality Control Reliability Handbook U12769J Guide for Products Related to Micro Computer Other Companies U11416J Caution The above documents are subject to change without prior no...

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Page 13: ... Port 4 39 2 2 6 P50 to P54 Port 5 40 2 2 7 P60 P61 Port 6 40 2 2 8 P81 to P87 Port 8 41 2 2 9 P90 to P97 Port 9 41 2 2 10 COM0 to COM3 41 2 2 11 VLCD 41 2 2 12 AVREF 41 2 2 13 AVSS 41 2 2 14 RESET 41 2 2 15 X1 and X2 41 2 2 16 SMVDD 42 2 2 17 SMVSS 42 2 2 18 VDD0 42 2 2 19 VROUT 42 2 2 20 VSS0 VSS1 42 2 2 21 VPP µPD78F0852 only 42 2 2 22 IC Mask ROM version only 42 2 3 Input Output Circuits and R...

Page 14: ...g 73 CHAPTER 4 PORT FUNCTIONS 75 4 1 Port Functions 75 4 2 Port Configuration 77 4 2 1 Port 0 77 4 2 2 Port 1 78 4 2 3 Port 2 79 4 2 4 Port 3 80 4 2 5 Port 4 81 4 2 6 Port 5 82 4 2 7 Port 6 83 4 2 8 Port 8 84 4 2 9 Port 9 85 4 3 Port Function Control Registers 86 4 4 Port Function Operations 89 4 4 1 Writing to input output port 89 4 4 2 Reading from input output port 89 4 4 3 Operations on input ...

Page 15: ...3 8 3 8 Bit Timer Event Counters 2 TM2 and 3 TM3 Control Registers 124 8 4 8 Bit Timer Event Counters 2 TM2 and 3 TM3 Operations 128 8 4 1 8 bit interval timer operation 128 8 4 2 External event counter operation 130 8 4 3 Square wave output operation 8 bit resolution 131 8 4 4 8 bit PWM output operation 132 8 5 8 Bit Timer Event Counters 2 TM2 and 3 TM3 Cautions 135 CHAPTER 9 WATCH TIMER 137 9 1 ...

Page 16: ...SERIAL INTERFACE SIO2 187 14 1 Serial Interface Functions 187 14 2 Serial Interface Configuration 188 14 3 Serial Interface Control Registers 189 14 4 Serial Interface Operations 193 14 4 1 Operation stop mode 193 14 4 2 3 wire serial I O mode 194 CHAPTER 15 SERIAL INTERFACE SIO3 201 15 1 Serial Interface Functions 201 15 2 Serial Interface Configuration 202 15 3 Serial Interface Control Register ...

Page 17: ...Sources and Configuration 241 19 3 Interrupt Function Control Registers 245 19 4 Interrupt Servicing Operations 252 19 4 1 Non maskable interrupt request acknowledge operation 252 19 4 2 Maskable interrupt request acknowledge operation 255 19 4 3 Software interrupt request acknowledge operation 257 19 4 4 Multiple interrupt servicing 258 19 4 5 Interrupt request hold 261 CHAPTER 20 STANDBY FUNCTIO...

Page 18: ...Instructions Listed by Addressing Type 292 APPENDIX A DEVELOPMENT TOOLS 297 A 1 Language Processing Software 299 A 2 Flash Memory Writing Tools 300 A 3 Debugging Tools 301 A 3 1 Hardware 301 A 3 2 Software 302 APPENDIX B EMBEDDED SOFTWARE 305 APPENDIX C REGISTER INDEX 307 C 1 Register Index in Alphabetical Order with Respect to Register Name 307 C 2 Register Index in Alphabetical Order with Respec...

Page 19: ...lock Diagram 82 4 8 P60 and P61 Block Diagram 83 4 9 P81 to P87 Block Diagram 84 4 10 P90 to P97 Block Diagram 85 4 11 Port Mode Register PM0 PM4 to PM6 PM8 PM9 Format 87 4 12 Port Mode Register PM2 PM3 Format 87 4 13 Pull Up Resistor Option Register PU0 Format 88 5 1 Clock Generator Block Diagram 91 5 2 Processor Clock Control Register PCC Format 92 5 3 Oscillator Mode Register OSCM Format 93 5 4...

Page 20: ...mat 126 8 6 Port Mode Register 4 PM4 Format 127 8 7 Interval Timer Operation Timings 128 8 8 External Event Counter Operation Timings with Rising Edge Specified 131 8 9 PWM Output Operation Timing 133 8 10 Operation Timing by Change of CRn 134 8 11 8 Bit Counters 2 and 3 TM2 and TM3 Start Timing 135 8 12 Timing after Compare Register Change during Timer Count Operation 135 9 1 Watch Timer Block Di...

Page 21: ...nterface SIO2 Block Diagram 187 14 2 Serial Operation Mode Register 2 CSIM2 Format 189 14 3 Serial Transfer Operation Timing According to CLPO and CLPH Settings 190 14 4 Serial Receive Data Buffer Status Register SRBS2 Format 191 14 5 Port Mode Register 0 PM0 Format 192 14 6 Operation Timing When CLPH Is Set to 0 Serial output data 55H serial input data AAH 197 14 7 Operation Timing When CLPH Is S...

Page 22: ...K1L Format 247 19 4 Priority Specify Flag Register PR0L PR0H PR1L Format 248 19 5 External Interrupt Rising Edge Enable Register EGP and External Interrupt Falling Edge Enable Register EGN Format 249 19 6 Prescaler Mode Register PRM0 Format 250 19 7 Program Status Word Format 251 19 8 Non Maskable Interrupt Request Generation to Acknowledge Flowchart 253 19 9 Non Maskable Interrupt Request Acknowl...

Page 23: ...2 2 Internal Expansion RAM Size Switching Register IXS Format 277 22 3 Transmission Method Selection Format 278 22 4 Flashpro III Connection Using 3 Wire Serial I O Method SIO3 280 22 5 Flashpro III Connection Using 3 Wire Serial I O Method SIO2 280 22 6 Flashpro III Connection Using UART Method 280 A 1 Development Tool Configuration 298 ...

Page 24: ...ations 123 9 1 Interval Timer Interval Time 138 9 2 Watch Timer Configuration 138 9 3 Interval Timer Interval Time 140 10 1 Watchdog Timer Runaway Detection Time 144 10 2 Interval Time 144 10 3 Watchdog Timer Configuration 145 10 4 Watchdog Timer Runaway Detection Time 147 10 5 Interval Timer Interval Time 148 11 1 Clock Output Controller Configuration 149 12 1 A D Converter Configuration 155 13 1...

Page 25: ...Source List 242 19 2 Flags Corresponding to Interrupt Request Sources 245 19 3 Times from Generation of Maskable Interrupt Request until Servicing 255 19 4 Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing 258 20 1 HALT Mode Operating Status 265 20 2 Operation after HALT Mode Clear 267 20 3 STOP Mode Operating Status 268 20 4 Operation after STOP Mode Clear 270 21 1 Hardw...

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Page 27: ...ding pins that have an alternate function as segment signal output 8 bit resolution A D converter 5 channels Sound generator 1 channel Meter controller driver PWM output 8 bit resolution 16 Can set pulse width with a precision of 8 1 bits with 1 bit addition function LCD controller driver Segment signal output 20 max Common signal output 4 max Bias 1 3 bias Power supply voltage VLCD 3 0 V to VDD S...

Page 28: ...emory Remark indicates ROM code suffix 1 4 Quality Grade Part Number Package Quality Grade µPD78F0852GC 8BT 80 pin plastic QFP 14 14 mm Standard µPD780851GC A 8BT 80 pin plastic QFP 14 14 mm Special µPD780852GC A 8BT 80 pin plastic QFP 14 14 mm Special Remark indicates ROM code suffix Please refer to Quality Grades on NEC Semiconductor Device Document No C11531E published by NEC Corporation to kno...

Page 29: ...0 79 78 77 P90 S12 P91 S11 P92 S10 P86 S14 P87 S13 P93 S9 P94 S8 P95 S7 P96 S6 P97 S5 S4 S3 S2 S1 S0 COM3 COM2 COM1 COM0 V LCD 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P85 S15 P84 S16 P83 S17 P82 S18 P81 S19 IC VPP X1 X2 VSS1 VROUT P07 P06 P05 SI2 P04 SO2 P03 SCK2 P02 INTP2 P01 INTP1 P00 INTP0 AVREF RESET Cautions 1 Connect IC Inte...

Page 30: ...eter Controller Power Supply P00 to P07 Port0 SMVSS Meter Controller Ground P10 to P14 Port1 SO2 SO3 Serial Output P20 to P27 Port2 TI00 to TI02 Timer Input P30 to P37 Port3 TIO2 TIO3 Timer Output Event Counter Input P40 to P44 Port4 TPO Prescaler Output P50 to P54 Port5 TxD Transmit Data P60 P61 Port6 VDD0 Power Supply P81 to P87 Port8 VLCD LCD Power Supply P90 to P97 Port9 VPP Programming Power ...

Page 31: ...ed EMI noise reduced version of the PD78064 Basic subseries for driving LCDs on chip UART PD780833Y 80 pin On chip J1850 CLASS2 controller PD78098B PD780701Y PD780852 80 pin 80 pin 80 pin Meter control Bus interface IEBusTM controller was added to the PD78054 EMI noise reduced version On chip DCAN IEBus controller On chip automobile meter driving controller driver Products in mass production Produ...

Page 32: ...6 K 1 ch UART 1 ch 33 Inverter µPD780988 16 K to 60 K 3 ch Note 1 ch 8 ch 3 ch UART 2 ch 47 4 0 V Available control VFD µPD780208 32 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch 2 ch 74 2 7 V µPD780232 16 K to 24 K 3 ch 4 ch 40 4 5 V µPD78044H 32 K to 48 K 2 ch 1 ch 1 ch 8 ch 1 ch 68 2 7 V µPD78044F 16 K to 40 K 2 ch LCD µPD780338 48 K to 60 K 3 ch 2 ch 1 ch 1 ch 10 ch 1 ch 2 ch UART 1 ch 54 1 8 V drive µPD...

Page 33: ...UT LCD CONTROLLER DRIVER WATCH TIMER SERIAL INTERFACE SIO3 SCK3 P50 SO3 P51 SI3 P52 TxD P54 RxD P53 A D CONVERTER POWER FAIL DETECTOR ANI0 P10 to ANI4 P14 PCL TPO P60 SGO P61 AVSS AVREF SERIAL INTERFACE SIO2 SCK2 P03 SO2 P04 SI2 P05 SYSTEM CONTROL X1 X2 RESET S0 to S4 S5 P97 to S12 P90 S13 P87 to S19 P81 SMVDD COM0 to COM3 METER CONTROLLER DRIVER SM11 P20 to SM14 P23 SM21 P24 to SM24 P27 SM31 P30 ...

Page 34: ... CMOS output 16 CMOS input output 35 A D converter 8 bit resolution 5 channels Power fail detection function LCD controller driver Segment signal outputs 20 max Common signal outputs 4 max Bias 1 3 bias only Serial interface 3 wire serial I O mode 2 channels UART mode 1 channel Timer 16 bit timer 1 channel 8 bit timer 1 channel 8 bit timer event counter 2 channels Watch timer 1 channel Watchdog ti...

Page 35: ...n be specified in 1 bit units SI3 P53 RxD P54 TxD P60 Input Output Input PCL TPO P61 SGO P81 to P87 Input Output Input S19 to S13 P90 to P97 Input Output Port 9 Input S12 to S5 8 bit input output port Input output mode can be specified in 1 bit units Can be set in I O port mode or segment output mode in 2 bit units with the LCD display control register LCDC Port 0 8 bit input output port Input out...

Page 36: ... input to capture register CR02 P42 TIO2 Input Output 8 bit timer TM2 input output also used for 8 bit PWM output Input P43 TIO3 8 bit timer TM3 input output also used for 8 bit PWM output P44 TPO Output Prescaler signal output of 16 bit timer TM0 Input PCL P60 PCL Output Clock output for main system clock trimming Input TPO P60 SGO Output Sound generator signal output Input P61 S0 to S4 Output Se...

Page 37: ...or output pin for power supply of pins other than port pins Connect this pin to VSS0 or VSS1 via a 0 1 µF capacitor VSS1 Ground potential except for port block VPP High voltage application for program write verify Connect directly to VSS0 or VSS1 in normal operation mode µPD78F0852 only IC Internally connected Connect directly to VSS0 or VSS1 ...

Page 38: ...ister 0 PU0 2 Control mode In this mode P00 to P07 function as external interrupt request input serial interface data input output and clock input output pins a INTP0 to INTP2 These are external interrupt input pins for which the valid edge rising edge falling edge and both the rising and falling edges can be specified b SI2 Serial interface serial data input pin c SO2 Serial interface serial data...

Page 39: ...ration modes can be specified in 1 bit units 1 Port mode In this mode P30 to P37 function as an 8 bit output only port They go into a high impedance state when 1 is set to port mode register 3 PM3 2 Control mode In this mode P30 to P37 function as PWM output pins SM31 to SM34 and SM41 to SM44 for meter control 2 2 5 P40 to P44 Port 4 These pins constitute a 5 bit input output port In addition they...

Page 40: ...Serial interface serial data output pin c SCK3 Serial interface serial clock input output pin d RxD TxD Asynchronous serial interface serial data input output pins 2 2 7 P60 P61 Port 6 These pins constitute a 2 bit input output port In addition they also function as clock output sound generator signal output and prescaler signal output pins The following operation modes can be specified in 1 bit u...

Page 41: ... 8 bit input output port They can be set in the input or output port in 1 bit units with the port mode register 9 PM9 2 Control mode In this mode P90 to P97 function as segment signal output pins S5 to S12 of the LCD controller driver 2 2 10 COM0 to COM3 These pins output common signals from the LCD controller driver during 4 time division drive in 1 3 bias mode COM0 to COM3 outputs 2 2 11 VLCD Th...

Page 42: ...d potential pin except for port block 2 2 21 VPP µPD78F0852 only A high voltage should be applied to this pin when the flash memory programming mode is set and when the program is written or verified Directly connect this pin to VSS0 or VSS1 in the normal operation mode 2 2 22 IC Mask ROM version only The IC Internally Connected pin is provided to set the test mode to check the µPD780852 Subseries...

Page 43: ...output Independently connect to VSS0 via a resistor P03 SCK2 P04 SO2 P05 SI2 P06 P07 P10 ANI0 to P14 ANI4 9 Input Independently connect to VDD0 or VSS0 via a resistor P20 SM11 to P23 SM14 4 Output Leave open P24 SM21 to P27 SM24 P30 SM31 to P33 SM34 P34 SM41 to P37 SM44 P40 TI00 to P42 TI02 8 Input output Independently connect to VDD0 or VSS0 via a resistor P43 TIO2 P44 TIO3 P50 SCK3 P51 SO3 5 P52...

Page 44: ...data output disable P ch IN OUT VDD N ch P ch VDD pullup enable Type 4 data output disable P ch OUT VDD N ch Type 8 A Type 8 Type 9 data output disable P ch IN OUT VDD N ch data output disable input enable P ch IN OUT VDD N ch input enable Comparator P ch N ch VREF Threshold voltage IN Push pull output whose output can go into a high impedance state both P ch and N ch are off ...

Page 45: ...O Circuits of Pins 2 2 Type 17 Type 18 Type 17 G VLC0 VLC1 SEG data VLC2 P ch N ch P ch N ch P ch N ch OUT VLC0 VLC1 COM data VLC2 P ch N ch P ch N ch P ch N ch OUT N ch P ch VLC0 VLC1 SEG data VLC2 P ch N ch P ch N ch P ch N ch P ch N ch input enable output disable data IN OUT VDD ...

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Page 47: ...l registers 32 8 bits Internal ROM 32 768 8 bits 7FFFH 1000H 0FFFH 0800H 07FFH 0080H 007FH 0040H 003FH 0000H CALLF entry area CALLT table area Vector table area Program area Program area LCD display RAM 20 4 bits Reserved Program memory space 8000H 7FFFH FA59H FA58H FA6DH FA6CH FEE0H FEDFH FF00H FEFFH FFFFH Internal high speed RAM 1 024 8 bits Special function registers SFRs 256 8 bits Reserved FB...

Page 48: ...00H 07FFH 0080H 007FH 0040H 003FH 0000H CALLF entry area CALLT table area Vector table area Program area Program area LCD display RAM 20 4 bits Reserved Program memory space A000H 9FFFH FA59H FA58H FA6DH FA6CH FEE0H FEDFH FF00H FEFFH FFFFH Internal high speed RAM 1 024 8 bits Special function registers SFRs 256 8 bits Reserved FB00H FAFFH Reserved Internal expansion RAM 512 8 bits F800H F7FFH F600...

Page 49: ...0H 07FFH 0080H 007FH 0040H 003FH 0000H CALLF entry area CALLT table area Vector table area Program area Program area LCD display RAM 20 4 bits Reserved Program memory space A000H 9FFFH FA59H FA58H FA6DH FA6CH FEE0H FEDFH FF00H FEFFH FFFFH Internal high speed RAM 1 024 8 bits Special function registers SFRs 256 8 bits Reserved FB00H FAFFH Reserved Internal expansion RAM 512 8 bits F800H F7FFH F600H...

Page 50: ...owing three areas are allocated to the program memory space 1 Vector table area The 64 byte area 0000H to 003FH is reserved as a vector table area This area stores program start addresses to which execution branches when the RESET signal is input or when an interrupt request is generated Of a 16 bit address the lower 8 bits are stored at an even address and the higher 8 bits are stored at an odd a...

Page 51: ... The 32 byte area FEE0H to FEFFH is allocated with four general purpose register banks composed of eight 8 bit registers The internal high speed RAM can be used as stack memory 2 LCD display RAM An LCD display RAM is allocated to an area of 20 4 bits at addresses FA59H to FA6CH The LCD display RAM can also be used as a normal RAM 3 Internal expansion RAM An internal expansion RAM is allocated to a...

Page 52: ...n particular special addressing methods designed for the functions of special function registers SFRs and general purpose registers are available for use Data memory addressing is illustrated in Figures 3 4 to 3 6 For the details of each addressing mode see 3 4 Operand Address Addressing Figure 3 4 Data Memory Addressing µPD780851 A 0000H General registers 32 8 bits Internal ROM 32 768 8 bits LCD ...

Page 53: ...H 9FFFH FA59H FA58H FA6DH FA6CH FEE0H FEDFH FF00H FEFFH FFFFH Internal high speed RAM 1 024 8 bits Reserved FB00H FAFFH FF20H FF1FH FE20H FE1FH Special function registers SFRs 256 8 bits SFR addressing Register addressing Short direct addressing Direct addressing Register indirect addressing Based addressing Based indexed addressing F800H F7FFH Reserved F600H F5FFH Reserved Internal expansion RAM ...

Page 54: ...H 9FFFH FA59H FA58H FA6DH FA6CH FEE0H FEDFH FF00H FEFFH FFFFH Internal high speed RAM 1 024 8 bits Reserved FB00H FAFFH FF20H FF1FH FE20H FE1FH Special function registers SFRs 256 8 bits SFR addressing Register addressing Short direct addressing Direct addressing Register indirect addressing Based addressing Based indexed addressing F800H F7FFH Reserved F600H F5FFH Reserved Internal expansion RAM ...

Page 55: ... of the instruction to be fetched When a branch instruction is executed immediate data and register contents are set RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter Figure 3 7 Program Counter Configuration PC 15 0 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 2 Program status word PSW The program status word is an 8 bit reg...

Page 56: ... and RBS1 These are 2 bit flags to select one of the four register banks In these flags the 2 bit information which indicates the register bank selected by SEL RBn instruction execution is stored d Auxiliary carry flag AC If the operation result has a carry from bit 3 or a borrow at bit 3 this flag is set to 1 It is reset to 0 in all other cases e In service priority flag ISP This flag manages the...

Page 57: ...res data as shown in Figures 3 10 and 3 11 Caution Since RESET input makes SP contents undefined be sure to initialize the SP before instruction execution Figure 3 10 Data to Be Saved to Stack Memory Interrupt and BRK instruction PSW PC15 to PC8 PC15 to PC8 PC7 to PC0 Register pair low SP SP _ 2 SP _ 2 Register pair high CALL CALLF and CALLT instructions PUSH rp instruction SP _ 1 SP SP SP _ 2 SP ...

Page 58: ...AX BC DE and HL and absolute names R0 to R7 and RP0 to RP3 Register banks to be used for instruction execution are set with the CPU control instruction SEL RBn Because of the 4 register bank configuration an efficient program can be created by switching between a register for normal processing and a register for interrupt processing for each bank Figure 3 12 General Register Configuration a Absolu...

Page 59: ...ulation instruction operand sfr This manipulation can also be specified with an address 16 bit manipulation Describe the symbol reserved with assembler for the 16 bit manipulation instruction operand sfrp When addressing an address describe an even address Table 3 3 gives a list of special function registers The meaning of items in the table is as follows Symbol Symbol indicating the address of a ...

Page 60: ... 3 CR3 FF0DH 8 bit counter 1 TM1 R FF0EH 8 bit counter 2 TM2 FF0FH 8 bit counter 3 TM3 FF10H Capture register 00 CR00 0000H FF11H FF12H Capture register 01 CR01 FF13H FF14H Capture register 02 CR02 FF15H FF16H 16 bit timer register 0 TM0 FF17H FF18H Serial I O shift register 3 SIO3 R W 00H FF19H Transmit shift register TXS W FFH Receive buffer register RXB R FFH FF1BH A D conversion result registe...

Page 61: ...ister cos side MCMP11 FF63H Compare register sin side MCMP20 FF64H Compare register cos side MCMP21 FF65H Compare register sin side MCMP30 FF66H Compare register cos side MCMP31 FF67H Compare register sin side MCMP40 FF68H Compare register cos side MCMP41 FF69H Timer mode control register MCNTC FF6AH Port mode control register PMC FF6BH Compare control register 1 MCMPC1 FF6CH Compare control regis...

Page 62: ...LCDC FFE0H Interrupt request flag register 0L IF0 IF0L FFE1H Interrupt request flag register 0H IF0H FFE2H Interrupt request flag register 1L IF1L FFE4H Interrupt mask flag register 0L MK0 MK0L FFH FFE5H Interrupt mask flag register 0H MK0H FFE6H Interrupt mask flag register 1L MK1L FFE8H Priority specify flag register 0L PR0 PR0L FFE9H Priority specify flag register 0H PR0H FFEAH Priority specify...

Page 63: ...lative addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program counter PC and branched The displacement value is treated as signed two s complement data 128 to 127 and bit 7 becomes a sign bit In other words relative addressing consists in relative branchin...

Page 64: ...t when the CALL addr16 BR addr16 or CALLF addr11 instruction is executed CALL addr16 and BR addr16 instructions can be branched to the entire memory space The CALLF addr11 instruction is branched to the 0800H to 0FFFH area Operation In the case of CALL addr16 and BR addr16 instructions 15 0 PC 8 7 7 0 CALL or BR Low Addr High Addr In the case of CALLF addr11 instruction 15 0 PC 8 7 7 0 fa10 8 11 1...

Page 65: ...is executed This instruction references the address stored in the memory table from 40H to 7FH and allows branching to the entire memory space Operation 15 1 15 0 PC 7 0 Low Addr High Addr Memory table Effective address 1 Effective address 0 1 0 0 0 0 0 0 0 0 8 7 8 7 6 5 0 0 1 1 1 7 6 5 1 0 ta4 0 Operation code 3 3 4 Register addressing Function Register pair AX contents to be specified with an in...

Page 66: ...ing Instruction Register to be Specified by Implied Addressing MULU Register A for multiplicand and register AX for product storage DIVUW Register AX for dividend and quotient storage ADJBA ADJBS Register A for storage of numeric values subject to decimal adjustment ROR4 ROL4 Register A for storage of digit data subject to digit rotation Operand format Because implied addressing can be automatical...

Page 67: ...llowing operand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the operation code Operand format Identifier Description r X A C B E D L H rp AX BC DE HL r and rp can be described with function names X A C B E D L H AX BC DE and HL as well as absolute names R0 to R7 and RP0 to RP3 Description example MOV A C when selecting C register as...

Page 68: ...ed with immediate data in an instruction word becoming an operand address Operand format Identifier Description addr16 Label or 16 bit immediate data Description example MOV A 0FE00H when setting addr16 to FE00H Operation code 1 0 0 0 1 1 1 0 OP code 0 0 0 0 0 0 0 0 00H 1 1 1 1 1 1 1 0 FEH Operation Memory 0 7 addr16 lower addr16 upper OP code ...

Page 69: ... capture register of the timer event counter are mapped and these SFRs can be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is set to 0 When it is at 00H to 1FH bit 8 is set to 1 Operand format Identifier Description saddr Label or FE20H to FF1FH immediate data saddrp Label or FE20H to FF1FH immediate data even address ...

Page 70: ...aces FF00H to FFCFH and FFE0H to FFFFH However the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing Operand format Identifier Description sfr Special function register name sfrp 16 bit manipulatable special function register name even address only Description example MOV PM0 A when selecting PM0 FF20H as sfr Operation code 1 1 1 1 0 1 1 0 OP code 0 0 1 0 0 0 0 0 20H sfr of...

Page 71: ...he register bank select flags RBS0 and RBS1 and the register pair specification code in the operation code This addressing can be carried out for all the memory spaces Operand format Identifier Description DE HL Description example MOV A DE when selecting DE as register pair Operation code 1 0 0 0 0 1 0 1 Operation 16 0 8 D 7 E 0 7 7 0 A DE The contents of the memory addressed are transferred Memo...

Page 72: ... Description HL byte Description example MOV A HL 10H when setting byte to 10H Operation code 1 0 1 0 1 1 1 0 0 0 0 1 0 0 0 0 3 4 8 Based indexed addressing Function The B or C register contents specified in an instruction word are added to the contents of the base register that is the HL register pair in an instruction word of the register bank specified with the register bank select flags RBS0 a...

Page 73: ... pointer SP contents This addressing method is automatically employed when the PUSH POP subroutine call and RETURN instructions are executed or the register is saved reset upon generation of an interrupt request Stack addressing enables to address the internal high speed RAM area only Description example In the case of PUSH DE Operation code 1 0 1 1 0 1 0 1 ...

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Page 75: ...irty five input output port pins Figure 4 1 shows the port configuration Every port can be manipulated in 1 bit or 8 bit units controlled in various ways Moreover the port pins can also serve as I O pins of the internal hardware Figure 4 1 Port Types P00 Port 0 P10 Port 1 P14 P20 Port 2 P27 P30 Port 4 Port 5 Port 6 Port 9 P40 P44 P50 P54 P60 P61 Port 8 P81 P87 P90 P97 Port 3 P37 P07 ...

Page 76: ...t units SI3 P53 RxD P54 TxD P60 Input Output PCL TPO P61 SGO P81 to P87 Input Output S19 to S13 P90 to P97 Input Output Port 9 S12 to S5 8 bit input output port Input output mode can be specified in 1 bit units Can be set in input output port or segment output mode in 2 bit units with the LCD display control register LCDC Port 0 8 bit input output port Input output mode can be specified in 1 bit u...

Page 77: ... be used in 1 bit units with a pull up resistor option register 0 PU0 Alternate functions include external interrupt request input serial interface data input output and clock input output RESET input sets port 0 to input mode Figure 4 2 shows a block diagram of port 0 Cautions 1 Because port 0 also serves for external interrupt request input when the port function output mode is specified and the...

Page 78: ...P00 to P07 PM00 to PM07 Selector VDD0 Alternate functions Internal bus PU Pull up resistor option register PM Port mode register RD Port 0 read signal WR Port 0 write signal 4 2 2 Port 1 Port 1 is a 5 bit input only port Alternate functions include an A D converter analog input Figure 4 3 shows a block diagram of port 1 Figure 4 3 P10 to P14 Block Diagram RD P10 ANI0 to P14 ANI4 Internal bus RD Po...

Page 79: ...include meter control PWM output RESET input sets port 2 to high impedance state Figure 4 4 shows a block diagram of port 2 Figure 4 4 P20 to P27 Block Diagram P20 SM11 to P23 SM14 P24 SM21 to P27 SM24 WRPORT WRPM Output latch P20 to P27 Selector Decoder PM20 to PM27 2 Alternate functions Internal bus RD DIRn1 DIRn0 MODn ENn PM Port mode register RD Port 2 read signal WR Port 2 write signal Cautio...

Page 80: ...include meter control PWM output RESET input sets port 3 to high impedance state Figure 4 5 shows a block diagram of port 3 Figure 4 5 P30 to P37 Block Diagram P30 SM31 to P33 SM34 P34 SM41 to P37 SM44 WRPORT WRPM Output latch P30 to P37 PM30 to PM37 Alternate functions Internal bus RD Selector Decoder 2 DIRn1 DIRn0 MODn ENn PM Port mode register RD Port 3 read signal WR Port 3 write signal Cautio...

Page 81: ...ts with the port mode register 4 PM4 Alternate functions also include timer input output RESET input sets port 4 to input mode Figure 4 6 shows a block diagram of port 4 Figure 4 6 P40 to P44 Block Diagram RD P40 TI00 to P42 TI02 P43 TIO2 P44 TIO3 WRPORT WRPM Output latch P40 to P44 PM40 to PM44 Alternate functions Selector Internal bus PM Port mode register RD Port 4 read signal WR Port 4 write s...

Page 82: ... to input mode Figure 4 7 shows a block diagram of port 5 Caution When port 0 is used as the serial interface pins an I O and output latches must be set according to the functions to be used For an explanation of how to set these latches refer to the description of the format of the serial operation mode register Figure 4 7 P50 to P54 Block Diagram RD P50 SCK3 P51 SO3 P52 SI3 P53 RxD P54 TxD WRPOR...

Page 83: ...t units with the port mode register 6 PM6 Alternate functions include clock output and sound generator output RESET input sets port 6 to input mode Figure 4 8 shows a block diagram of port 6 Figure 4 8 P60 and P61 Block Diagram PM Port mode register RD Port 6 read signal WR Port 6 write signal RD P60 PCL TPO P61 SGO WRPORT WRPM Output latch P60 P61 PM60 PM61 Alternate functions Selector Internal b...

Page 84: ...lso include segment signal output of the LCD controller driver Segment output and input output port can be switched by setting the LCD display control register LCDC RESET input sets port 8 to input mode Figure 4 9 shows block diagram of port 8 Figure 4 9 P81 to P87 Block Diagram P81 S19 to P87 S13 WRPORT WRPM Output latch P81 to P87 PM81 to PM87 Segment output function RD Selector Internal bus PM ...

Page 85: ...also include segment signal output of the LCD controller driver Segment output and input output port can be switched by setting the LCD display control register LCDC RESET input sets port 9 to input mode Figure 4 10 shows a block diagram of port 9 Figure 4 10 P90 to P97 Block Diagram P90 S12 to P97 S5 WRPORT WRPM Output latch P90 to P97 PM90 to PM97 Segment output latch RD Selector Internal bus PM...

Page 86: ...hen a port pin is used as an alternate function pin set the port mode register and output latch corresponding to the port in accordance with the function to be used Cautions 1 Pins P10 to P17 are input only pins and pins P20 to P27 and P30 to P37 are output only pins 2 Port 0 has an alternate function as external interrupt request input when the port function output mode is specified and the outpu...

Page 87: ... Symbol 7 6 5 4 3 2 1 0 PM8 PM87 PM86 PM85 PM84 PM83 PM82 PM81 1 Address FF29H After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM9 PM97 PM96 PM95 PM94 PM93 PM92 PM91 PM90 PMmn Pmn Pin Input Output Mode Selection m 0 4 to 6 8 9 n 0 to 7 0 Output Mode Output buffer on 1 Input Mode Output buffer off Figure 4 12 Port Mode Register PM2 PM3 Format Address FF22H After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM2 ...

Page 88: ...on RESET input clears this register to 00H Caution When the on chip pull up resistor is used the pull up resistor is not cut off even when the port is set to the output mode To use the port in the output mode clear the corresponding pull up resistor option register to 0 Figure 4 13 Pull Up Resistor Option Register PU0 Format Address FF30H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 PU0 PU07 PU06 PU...

Page 89: ...ns the output latch contents for pins specified as input are undefined even for bits other than the manipulated bit 4 4 2 Reading from input output port 1 Output mode The output latch contents are read by a transfer instruction The output latch contents do not change 2 Input mode The pin status is read by a transfer instruction The output latch contents do not change 4 4 3 Operations on input outp...

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Page 91: ...Clock Generator Block Diagram X1 X2 Main system clock oscillator HALFOSC fX Prescaler fX 2 fX 22 fX 23 fX 24 Prescaler Clock to peripheral hardware CPU clock fCPU Standby controller Selector STOP PCC2 PCC1 3 PCC0 Processor clock control register PCC Oscillator mode register OSCM Internal bus 5 2 Clock Generator Configuration The clock generator consists of the following hardware Table 5 1 Clock Ge...

Page 92: ...0 0 0 0 0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 CPU Clock fCPU Selection 0 0 0 fX 0 0 1 fX 2 0 1 0 fX 22 0 1 1 fX 23 1 0 0 fX 24 Other than above Setting prohibited Caution Bits 3 to 7 must be set to 0 Remark fX Main system clock oscillation frequency The fastest instructions of the µPD780852 Subseries are executed in two CPU clocks Therefore the relation between the CPU clock fCPU and the minimum instruc...

Page 93: ...cillator Mode Register OSCM Format Address FFA0H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 OSCM HALFOSC 0 0 0 0 0 0 0 HALFOSC Oscillator Mode Selection 0 Normal operation mode 1 Reduced current consumption mode only when operated at fX 4 to 4 19 MHz Cautions 1 This function is available only when the device is operated at fX 4 to 4 19 MHz In other cases be sure not to set 1 to HALFOSC 2 When usin...

Page 94: ... External clock X2 X1 IC µ Cautions 1 Do not execute the STOP instruction while an external clock is input This is because if the STOP instruction is executed the main system clock operation is stopped and the X2 pin is connected to VDD via a pull up resistor 2 When using a main system clock oscillator carry out wiring in the broken line area in Figure 5 4 as follows to avoid influence of wiring c...

Page 95: ...s of Resonator Connection 1 2 a Too long wiring b Crossed signal line X1 IC X2 X2 IC X1 PORTn n 0 to 6 8 and 9 c Wiring near high alternating current d Current flowing through ground line of oscillator potential at points A B and C fluctuates IC X2 X1 IC X2 X1 A B C Pmn VDD High current High current ...

Page 96: ...ser s Manual U14581EJ3V0UM00 Figure 5 5 Incorrect Examples of Resonator Connection 2 2 e Signals are fetched IC X2 X1 5 4 2 Divider circuit The divider circuit divides the output of the main system clock oscillator fX to generate various clocks ...

Page 97: ... b Five types of CPU clocks 0 24 µs 0 48 µs 0 95 µs 1 91 µs and 3 81 µs at 8 38 MHz operation can be selected by the PCC setting c Two standby modes STOP and HALT can be used d The clock to the peripheral hardware is supplied by dividing the main system clock The other peripheral hardware is stopped when the main system clock is stopped except however the external clock input operation e The µPD78...

Page 98: ...e 5 3 Maximum Time Required for Switching CPU Clock Set Value after Switching PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 0 16 instructions 16 instructions 16 instructions 16 instructions 0 0 1 8 instructions 8 instructions 8 instructions 8 instructions 0 1 0 4 instructions 4 instructions 4 instructions 4 instructions ...

Page 99: ...cation The effect of resetting is released when the RESET pin is later made high and the main system clock starts oscillating At this time the time during which oscillation stabilizes 217 fX is automatically secured After that the CPU starts instruction execution at the slowest speed of the main system clock 3 81 µs at 8 38 MHz operation 2 After a lapse of time long enough for the VDD voltage to r...

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Page 101: ...and 3 TM3 TM2 and TM3 can be used to serve as an interval timer and an external event counter and to output square waves with any selected frequency and PWM see CHAPTER 8 8 BIT TIMER EVENT COUNTERS 2 TM2 AND 3 TM3 4 Watch timer This timer can set a flag every 0 5 sec and simultaneously generates interrupt request at the preset time intervals see CHAPTER 9 WATCH TIMER 5 Watchdog timer This timer ca...

Page 102: ... Interval timer 2 channels 1 channel 2 channels 1 channel Note 1 1 channel Note 2 mode External event counter Function Timer output PWM output Pulse width measurement Square wave output Divided output Interrupt request Notes 1 Watch timer can perform both watch timer and interval timer functions at the same time 2 Watchdog timer can perform either the watchdog timer function or the interval timer ...

Page 103: ...ES10 ES21 ES20 16 bit capture register CR01 16 bit capture register CR00 INTOVF INTTM02 INTTM01 INTTM00 ES21 ES20 ES11 fX 8 fX 16 fX 32 fX 64 ES10 ES01 CRC01 TMC02 TPOE CRC00 ES00 PRM01 PRM00 Prescaler mode register PRM0 Capture pulse control register CRC0 16 bit timer mode control register TMC0 Selector TI02 P42 TI01 P41 TI00 P40 TPO PCL P60 Prescaler 1 1 2 1 4 1 8 Noise rejection circuit Noise r...

Page 104: ... TMC02 2 Capture register 00 CR00 The valid edge of the TI00 pin can be selected as the capture trigger Setting of the TI00 valid edge is performed with the prescaler mode register PRM0 When the valid edge of the TI00 is detected an interrupt request INTTM00 is generated CR00 is set with a 16 bit memory manipulation instruction RESET input makes CR00 to undefined 3 Capture register 01 CR01 The val...

Page 105: ...ion mode and controls the prescaler output signals TMC0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears TMC0 to 00H Figure 6 2 16 Bit Timer Mode Control Register TMC0 Format Address FF72H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 TMC0 0 0 0 0 0 TMC02 0 TPOE TMC02 TM0 Operation Mode Selection 0 Operation stop TM0 cleared to 0 1 Operation enabled TPOE Prescaler Outpu...

Page 106: ... or 8 bit memory manipulation instruction RESET input clears CRC0 to 00H Figure 6 3 Capture Pulse Control Register CRC0 Format Address FF71H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 CRC0 0 0 0 0 0 0 CRC01 CRC00 CRC01 CRC00 Capture Pulse Selection 0 0 Does not divide capture pulse 0 1 Divides capture pulse by 2 1 0 Divides capture pulse by 4 1 1 Divides capture pulse by 8 Cautions 1 Timer operati...

Page 107: ... falling and rising edges PRM01 PRM00 Count Clock Selection 0 0 fX 23 0 1 fX 24 1 0 fX 25 1 1 fX 26 Caution Timer operation must be stopped before setting PRM0 Remarks 1 fX Main system clock oscillation frequency 2 n 0 to 2 4 Port mode register 4 PM4 This register sets port 4 to the input or output mode in 1 bit units To use the P40 TI00 to P42 TI02 pins as timer input pins set PM40 to PM42 to 1 P...

Page 108: ...ns can be selected rising falling or both edges by means of bits 2 and 3 ES00 and ES01 of prescaler mode register PRM0 For TI00 pin valid edge detection sampling is performed at the count clock selected by PRM0 and a capture operation is only performed when a valid level is detected twice thus eliminating noise with a short pulse width Figure 6 6 Configuration Diagram for Pulse Width Measurement b...

Page 109: ...edge specified by bits 6 and 7 ES20 and ES21 of PRM0 is input to the TI02 P42 pin the value of TM0 is taken into 16 bit capture register 02 CR02 and external interrupt request signal INTTM02 is set Any of three edge specifications can be selected rising falling or both edges as the valid edges for the TI00 P40 to TI02 P42 pins by means of bits 2 and 3 ES00 and ES01 bits 4 and 5 ES10 and ES11 and b...

Page 110: ...Operation Timing by Free Running Counter with Both Edges Specified Count clock TM0 count value TI0m pin input Value loaded to CR0m INTTM0m TI0n pin input Value loaded to CR0n INTTM0n INTOVF D1 D0 t 10000H D0 D2 t 10000H D1 D2 1 t D3 D2 t t 0000H 0001H D0 D1 FFFFH 0000H D2 D3 D3 D1 D0 D1 D2 Remark m 0 to 2 n 1 2 ...

Page 111: ...ing 16 bit capture register 0n CR0n read CR0n performs capture operation but the capture value is not guaranteed However the interrupt request flag INTTM0n is set upon detection of the valid edge Figure 6 11 Capture Register Data Retention Timing Count pulse TM0 count value Edge input Interrupt request flag Capture read signal CR0n interrupt value N 1 N 1 M 3 M 2 N N 2 N 3 M 1 M M 1 M 2 M 3 X N N ...

Page 112: ...imer operation has been started TMC02 of TMC0 has been set to 1 with a high level applied to input pins TI00 to TI02 of 16 bit timer 0 and with the rising edge with ESn1 and ESn0 of PRM0 set to 0 1 or both the rising and falling edges with ESn1 and ESn0 of PRM0 set to 1 1 selected However INTTM0n does not occur if a low level is applied to TI00 to TI02 Remark n 0 to 2 ...

Page 113: ... 8 bit interval timer Figure 7 1 shows timer 1 TM1 block diagram Figure 7 1 8 Bit Timer 1 TM1 Block Diagram Internal bus Internal bus 8 bit compare register 1 CR1 8 bit counter TM1 Clear Coincidence INTTM1 3 Timer mode control register TMC1 Timer clock select register 1 TCL1 TCE1 TCL12 TCL11 TCL10 fX 23 fX 24 fX 25 fX 27 fX 29 fX 211 Selector ...

Page 114: ...it read only register which counts the count pulses The counter is incremented in synchronization with the rising edge of the count clock When count value is read during operation count clock input is temporary stopped and then the count value is read In the following situations the count value is set to 00H 1 RESET input 2 Clear TCE1 3 Match between TM1 and CR1 2 8 bit compare register 1 CR1 The ...

Page 115: ...tion RESET input clears TCL1 to 00H Figure 7 2 Timer Clock Select Register 1 TCL1 Format Address FF73H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 TCL1 0 0 0 0 0 TCL12 TCL11 TCL10 TCL12 TCL11 TCL10 Count Clock Selection 0 1 0 fX 23 1 04 MHz 0 1 1 fX 24 523 kHz 1 0 0 fX 25 261 kHz 1 0 1 fX 27 65 4 kHz 1 1 0 fX 29 16 3 kHz 1 1 1 fX 211 4 09 kHz Other than above Setting prohibited Cautions 1 When rewr...

Page 116: ...et with a 1 bit or 8 bit memory manipulation instruction RESET input clears TMC1 to 00H Figure 7 3 8 Bit Timer Mode Control Register 1 TMC1 Format Address FF76H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 TMC1 TCE1 0 0 0 0 1 0 0 TCE1 TM1 Count Operation Control 0 After clearing counter to 0 count operation disabled 1 Count operation start Caution Bits 0 1 and 3 to 6 must be set to 0 and bit 2 must ...

Page 117: ... the TM1 can be selected with bits 0 to 2 TCL10 to TCL12 of the timer clock select register 1 TCL1 Setting 1 Set the registers TCL1 Select count clock CR1 Compare value 2 After TCE1 1 is set count operation starts 3 If the values of TM1 and CR1 match the INTTM1 is generated and TM1 is cleared to 00H 4 INTTM1 generates repeatedly at the same interval Set TCE1 to 0 to stop count operation Figure 7 4...

Page 118: ...Interval Timer Operation Timings 2 3 b When CR1 00H t Count clock TM1 CR1 TCE1 INTTM1 TM1 interval time Interval time 00H 00H 00H 00H 00H c When CR1 FFH t Count clock TM1 CR1 TCE1 INTTM1 TM1 interval time 01 FE FF 00 FE FF 00 FF FF FF Interval time Interrupt received Interrupt received ...

Page 119: ...peration Timings 3 3 d Operated by CR1 transition M N Count clock TM1 CR1 TCE1 INTTM1 TM1 interval time 00H N N M N FFH 00H M 00H M CR1 transition TM1 overflows since M N e Operated by CR1 transition M N Count clock TM1 CR1 TCE1 INTTM1 TM1 interval time N 1 N N 00H 01H N M 1 M 00H 01H M CR1 transition ...

Page 120: ...ion If the values after the 8 bit compare register 1 CR1 is changed are smaller than the value of 8 bit timer register 1 TM1 TM1 continues counting overflows and then restarts counting from 0 Thus if the value M after CR1 change is smaller than value N before the change it is necessary to restart the timer after changing CR1 Figure 7 6 Timing after Compare Register Change during Timer Count Operat...

Page 121: ...ck diagram and Figure 8 2 shows 8 bit timer event counter 3 TM3 block diagram Figure 8 1 8 Bit Timer Event Counter 2 TM2 Block Diagram Internal bus 8 bit compare register 2 CR2 8 bit counter 2 TM2 TIO2 P43 fX 211 fX 25 Selector Selector Coincidence Mask circuit OVF Clear 3 Selector TCL22 TCL21 TCL20 Timer clock select register 2 TCL2 Internal bus TCE2 TMC26 LVS2 LVR2 TMC21 TOE2 Invert level Timer ...

Page 122: ...er 3 CR3 8 bit counter 3 TM3 TIO3 P44 fX 212 fX 24 fX 26 Selector Coincidence Mask circuit OVF Clear 3 Selector TCL32 TCL31 TCL30 Timer clock select register 3 TCL3 Internal bus TCE3 TMC36 LVS3 LVR3 TMC31 TOE3 Invert level Timer mode control register 3 TMC3 S R Q R INV Selector INTTM3 S TIO3 P44 P44 output latch PM44 Note fX 27 fX 28 fX 210 Selector Note Bit 4 of port mode register 4 PM4 ...

Page 123: ...ising edge of the count clock When count value is read during operation count clock input is temporary stopped and then the count value is read In the following situations the count value is set to 00H 1 RESET input 2 Clear TCE2 and TCE3 3 Match between TM2 and TM3 and CR2 and CR3 in clear and start mode with match between TM2 and TM3 and CR2 and CR3 2 8 bit compare registers 2 3 CR2 CR3 The value...

Page 124: ... TM3 TCL2 and TCL3 are set with an 8 bit memory manipulation instruction RESET input clears these registers to 00H Figure 8 3 Timer Clock Select Register 2 TCL2 Format Address FF74H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 TCL2 0 0 0 0 0 TCL22 TCL21 TCL20 TCL22 TCL21 TCL20 Count Clock Selection 0 0 0 TIO2 falling edge 0 0 1 TIO2 rising edge 0 1 0 fX 23 1 04 MHz 0 1 1 fX 25 261 kHz 1 0 0 fX 27 65...

Page 125: ... other data stop the timer operation beforehand 2 Bits 3 to 7 must be set to 0 Remarks 1 fX Main system clock oscillation frequency 2 Figures in parentheses apply to operation with fX 8 38 MHz 2 8 bit timer mode control registers 2 3 TMC2 TMC3 TMC2 and TMC3 are registers which sets up the following five types 1 8 bit counters 2 and 3 TM2 and TM3 count operation control 2 8 bit counters 2 and 3 TM2...

Page 126: ...and start mode by matching between TMn and CRn 1 PWM Free running mode LVSn LVRn Timer Output F F Status Setting 0 0 No change 0 1 Timer output F F reset to 0 1 0 Timer output F F set to 1 1 1 Setting prohibited TMCn1 In Other Modes TMCn6 0 In PWM Mode TMCn6 1 Timer F F Control Active Level Selection 0 Inversion operation disabled Active high 1 Inversion operation enabled Active low TOEn Timer Out...

Page 127: ...3 pins as timer output pins clear the output latches of PM43 and PM44 and P43 and P44 to 0 PM4 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM4 to FFH Figure 8 6 Port Mode Register 4 PM4 Format Address FF24H After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM4 1 1 1 PM44 PM43 PM42 PM41 PM40 PM4n P4n Pin I O Mode Selection 0 Output mode output buffer on 1 Input mode outpu...

Page 128: ... timer register n TMn can be selected with the timer clock select register n TCLn Setting 1 Set the registers TCLn Select count clock CRn Compare value TMCn Select clear and start mode by match of TMn and CRn TMCn 0000 0B don t care 2 After TCEn 1 is set count operation starts 3 If the values of TMn and CRn match the INTTMn is generated and TMn is cleared to 00H 4 INTTMn generates repeatedly at th...

Page 129: ...3V0UM00 Figure 8 7 Interval Timer Operation Timings 2 3 b When CRn 00H t Count clock TMn CRn TCEn INTTMn TIOn Interval time 00H 00H 00H 00H 00H c When CRn FFH t Count clock TMn CRn TCEn INTTMn TIOn 01 FE FF 00 FE FF 00 FF FF FF Interval time Interrupt received Interrupt received Remark n 2 3 ...

Page 130: ...1H N M 1 M 00H 01H M CRn transition Remark n 2 3 8 4 2 External event counter operation The external event counter counts the number of external clock pulses to be input to the TIOn TMn is incremented each time the valid edge specified with the timer clock select register n TCLn is input Either the rising or falling edge can be selected When the TMn counted values match the values of 8 bit compare...

Page 131: ...reset to CRn by setting bit 0 TOEn of 8 bit timer mode control register n TMCn to 1 This enables a square wave with any selected frequency to be output duty 50 Setting 1 Set each register Set port latch and port mode register to 0 TCLn Select count clock CRn Compare value TMCn Clear and start mode by match of TMn and CRn LVSn LVRn Timer Output F F Status Setting 1 0 High level output 0 1 Low level...

Page 132: ...sic operation Setting 1 Set port latch P43 P44 and port mode register 4 PM43 PM44 to 0 2 Set active level width with 8 bit compare register CRn 3 Select count clock with timer clock select register n TCLn 4 Set active level with bit 1 TMCn1 of TMCn 5 Count operation starts when bit 7 TCEn of TMCn is set to 1 Set TCEn to 0 to stop count operation PWM output operation 1 PWM output output from TIOn o...

Page 133: ...n INTTMn TIOn 00H 01H FFH 00H 01H 02H N N 1 FFH 00H 01H 02H M 00H N Active level Active level Inactive level ii CRn 0 Count clock TMn CRn TCEn INTTMn TIOn Inactive level Inactive level 01H 00H FFH 00H 01H 02H N N 1 FFH 00H 01H 02H M 00H 00H N 2 iii CRn FFH TMn CRn TCEn INTTMn TIOn 01H 00H FFH 00H 01H 02H N N 1 FFH 00H 01H 02H M 00H FFH N 2 Inactive level Active level Inactive level Active level In...

Page 134: ...tion N M N N 1 N 2 FFH 00H 01H M M 1 M 2 FFH 00H 01H 02H M M 1 M 2 N 02H M H ii Change of CRn value to N to M after overflow of TMn Count clock TMn CRn TCEn INTTMn TIOn N N 1 N 2 FFH 00H 01H N N 1 N 2 FFH 00H 01H 02H N 02H N H 03H M M M 1 M 2 CRn transition N M iii Change of CRn value between two clocks 00H and 01H after overflow of TMn Count clock TMn CRn TCEn INTTMn TIOn N N 1 N 2 FFH 00H 01H N ...

Page 135: ...ister change during timer count operation If the values after the 8 bit compare registers 2 and 3 CR2 and CR3 are changed are smaller than the value of 8 bit counters 2 and 3 TM2 and TM3 TM2 and TM3 continue counting overflow and then restart counting from 0 Thus if the value M after CR2 and CR3 change is smaller than value N before the change it is necessary to restart the timer after changing CR...

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Page 137: ... The watch timer and the interval timer can be used simultaneously Figure 9 1 shows watch timer block diagram Figure 9 1 Watch Timer Block Diagram 9 bit prescaler 5 bit counter Selector Selector Selector WTM7 fX 27 fX 211 WTM6 WTM5 WTM4 Internal bus WTM3 WTM1 WTM0 Watch timer mode control register WTM Clear Clear INTWT INTWTI fW 24 fW 25 fW 26 fW 27 fW 28 fW 29 fW ...

Page 138: ... preset time interval Table 9 1 Interval Timer Interval Time Interval Time When Operated at fX 8 38 MHz 212 fX 489 µs 213 fX 978 µs 214 fX 1 96 ms 215 fX 3 91 ms 216 fX 7 82 ms 217 fX 15 65 ms Remark fX Main system clock oscillation frequency 9 2 Watch Timer Configuration The watch timer consists of the following hardware Table 9 2 Watch Timer Configuration Item Configuration Counter 5 bits 1 Pres...

Page 139: ...M7 WTM6 WTM5 WTM4 WTM3 0 WTM1 WTM0 WTM7 Watch Timer Count Clock Selection 0 fX 27 65 4 kHz 1 fX 211 4 09 kHz WTM6 WTM5 WTM4 Prescaler Interval Time Selection 0 0 0 24 fW 3 91 ms 0 0 1 25 fW 7 82 ms 0 1 0 26 fW 15 6 ms 0 1 1 27 fW 31 2 ms 1 0 0 28 fW 62 5 ms 1 0 1 29 fW 125 ms Other than above Setting prohibited WTM3 Watch Flag Set Time Selection 0 Normal operating mode flag set at fW 214 1 Fast fe...

Page 140: ...WTM1 to 0 However since the 9 bit prescaler is not cleared the first overflow of the watch timer INTWT after zero second start may include an error of up to 29 1 fW 9 4 2 Interval timer operation The watch timer operates as interval timer which generates interrupt request repeatedly at an interval of the preset count value The interval time can be selected with bits 4 to 6 WTM4 to WTM6 of the watc...

Page 141: ...Timer Operation Timing 0H Start Overflow Overflow 5 bit counter Count clock fW or fW 29 Watch timer interrupt INTWT Interval timer interrupt INTWTI Interrupt time of watch timer 0 25 s Interval timer T T Interrupt time of watch timer 0 25 s Remark fW Watch timer clock frequency fW 4 09 kHz fX 8 38 MHz ...

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Page 143: ... the watchdog timer mode register WDTM Figure 10 1 shows the watchdog timer block diagram Figure 10 1 Watchdog Timer Block Diagram Prescaler INTWDT Maskable interrupt request INTWDT Non maskable interrupt request RESET WDTIF WDTMK RUN Selector Controller fX 28 fX 212 fX 213 fX 214 fX 215 fX 216 fX 217 fX 218 fX 220 3 Internal bus Internal bus WDCS2WDCS1WDCS0 RUN WDTM4WDTM3 Watchdog timer mode regi...

Page 144: ...16 1 fX 7 82 ms 217 1 fX 15 6 ms 218 1 fX 31 3 ms 220 1 fX 125 ms Remarks 1 fX Main system clock oscillation frequency 2 Figures in parentheses apply to operation with fX 8 38 MHz 2 Interval timer mode Interrupt requests are generated at preset time intervals Table 10 2 Interval Time Interval Time 212 1 fX 489 µs 213 1 fX 978 µs 214 1 fX 1 96 ms 215 1 fX 3 91 ms 216 1 fX 7 82 ms 217 1 fX 15 6 ms 2...

Page 145: ... sets overflow time of the watchdog timer and the interval timer WDCS is set with an 8 bit memory manipulation instruction RESET input clears WDCS to 00H Figure 10 2 Watchdog Timer Clock Select Register WDCS Format Address FF42H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 WDCS 0 0 0 0 0 WDCS2 WDCS1 WDCS0 WDCS2 WDCS1 WDCS0 Overflow Time of Watchdog Timer Interval Timer 0 0 0 fX 212 489 µs 0 0 1 fX 2...

Page 146: ...askable interrupt request occurs upon generation of an overflow 1 0 Watchdog timer mode 1 Non maskable interrupt request occurs upon generation of an overflow 1 1 Watchdog timer mode 2 Reset operation is activated upon generation of an overflow Notes 1 Once set to 1 RUN cannot be cleared to 0 by software Thus once counting starts it can only be stopped by RESET input 2 Once set to 1 WDTM3 and WDTM...

Page 147: ...the runaway detection time is past system reset or a non maskable interrupt request is generated according to the WDTM bit 3 WDTM3 value The watchdog timer is cleared if RUN is set to 1 The watchdog timer continues operating in the HALT mode but it stops in the STOP mode Thus set RUN to 1 before the STOP mode is set clear the watchdog timer and then execute the STOP instruction Caution The actual ...

Page 148: ...terval timer continues operating in the HALT mode but it stops in STOP mode Thus set bit 7 RUN of WDTM to 1 before the STOP mode is set clear the interval timer and then execute the STOP instruction Cautions 1 Once bit 4 WDTM4 of WDTM is set to 1 with the watchdog timer mode selected the interval timer mode is not set unless RESET input is applied 2 The interval time just after setting with WDTM m...

Page 149: ...tput controller block diagram Figure 11 1 Clock Output Controller Block Diagram fX fX 2 fX 22 fX 23 fX 24 fX 25 fX 26 fX 27 Selector Clock controller CLOE CCS2 CCS1 CCS0 PM60 PCL TPO P60 Clock output selection register CKS Port mode register 6 PM6 P60 output latch 3 Internal bus TPO Note Note TPO Prescaler output signal of 16 bit timer 0 TM0 11 2 Clock Output Controller Configuration The clock out...

Page 150: ...y using a 1 bit memory manipulation instruction Figure 11 2 Clock Output Selection Register CKS Format Address FF40H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 CKS 0 0 0 CLOE 0 CCS2 CCS1 CCS0 CLOE PCL Output Enable Disable Specification 0 Operation disabled 1 Operation enabled CCS2 CCS1 CCS0 PCL Output Clock Selection 0 0 0 fX 8 38 MHz 0 0 1 fX 2 4 19 MHz 0 1 0 fX 22 2 09 MHz 0 1 1 fX 23 1 04 MHz ...

Page 151: ...pin for clock output set PM60 and the output latch of P60 to 0 PM6 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM6 to FFH Figure 11 3 Port Mode Register 6 PM6 Format Address FF26H After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM6 1 1 1 1 1 1 PM61 PM60 PM6n P6n Pin Input Output Mode Selection n 0 1 0 Output mode output buffer on 1 Input mode output buffer off ...

Page 152: ...bled status 3 Set the P60 output latch to 0 4 Set bit 0 PM60 of port mode register 6 to 0 set to output mode 5 Set bit 4 CLOE of CKS to 1 and enable clock output Caution The clock output cannot be used if the output latch of P60 is set to 1 Remark The clock output controller is designed not to output pulses with a small width during output enable disable switching of the clock output As shown in F...

Page 153: ...solution One channel of analog input is selected from ANI0 to ANI4 and A D conversion is repeatedly executed with a resolution of 8 bits Each time the conversion has been completed interrupt request INTAD is generated 2 Power fail detection function This function is to detect a voltage drop in the battery of an automobile The result of A D conversion value of the ADCR1 register and the value of PF...

Page 154: ...lt register ADCR1 Tap selector AVREF AVSS INTAD A D converter mode register ADM1 Analog input channel specification register ADS1 Internal bus ADS12 ADS11 ADS10 ADCS1 FR12 FR11 FR10 Series resistor string Figure 12 2 Power Fail Detection Function Block Diagram ANI0 P10 ANI1 P11 ANI2 P12 ANI3 P13 ANI4 P14 Multiplexer Selector A D converter Internal bus Power fail compare mode register PFM Comparato...

Page 155: ...it memory manipulation instruction RESET input clears ADCR1 to 00H Caution When write operation is executed to A D converter mode register ADM1 and analog input channel specification register ADS1 the contents of ADCR1 are undefined Read the conversion result before write operation is executed to ADM1 ADS1 If a timing other than the above is used the correct conversion result may not be read 3 Sam...

Page 156: ... A D converter is used It converts signals input to ANI0 to ANI4 into digital signals according to the voltage applied between AVREF and AVSS The current flowing in the series resistor string can be reduced by setting the voltage to be input to the AVREF pin to AVSS level in the standby mode 8 AVSS pin This is the GND potential pin of the A D converter Always keep it at the same potential as the V...

Page 157: ...Converter Mode Register ADM1 Format Address FF80H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 ADM1 ADCS1 0 FR12 FR11 FR10 0 0 0 ADCS1 A D Conversion Operation Control 0 Conversion operation stop 1 Conversion operation enabled FR12 FR11 FR10 Conversion Time Selection Note 1 0 0 0 144 fX 17 2 µs 0 0 1 120 fX 14 3 µs 0 1 0 96 fX Note 2 1 0 0 288 fX 34 4 µs 1 0 1 240 fX 28 6 µs 1 1 0 192 fX 22 9 µs Oth...

Page 158: ...h an 8 bit memory manipulation instruction RESET input clears ADS1 to 00H Figure 12 4 Analog Input Channel Specification Register ADS1 Format Address FF81H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 ADS1 0 0 0 0 0 ADS12 ADS11 ADS10 ADS12 ADS11 ADS10 Analog Input Channel Specification 0 0 0 ANI0 0 0 1 ANI1 0 1 0 ANI2 0 1 1 ANI3 1 0 0 ANI4 Other than above Setting prohibited Caution Bits 3 to 7 must...

Page 159: ... Compare Mode Selection 0 ADCR1 PFT Generates interrupt request signal INTAD ADCR1 PFT Does not generate interrupt request signal INTAD 1 ADCR1 PFT Does not generate interrupt request signal INTAD ADCR1 PFT Generates interrupt request signal INTAD Caution Bits 0 to 5 must be set to 0 4 Power fail compare threshold value register PFT The power fail compare threshold value register PFT sets a thresh...

Page 160: ... remains set If the analog input is smaller than 1 2 AVREF the MSB is reset 6 Next bit 6 of SAR is automatically set and the operation proceeds to the next comparison The series resistor string voltage tap is selected according to the preset value of bit 7 as described below Bit 7 1 3 4 AVREF Bit 7 0 1 4 AVREF The voltage tap and analog input voltage are compared and bit 6 of SAR is manipulated as...

Page 161: ...rsion result A D conversion operations are performed continuously until bit 7 ADCS1 of the A D converter mode register ADM1 is reset to 0 by software If a write operation to the ADM1 and analog input channel specification register ADS1 is performed during an A D conversion operation the conversion operation is initialized and if the ADCS1 bit is set to 1 conversion starts again from the beginning ...

Page 162: ... 0 5 AVREF or ADCR1 0 5 AVREF VIN ADCR1 0 5 AVREF 256 256 where INT Function which returns integer part of value in parentheses VIN Analog input voltage AVREF AVREF pin voltage ADCR1 A D conversion result register ADCR1 value Figure 12 8 shows the relation between the analog input voltage and the A D conversion result Figure 12 8 Relation between Analog Input Voltage and A D Conversion Result 255 ...

Page 163: ...sion operation is immediately started A D conversion operations are repeated until new data is written to ADS1 If ADS1 is rewritten during A D conversion operation the A D conversion operation under execution is stopped and A D conversion of a newly selected analog input channel is started If data with ADCS1 set to 0 is written to ADM1 during A D conversion operation the A D conversion operation s...

Page 164: ...re 12 9 A D Conversion ADM1 rewrite ADCS1 1 ADS1 rewrite ADCS1 0 A D conversion ADCR1 INTAD PFEN 0 INTAD PFEN 1 ANIn ANIn ANIn ANIm ANIm Stop ANIn ANIn ANIm Conversion suspended Conversion results are not stored First conversion Condition satisfied Remarks 1 n 0 1 4 2 m 0 1 4 ...

Page 165: ...by instruction upon the end of conversion ADCR1 read is given priority After the read operation the new conversion result is written to ADCR1 2 Contention between ADCR1 write and A D converter mode register ADM1 write or analog input channel specification register ADS1 write upon the end of conversion ADM1 or ADS1 write is given priority ADCR1 write is not performed nor is the conversion end inter...

Page 166: ...The analog input pins ANI0 to ANI4 also function as input port pins P10 to P14 When A D conversion is performed with any of pins ANI0 to ANI4 selected do not execute a port input instruction while conversion is in progress as this may reduce the conversion resolution Also if digital pulses are applied to a pin adjacent to the pin in the process of A D conversion the expected A D conversion value m...

Page 167: ...ange analog input has not ended When the A D conversion is stopped and then resumed clear ADIF before the A D conversion operation is resumed Figure 12 12 A D Conversion End Interrupt Request Generation Timing ADS1 rewrite start of ANIn conversion A D conversion ADCR1 INTAD ANIn ANIn ANIm ANIm ANIn ANIn ANIm ANIm ADS1 rewrite start of ANIm conversion ADIF is set but ANIm conversion has not ended R...

Page 168: ... the power fail detection function Figure 12 13 D A Converter Mode Register DAM1 Format Address FF89H After Reset 00H W Symbol 7 6 5 4 3 2 1 0 DAM1 0 0 0 0 0 0 0 DACE DACE Reference Voltage Control 0 Disabled 1 Enabled when power fail detection function is used Cautions 1 DAM1 is a special register that must be set when debugging is performed with an in circuit emulator Even if this register is us...

Page 169: ... using a wide range of selectable baud rates For details see 13 4 2 Asynchronous serial interface UART mode Figure 13 1 shows the serial interface UART block diagram Figure 13 1 Serial Interface UART Block Diagram Internal bus Internal bus Receive buffer register RXB Receive shift register RXS Direction controller Direction controller Transmit controller Baud rate generator Transmit shift register...

Page 170: ...igned to TXS and the receive buffer register RXB A read operation reads values from RXB 2 Receive shift register RXS This register converts serial data input via the RxD pin to parallel data When one byte of data is received at this register the receive data is transferred to the receive buffer register RXB RXS cannot be manipulated directly by a program 3 Receive buffer register RXB This register...

Page 171: ...used to control the serial interface UART Asynchronous serial interface mode register ASIM Asynchronous serial interface status register ASIS Baud rate generator control register BRGC 1 Asynchronous serial interface mode register ASIM This is an 8 bit register that controls UART s serial transfer operations ASIM is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears ASIM t...

Page 172: ...de Serial function RxD Serial function TxD transmit and receive PS1 PS0 Parity Bit Specification 0 0 No parity 0 1 Zero parity always added during transmission No parity detection during reception parity errors do not occur 1 0 Odd parity 1 1 Even parity CL Character Length Specification 0 7 bits 1 8 bits SL Stop Bit Length Specification for Transmit Data 0 1 bit 1 2 bits ISRM Receive Completion I...

Page 173: ...or Note 1 Stop bit not detected OVE Overrun Error Flag 0 No overrun error 1 Overrun error Note 2 Next receive operation was completed before data was read from receive buffer register Notes 1 Even if a stop bit length of two bits has been set to bit 2 SL in the asynchronous serial interface mode register ASIM stop bit detection during a receive operation only applies to a stop bit length of 1 bit ...

Page 174: ... 0 0 0 0 fSCK 16 0 0 0 0 1 fSCK 17 1 0 0 1 0 fSCK 18 2 0 0 1 1 fSCK 19 3 0 1 0 0 fSCK 20 4 0 1 0 1 fSCK 21 5 0 1 1 0 fSCK 22 6 0 1 1 1 fSCK 23 7 1 0 0 0 fSCK 24 8 1 0 0 1 fSCK 25 9 1 0 1 0 fSCK 26 10 1 0 1 1 fSCK 27 11 1 1 0 0 fSCK 28 12 1 1 0 1 fSCK 29 13 1 1 1 0 fSCK 30 14 1 1 1 1 Setting prohibited Caution Writing to BRGC during a communication operation may cause abnormal output from the baud ...

Page 175: ...rt function P53 Port function P54 0 1 UART mode Serial function RxD Port function P54 receive only 1 0 UART mode Port function P53 Serial function TxD transmit only 1 1 UART mode Serial function RxD Serial function TxD transmit and receive Cautions 1 Do not switch the operation mode until after the current serial transmit receive operation has stopped 2 Bit 0 must be set to 0 13 4 2 Asynchronous s...

Page 176: ...top Port function P53 Port function P54 0 1 UART mode Serial function RxD Port function P54 receive only 1 0 UART mode Port function P53 Serial function TxD transmit only 1 1 UART mode Serial function RxD Serial function TxD transmit and receive PS1 PS0 Parity Bit Specification 0 0 No parity 0 1 Zero parity always added during transmission No parity detection during reception parity errors do not ...

Page 177: ...o framing error 1 Framing error Note 1 Stop bit not detected OVE Overrun Error Flag 0 No overrun error 1 Overrun error Note 2 Next receive operation was completed before data was read from receive buffer register Notes 1 Even if a stop bit length of two bits has been set to bit 2 SL in the asynchronous serial interface mode register ASIM stop bit detection during a receive operation only applies t...

Page 178: ... for Baud Rate Generator k 0 0 0 0 fSCK 16 0 0 0 0 1 fSCK 17 1 0 0 1 0 fSCK 18 2 0 0 1 1 fSCK 19 3 0 1 0 0 fSCK 20 4 0 1 0 1 fSCK 21 5 0 1 1 0 fSCK 22 6 0 1 1 1 fSCK 23 7 1 0 0 0 fSCK 24 8 1 0 0 1 fSCK 25 9 1 0 1 0 fSCK 26 10 1 0 1 1 fSCK 27 11 1 1 0 0 fSCK 28 12 1 1 0 1 fSCK 29 13 1 1 1 0 fSCK 30 14 1 1 1 1 Setting prohibited Cautions 1 Writing to BRGC during a communication operation may cause a...

Page 179: ...ng formula Baud rate fX Hz 2n 1 k 16 fX Main system clock oscillation frequency n Value set via TPS0 to TPS2 1 n 8 For details see Table 13 2 k Value set via MDL0 to MDL3 0 k 14 Table 13 2 shows the relation between the 5 bit counter s source clock assigned to bits 4 to 6 TPS0 to TPS2 of BRGC and the n value in the above formula Table 13 2 Relation between 5 Bit Counter s Source Clock and n Value ...

Page 180: ...7BH 1 10 1 200 6BH 1 10 2 400 5BH 1 10 4 800 4BH 1 10 9 600 3BH 1 10 19 200 2BH 1 3 31 250 21H 1 10 38 400 1BH 1 10 76 800 0BH 1 10 115 200 01H 1 03 Remark fX Main system clock oscillation frequency Figure 13 5 Error Tolerance When k 0 Including Sampling Errors Basic timing clock cycle T START D0 D7 P STOP High speed clock clock cycle T enabling normal reception START D0 D7 P STOP Low speed clock ...

Page 181: ...op bit s 1 bit or 2 bits The asynchronous serial interface mode register ASIM is used to set the character bit length parity selection and stop bit length within each data frame When 7 bits is selected as the number of character bits only the lower 7 bits bits 0 to 6 are valid so that during a transmission the highest bit bit 7 is ignored and during reception the highest bit bit 7 must be set to 0...

Page 182: ... the receive data that include a parity bit and a parity error occurs when the result is an odd number ii Odd parity During transmission The number of bits in transmit data that includes a parity bit is controlled so that there is an odd number of 1 bits The value of the parity bit is as follows If the transmit data contains an odd number of 1 bits the parity bit value is 0 If the transmit data co...

Page 183: ... 13 7 Figure 13 7 Asynchronous Serial Interface Transmit Completion Interrupt Timing TxD output D0 D1 D2 D6 D7 Parity STOP START INTST i Stop bit length 1 bit TxD output D0 D1 D2 D6 D7 Parity START INTST ii Stop bit length 2 bits STOP Caution Do not rewrite the asynchronous serial interface mode register ASIM during a transmit operation Rewriting to the ASIM register during a transmit operation ma...

Page 184: ...ion of one data frame is completed the receive data in the shift register is transferred to the receive buffer register RXB and a receive completion interrupt INTSR occurs Even if an error has occurred the receive data in which the error occurred is still transferred to RXB INTSR occurs if bit 1 ISRM of ASIM is cleared to 0 on occurrence of an error If the ISRM bit is set to 1 INTSR does not occur...

Page 185: ...13 4 Causes of Receive Errors Receive Error Cause ASIS Value Parity error Parity specified during transmission does not match parity of receive data 04H Framing error Stop bit was not detected 02H Overrun error Reception of the next data was completed before data was read from the 01H receive buffer register Figure 13 9 Receive Error Timing RxD input D0 D1 D2 D6 D7 Parity STOP START INTSR Note INT...

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Page 187: ... first bit in the 8 bit data in serial transfer is fixed as the MSB This data contains a 1 byte receive buffer and can be received successively The serial clock and the data phase polarity can be selected The 3 wire serial I O mode is useful for connection to a peripheral I O device that includes a clocked serial interface a display controller etc Figure 14 1 shows the serial interface SIO2 block ...

Page 188: ... data is held in SIO2 RESET input clears SIO2 to 00H Cautions 1 Do not access read write SIO2 during a transmit receive operation shift operation 2 When a transmit receive operation starts writing to SIO2 do not access read write SIO2 before a transmit completion interrupt INTCSI2 occurs in the transmit receive mode MODE2 1 3 If the external clock mode CLPH 1 is selected in the slave mode SCL20 0 ...

Page 189: ...LPH CLPO MODE2 SCL21 SCL20 CSIE2 SIO2 Operation Enable Disable Specification Shift Register Operation Serial Counter Port 0 Operation disabled Clear Port function 1 Operation enabled Counter operation enabled Serial function port function CLPH SO2 Output Timing Selection 0 Transfer starts at the first active edge of SCK2 1 Transfer starts when SCK2 is written CLPO Serial Clock Active Level Selecti...

Page 190: ...n execute an access that will be the start trigger of each transfer operation mode 4 Changing CSIE2 and other bits at the same time is prohibited After clearing CSIE2 to 0 change the other bits Remark fX Main system clock oscillation frequency The following shows the relationships between the CLPO and CLPH settings and the serial transfer clock data output and input data capture timing Figure 14 3...

Page 191: ...utions 1 When an overflow error occurs receive data in SIO2 will not be transferred to SIRB2 even if the next receive operation for SIO2 is complete 2 When an overflow error occurs be sure to read SRBS2 clear SDOF and read SIRB2 clear SDVA If the receive operation is resumed without reading SIRB2 clearing SDVA after SDOF clear SDOF is set even if the next receive operation ends normally 3 Even if ...

Page 192: ...et FFH R W Symbol 7 6 5 4 3 2 1 0 PM0 PM07 PM06 PM05 PM04 PM03 PM02 PM01 PM00 PM0n P0n Pin Input Output Mode Selection 0 Output mode output buffer on 1 Input mode output buffer off Remark n 0 to 7 Table 14 2 Relation between Operation Modes and Settings of PM03 to PM05 Operation Mode PM0 Settings Note 2 SIO2 Operation Serial Operation Mode Master Slave Note 1 PM03 PM04 PM05 Disabled CSIE2 0 Enable...

Page 193: ...pins can be used as normal I O port pins 1 Register setting The operation stop mode is set with the serial operation mode register 2 CSIM2 CSIM2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears CSIM2 to 00H Address FF98H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 CSIM2 CSIE2 0 0 CLPH CLPO MODE2 SCL21 SCL20 CSIE2 SIO2 Operation Enable Disable Specification Shift Regis...

Page 194: ... SCL21 SCL20 CSIE2 SIO2 Operation Enable Disable Specification Shift Register Operation Serial Counter Port 0 Operation disabled Clear Port function 1 Operation enabled Counter operation enabled Serial function port function CLPH SO2 Output Timing Sleleciton 0 Transfer starts at the first active edge of SCK2 1 Transfer starts when SCK2 is written CLPO Serial Clock Active Level Selection 0 SCK2 is ...

Page 195: ...k fX Main system clock oscillation frequency 2 Communication operations Data is transmitted received in 8 bit units 8 bit data is transmitted received bit by bit in synchronization with the serial clock Two transfer modes are provided for the 3 wire serial I O mode transmit receive mode and receive only mode After setting each operation mode using the serial operation mode register CSIM2 transmit ...

Page 196: ...de the SCK2 pin operates as an external serial clock input pin Serial data is transferred to SIO2 in synchronization with the externally input serial clock After the serial data has been received by SIO2 it is transferred to the serial receive data buffer register SIRB2 At the same time the SDVA flag is set to 1 and a transmit completion interrupt INTCSI2 occurs Caution To prevent the occurrence o...

Page 197: ...H 0 Figure 14 6 shows the operation timing when CLPH 0 Two waves of SCK2 when CLPO 0 and when CLPO 1 are shown in the figure Data is transmitted or received in 8 bit units Each bit of data is transmitted or received in synchronization with the serial clock SIO2 is shifted at the falling edge of SCK2 if CLPH 0 and CLPO 0 If CLPH 0 and CLPO 1 SIO2 is shifted at the rising edge of SCK2 The transmit d...

Page 198: ...al input data AAH ABH 56H ADH 5AH B5H 6AH D5H AAH AAH AAH 55H SCK2 CLPO 0 SIRB2 SI2 SO2 SCK2 CLPO 1 55H Write SIO2 55H Serial output data timing Start trigger operation timing INTCSI2 interrupt request generated at rising edge 6 Hardware detection in error status Serial interface SIO2 has a function for checking whether an overflow error has occurred While serial data being transferred to the seri...

Page 199: ...2 read 4 SRBS2 is read and the status is checked overflow error check 5 Like 1 above DATA2 receive data is transferred to SIRB2 after it is received completely 6 Even though DATA3 receive data reception is complete it is held in SIO2 without being transferred to SIRB2 since the previous receive data DATA2 has not been read from SIRB2 7 SDOF is set to 1 since SDVA has been set to 1 and DATA3 recept...

Page 200: ...te In the HALT mode the CPU cannot access the registers of serial interface SIO2 If it is not necessary to use serial interface SIO2 in the HALT mode the power consumption can be reduced by stopping the operation of the serial interface SIO2 before the HALT instruction is executed b Operation in STOP mode Serial interface SIO2 can operate in the STOP mode if the slave mode in which an external clo...

Page 201: ...eive operations are enabled in 3 wire serial I O mode the processing time for data transfers is reduced The first bit in the 8 bit data in serial transfers is fixed as the MSB 3 wire serial I O mode is useful for connection to a peripheral I O device that includes a clocked serial interface a display controller etc For details see 15 4 2 3 wire serial I O mode Figure 15 1 shows the serial interfac...

Page 202: ... and serial transmit receive shift operations synchronized with the serial clock SIO3 is set with an 8 bit memory manipulation instruction When 1 is set to bit 7 CSIE3 of the serial operation mode register 3 CSIM3 a serial operation can be started by writing data to or reading data from SIO3 When transmitting data written to SIO3 is output via the serial output SO3 When receiving data is read from...

Page 203: ...K3 to the output mode PM50 0 When serial clock input Slave transmit or slave receive Set P50 to the input mode PM50 1 When transmit or transmit receive mode Set P51 SO3 to the output mode PM51 0 When receive mode Set P52 SI3 to the input mode PM52 1 Figure 15 2 Serial Operation Mode Register 3 CSIM3 Format Address FF84H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 CSIM3 CSIE3 0 0 0 0 MODE3 SCL31 SCL...

Page 204: ...e the P50 SCK3 P51 SO3 and P52 SI3 pins can be used as normal I O port pins 1 Register settings Operation stop mode is set with the serial operation mode register 3 CSIM3 CSIM3 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears CSIM3 to 00H Address FF84H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 CSIM3 CSIE3 0 0 0 0 MODE3 SCL31 SCL30 CSIE3 SIO3 Operation Enable Disable...

Page 205: ...lows Besides that set all output latches to 0 When serial clock output Master transmit or master receive Set P50 SCK3 to the output mode PM50 0 When serial clock input Slave transmit or slave receive Set P50 to the input mode PM50 1 When transmit or transmit receive mode Set P51 SO3 to the output mode PM51 0 When receive mode Set P52 SI3 to the input mode PM52 1 Address FF84H After Reset 00H R W S...

Page 206: ...e Timing SI3 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 CSIIF3 SCK3 1 SO3 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 2 3 4 5 6 7 8 Transfer completion Transfer starts in synchronized with the falling edge of SCK3 3 Transfer start A serial transfer starts when the following two conditions have been satisfied and transfer data has been set to or read from serial I O shift register 3 SIO3 SIO3 operation control bit CSIE3 ...

Page 207: ...ny of four frame frequencies can be selected in each display mode 4 Maximum of 20 segment signal outputs S0 to S19 4 common signal outputs COM0 to COM3 Fifteen of the segment signal outputs can be switched to input output ports in units of 2 P81 S19 to P87 S13 P90 S12 to P97 S5 The maximum number of displayable pixels is shown in Table 16 1 Table 16 1 Maximum Number of Display Pixels Bias Method T...

Page 208: ...0 to COM3 Control registers LCD display mode register LCDM LCD display control register LCDC Figure 16 1 LCD Controller Driver Block Diagram Note Segment driver Internal bus FA59H 7 6 5 4 3 2 1 0 FA67H 7 6 5 4 3 2 1 0 FA68H 7 6 5 4 3 2 1 0 FA6CH 7 6 5 4 3 2 1 0 Display data memory 3 2 1 0 Selector 3 2 1 0 Selector 3 2 1 0 Selector 3 2 1 0 Selector Note Note Note Note P97 output buffer S4 S0 S5 P97...

Page 209: ... User s Manual U14581EJ3V0UM00 Figure 16 2 LCD Clock Selector Block Diagram Prescaler fLCD 2 3 fX 2 14 fLCD 2 2 fLCD 2 fLCD Selector LCDM6 LCDM5 LCDM4 3 LCDCL LCD display mode register Internal bus Remarks 1 LCDCL LCD clock 2 fLCD LCD clock frequency ...

Page 210: ...frame frequency LCDM is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears LCDM to 00H Figure 16 3 LCD Display Mode Register LCDM Format Address FFB0H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 LCDM LCDON LCDM6 LCDM5 LCDM4 0 0 0 0 LCDON LCD Display Enable Disable 0 Display off all segment outputs are non select signal outputs 1 Display on LCDM6 LCDM5 LCDM4 LCD Clock Selec...

Page 211: ... LCDC7 LCDC6 LCDC5 LCDC4 P81 S19 to P97 S5 Pin Functions Port Pins Segment Pins 0 0 0 0 P81 to P97 None 0 0 0 1 P81 to P95 S5 S6 0 0 1 0 P81 to P93 S5 to S8 0 0 1 1 P81 to P91 S5 to S10 0 1 0 0 P81 to P87 S5 to S12 0 1 0 1 P81 to P85 S5 to S14 0 1 1 0 P81 to P83 S5 to S16 0 1 1 1 P81 S5 to S18 1 0 0 0 None S5 to S19 Other than above Setting prohibited LIPS LCD Driving Power Supply Selection 0 Does...

Page 212: ...iver settings should be performed as shown below 1 Set the initial value in the display data memory FA59H to FA6CH 2 Set the pins to be used as segment outputs in the LCD display control register LCDC 3 Set the LCD clock in the LCD display mode register LCDM Next set data in the display data memory according to the display contents ...

Page 213: ...e 16 5 shows the relation between the LCD display data memory contents and the segment outputs common outputs Any area not used for display can be used as normal RAM Figure 16 5 Relation between LCD Display Data Memory Contents and Segment Common Outputs S0 FA6CH S1 FA6BH S2 FA6AH S3 FA69H S17 P83 FA5BH S18 P82 FA5AH S19 P81 FA59H COM3 COM2 COM1 COM0 b7 b6 b5 b4 b3 b2 b1 b0 Address Caution The hig...

Page 214: ...ly and if the value of the bit is 1 it is converted to the selection voltage If the value of the bit is 0 it is converted to the non selection voltage and output to a segment pin S0 to S19 S18 to S5 have an alternate function as input output port pins Consequently it is necessary to check what combination of front surface electrodes corresponding to the segment signals and rear surface electrodes ...

Page 215: ...on signal and segment signal voltages and phases Figure 16 6 Common Signal Waveform TF 4 T COMn Divided by 4 VLC0 VSS VLCD VLC1 VLC2 T One LCDCL cycle TF Frame frequency Figure 16 7 Common Signal and Segment Signal Voltages and Phases Selected Not selected Common signal Segment signal VLC0 VSS VLCD VLC0 VSS VLCD T T VLC2 VLC2 VLC1 VLC1 T One LCDCL cycle ...

Page 216: ...e is fixed to 1 3 bias To supply various LCD drive voltages internal VDD or external VLCD supply voltage can be selected Table 16 5 LCD Drive Voltage Bias Method 1 3 Bias Method LCD Drive Voltage VLC0 VLCD VLC1 2 3VLCD VLC2 1 3VLCD Figure 16 8 shows an example of supplying an LCD drive voltage from an internal source according to Table 16 5 By using variable resistors r1 and r2 a non stepwise LCD ...

Page 217: ... Connection of LCD Drive Power Supply a To supply LCD drive voltage from VDD VDD VSS VLCD VDD P ch LIPS 1 R R R VSS VLC2 VLC1 VLC0 VLCD Open VLCD pin b To supply LCD drive voltage from external source VDD VLCD VDD r1 r2 VSS VSS VLCD VDD P ch LIPS 0 R R R VSS VLC2 VLC1 VLC0 VLCD 3R r2 3R r2 3R r1 r1 r2 ...

Page 218: ...ges must be output to pins S8 and S9 as shown in Table 16 6 at the COM0 to COM3 common signal timings Table 16 6 Selection and Non Selection Voltages COM0 to COM3 Segment S8 S9 Common COM0 S S COM1 NS S COM2 S S COM3 NS S S Selection NS Non selection From this it can be seen that 0101 must be prepared in the display data memory address FA64H corresponding to S8 Examples of the LCD drive waveforms ...

Page 219: ... COM3 COM2 COM1 COM0 BIT0 BIT1 BIT2 BIT3 S0 S1 S2 S3 1 1 0 FA6CH 1 1 1 B 1 1 0 A 1 0 0 9 S4 S5 S6 S7 1 1 0 8 1 1 1 7 1 1 0 6 1 0 0 5 S8 S9 S10 S11 1 1 0 4 1 1 1 3 1 1 0 2 1 0 1 1 S12 S13 S14 S15 0 1 0 0 1 0 0 FA5FH 1 1 0 E 0 0 1 D S16 S17 S18 S19 1 0 0 C 0 1 1 B 0 1 0 A 0 0 0 FA59H Data memory address LCD panel 1 0 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 1 1 0 ...

Page 220: ...UM00 Figure 16 11 4 Time Division LCD Drive Waveform Examples 1 3 Bias Method TF VLC0 VLC2 COM0 VLCD 0 COM0 to S8 VLCD VLC1 1 3VLCD 1 3VLCD VSS VLC0 VLC2 COM1 VLC1 VSS VLC0 VLC2 COM2 VLC1 VSS VLC0 VLC2 COM3 VLC1 VSS VLCD 0 COM1 to S8 VLCD 1 3VLCD 1 3VLCD VLC0 VLC2 S8 VLC1 VSS ...

Page 221: ...1 when using the LCD controller driver Figure 16 12 LCD Timer Control Register LCDTM Format Address FF4AH After Reset 00H W Symbol 7 6 5 4 3 2 1 0 LCDTM 0 0 0 0 0 0 TMC21 0 TMC21 LCD Clock Supply Control 0 LCD controller driver stop mode supply of LCD clock is stopped 1 LCD controller driver operation mode supply of LCD clock is enabled Cautions 1 LCDTM is a special register that must be set when ...

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Page 223: ...an be varied to enable control of the buzzer sound volume Figure 17 1 shows the sound generator block diagram and Figure 17 2 shows the concept of basic cycle output signal SGO Figure 17 1 Sound Generator Block Diagram Internal bus Internal bus Sound generator control register SGCR TCE SGCL2 SGCL1 SGCL0 2 4 7 Q fX fSG1 fSG2 1 2 1 2 5 bit counter Comparator Comparator SGO P61 Clear Selector Selecto...

Page 224: ...uration The sound generator consists of the following hardware Table 17 1 Sound Generator Configuration Item Configuration Counter 8 bits 1 5 bits 1 SG output SGO Control register Sound generator control register SGCR Sound generator buzzer control register SGBR Sound generator amplitude register SGAM ...

Page 225: ...und generator buzzer control register SGBR Sound generator amplitude register SGAM 1 Sound generator control register SGCR SGCR is a register which sets up the following three types Controls sound generator output Selects sound generator input frequency fSG1 Selects 5 bit counter input frequency fSG2 SGCR is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears SGCR to 00H F...

Page 226: ...SG1 fX 2 1 fSG1 fX Cautions 1 Before setting the TCE bit set all the other bits 2 When rewriting SGCR to other data stop the timer operation TCE 0 beforehand 3 Bits 4 to 6 must be set to 0 4 Bit 3 must be set to 1 The maximum and minimum values of the buzzer output frequency are as follows Table 17 2 Maximum Value and Minimum Value of Buzzer Output Frequency SGCL2 SGCL1 SGCL0 Maximum and Minimum V...

Page 227: ...fX 8 38 MHz 0 0 0 0 3 677 3 851 0 0 0 1 3 472 3 637 0 0 1 0 3 290 3 446 0 0 1 1 3 125 3 273 0 1 0 0 2 976 3 117 0 1 0 1 2 841 2 976 0 1 1 0 2 717 2 847 0 1 1 1 2 604 2 728 1 0 0 0 2 500 2 619 1 0 0 1 2 404 2 518 1 0 1 0 2 315 2 425 1 0 1 1 2 232 2 339 1 1 0 0 2 155 2 258 1 1 0 1 2 083 2 182 1 1 1 0 2 016 2 112 1 1 1 1 1 953 2 046 Note Output frequency where SGCL0 SGCL1 and SGCL2 are all 0s Caution...

Page 228: ...0 0 0 1 0 0 1 10 128 0 0 0 1 0 1 0 11 128 0 0 0 1 0 1 1 12 128 0 0 0 1 1 0 0 13 128 0 0 0 1 1 0 1 14 128 0 0 0 1 1 1 0 15 128 0 0 0 1 1 1 1 16 128 0 0 1 0 0 0 0 17 128 0 0 1 0 0 0 1 18 128 0 0 1 0 0 1 0 19 128 0 0 1 0 0 1 1 20 128 0 0 1 0 1 0 0 21 128 0 0 1 0 1 0 1 22 128 0 0 1 0 1 1 0 23 128 0 0 1 0 1 1 1 24 128 0 0 1 1 0 0 0 25 128 0 0 1 1 0 0 1 26 128 0 0 1 1 0 1 0 27 128 0 0 1 1 0 1 1 28 128 0...

Page 229: ...in if the bit 7 TCE of the sound generator control register SGCR is set to 1 The basic cycle signal of the frequency set by SGCL0 to SGCL2 and SGBR0 to SGBR3 is output The amplitude of the basic cycle signal can be changed by changing the set value of the sound generator amplitude register SGAM Figure 17 6 Sound Generator Output Operation Timing Timer Comparator 1 coincidence SGO n n n n n n ...

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Page 231: ...1 shows the block diagram of the meter controller driver and Figure 18 2 shows 1 bit addition circuit block diagram Figure 18 1 Meter Controller Driver Block Diagram Remark n 1 to 4 Internal bus Compare register MCMPn0 8 bit timer register ftCC Selector 1 bit addition circuit fX fX 2 PCS PCE Compare register MCMPn1 1 bit addition circuit Internal bus MODn ENn Port mode control register PMC Timer m...

Page 232: ...ontrol register PMC Pulse controller 1 bit addition circuit output controller Remark n 1 to 4 1 Free running up counter MCNT MCNT is an 8 bit free running up counter and is a register that executes increment at the rising edge of input clock A PWM pulse with a resolution of 8 bits can be output The duty factor can be set in a range of 0 to 100 The count value is cleared in the following cases RESE...

Page 233: ...er n is generated 4 1 bit addition circuit The 1 bit addition circuit repeats 1 bit addition non addition to PWM output alternately upon MCNT overflow output and enables the state of PWM output between current compare value and the next compare value This circuit is controlled by bits 2 and 3 ADBn0 and ADBn1 of the MCMPCn register 5 Output controller The output controller consists of a P ch and N ...

Page 234: ... that controls the operation of the free running up counter MCNT MCNTC is set with an 8 bit memory manipulation instruction RESET input clears MCNTC to 00H Figure 18 3 shows the MCNTC format Figure 18 3 Timer Mode Control Register MCNTC Format Address FF69H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 MCNTC 0 0 PCS PCE 0 0 0 0 PCS Timer Counter Clock fMC Selection 0 fX 1 fX 2 PCE Timer Operation Con...

Page 235: ...Control Bit by Register from Master to Slave 0 Disables data transfer from master to slave New data can be written 1 Transfers data from master to slave when MCNT overflows New data cannot be written ADBn1 1 Bit Addition Circuit Control cos side of meter n 0 No 1 bit addition to PWM output 1 1 bit addition to PWM output ADBn0 1 Bit Addition Circuit Control sin side of meter n 0 No 1 bit addition t...

Page 236: ...tput pins is shown below ENn MODn DIRn1 DIRn0 SMn1 SMn2 SMn3 SMn4 Mode sin sin cos cos 0 Port Port Port Port Port mode 1 0 0 0 PWM 0 PWM 0 PWM mode full bridge 1 0 0 1 PWM 0 0 PWM 1 0 1 0 0 PWM 0 PWM 1 0 1 1 0 PWM PWM 0 1 1 0 0 PWM Port PWM Port PWM mode half bridge 1 1 0 1 PWM Port Port PWM 1 1 1 0 Port PWM Port PWM 1 1 1 1 Port PWM PWM Port DIRn1 and DIRn0 mean the quadrant of sin and cos DIRn1 ...

Page 237: ...C Figure 18 6 shows the timing from count start to restart Figure 18 6 Restart Timing after Count Stop Count Start Count Stop Count Start CLK MCNT PCE 0H 1H 2H 1H 2H 3H 4H N N 1 00H Count start Count stop Count start Remark N 00H to FFH 18 4 2 To update PWM data Confirm that bit 4 TENn of MCMPCn is 0 and then set 8 bit PWM data to MCMPn1 and MCMPn0 and bits 2 and 3 ADBn1 and ADBn0 of MCMPCn and at...

Page 238: ... enables the state of PWM output between current compare value N and the next compare value N 1 In this mode 1 bit addition to the PWM output is set by setting ADBn of the MCMPCn register to 1 and 1 bit non addition normal output is set by setting ADBn to 0 Remark n 1 to 4 MCNT value OVF overflow Match signal of expected value N PWM output of expected value N 1 bit non addition PWM output of expec...

Page 239: ...ter 1 sin SM11 SM12 Meter 1 cos SM13 SM14 Meter 2 sin SM21 SM22 Meter 2 cos SM23 SM24 Meter 3 sin SM31 SM32 Meter 3 cos SM33 SM34 Meter 4 sin SM41 SM42 Meter 4 cos SM43 SM44 If the wave of sin and cos of meters 1 to 4 rises and falls internally as indicated by the broken line the SM11 to SM44 pins always shift the count clock by 1 clock and output signals in order to prevent VDD GND from fluctuati...

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Page 241: ...nd a low interrupt priority group by setting the priority specify flag registers PR0L PR0H PR1L High priority interrupts can be issued even if there are low priority interrupts If two or more interrupts with the same priority are simultaneously generated each interrupt has a predetermined priority see Table 19 1 A standby release signal is generated Three external interrupt requests and sixteen in...

Page 242: ...rface SIO3 transfer Internal 0016H B 10 INTSER Generation of serial interface UART receive error 0018H 11 INTSR End of serial interface UART reception 001AH 12 INTST End of serial interface UART transmission 001CH 13 INTTM1 Generation of 8 bit timer register and capture 001EH register CR1 match signal 14 INTTM2 Generation of 8 bit timer register and capture 0020H register CR2 match signal 15 INTTM...

Page 243: ...ble address generator Standby release signal B Internal maskable interrupt Internal bus Interrupt request IF MK IE PR ISP Priority controller Vector table address generator Standby release signal C External maskable interrupt 16 bit timer capture input Internal bus Interrupt request IF MK IE PR ISP Priority controller Vector table address generator Standby release signal Sampling clock Edge detect...

Page 244: ...IE PR ISP Internal bus Interrupt request Priority controller Vector table address generator Standby release signal External interrupt edge enable register EGP EGN Edge detector E Software interrupt Internal bus Interrupt request Priority controller Vector table address generator IF Interrupt request flag IE Interrupt enable flag ISP In service priority flag MK Interrupt mask flag PR Priority speci...

Page 245: ...t request sources Table 19 2 Flags Corresponding to Interrupt Request Sources Interrupt Source Interrupt Request Flag Interrupt Mask Flag Priority Specify Flag Register Register Register INTWDT WDTIF IF0L WDTMK MK0L WDTPR PR0L INTAD ADIF ADMK ADPR INTOVF OVFIF OVFMK OVFPR INTTM00 TMIF00 TMMK00 TMPR00 INTTM01 TMIF01 TMMK01 TMPR01 INTTM02 TMIF02 TMMK02 TMPR02 INTP0 PIF0 PMK0 PPR0 INTP1 PIF1 PMK1 PPR...

Page 246: ...lation instruction RESET input clears these registers to 00H Figure 19 2 Interrupt Request Flag Register IF0L IF0H IF1L Format Address FFE0H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF0L PIF1 PIF0 TMIF02 TMIF01 TMIF00 OVFIF ADIF WDTIF Address FFE1H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF0H TMIF3 TMIF2 TMIF1 STIF SRIF SERIF CSIIF3 PIF2 Address FFE2H After Reset 00H R W Symbol 7 6 5 4 3 2 1 ...

Page 247: ... PMK1 PMK0 TMMK02 TMMK01 TMMK00 OVFMK ADMK WDTMK Address FFE5H After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK0H TMMK3 TMMK2 TMMK1 STMK SRMK SERMK CSIMK3 PMK2 Address FFE6H After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK1L 1 1 1 1 1 WTMK WTIMK CSIMK2 XXMKX Interrupt Servicing Control 0 Interrupt servicing enabled 1 Interrupt servicing disabled Cautions 1 If the watchdog timer is used in watchdog timer...

Page 248: ...tion RESET input sets these registers to FFH Figure 19 4 Priority Specify Flag Register PR0L PR0H PR1L Format Address FFE8H After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 PR0L PPR1 PPR0 TMPR02 TMPR01 TMPR00 OVFPR ADPR WDTPR Address FFE9H After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 PR0H TMPR3 TMPR2 TMPR1 STPR SRPR SERPR CSIPR3 PPR2 Address FFEAH After Reset FFH R W Symbol 7 6 5 4 3 2 1 0 PR1L 1 1 1 1 1 ...

Page 249: ...manipulation instruction RESET input clears these registers to 00H Figure 19 5 External Interrupt Rising Edge Enable Register EGP and External Interrupt Falling Edge Enable Register EGN Format Address FF48H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 EGP 0 0 0 0 0 EGP2 EGP1 EGP0 Address FF49H After Reset 00H R W Symbol 7 6 5 4 3 2 1 0 EGN 0 0 0 0 0 EGN2 EGN1 EGN0 EGPn EGNn INTPn Pin Valid Edge n 0 ...

Page 250: ...ES21 ES20 ES11 ES10 ES01 ES00 PRM01 PRM00 ES21 ES20 TI02 Valid Edge Selection 0 0 Falling edge 0 1 Rising edge 1 0 Interrupt disabled 1 1 Both rising and falling edges ES11 ES10 TI01 Valid Edge Selection 0 0 Falling edge 0 1 Rising edge 1 0 Interrupt disabled 1 1 Both rising and falling edges ES01 ES00 TI00 Valid Edge Selection 0 0 Falling edge 0 1 Rising edge 1 0 Interrupt disabled 1 1 Both risin...

Page 251: ...aved into a stack and the IE flag is reset to 0 If a maskable interrupt request is acknowledged the contents of the priority specify flag of the acknowledged interrupt are transferred to the ISP flag The PSW contents are also saved into the stack with the PUSH PSW instruction They are reset from the stack with the RETI RETB and POP PSW instructions RESET input sets PSW to 02H Figure 19 7 Program S...

Page 252: ...A new non maskable interrupt request generated during execution of a non maskable interrupt servicing program is acknowledged after the current execution of the non maskable interrupt servicing program is terminated following RETI instruction execution and one main routine instruction is executed However if a new non maskable interrupt request is generated twice or more during non maskable interru...

Page 253: ...am CPU processing WDTIF Interrupt request generated during this interval is acknowledged at WDTIF Watchdog timer interrupt request flag Start WDTM4 1 with watchdog timer mode selected Overflow in WDT WDT interrupt servicing Interrupt control register accessed Interval timer No Reset processing No Interrupt request generation Start of interrupt servicing Interrupt request held pending Yes Yes No Ye...

Page 254: ...ion of NMI request 1 NMI request 2 held pending Servicing of NMI request 2 that was pended b If two non maskable interrupt requests are generated during non maskable interrupt servicing program execution Main routine NMI request 1 Execution of 1 instruction Execution of NMI request 1 NMI request 2 held pending NMI request 3 held pending Servicing of NMI request 2 that was pended NMI request 3 not ...

Page 255: ...cks When PR 1 8 clocks 33 clocks Note If an interrupt request is generated just before a divide instruction the wait time is maximized Remark 1 clock 1 fCPU fCPU CPU clock If two or more maskable interrupt requests are generated simultaneously the request with a higher priority level specified in the priority specify flag is acknowledged first If two or more interrupts requests have the same prior...

Page 256: ...nterrupt servicing Start IF 1 MK 0 PR 0 IE 1 ISP 1 Interrupt request held pending Yes Yes No No Yes Interrupt request generation Yes No Low priority No No Yes Yes No IE 1 No Any high priority interrupt request among those simultaneously generated with PR 0 Yes High priority No Yes Yes No Vectored interrupt servicing Interrupt request held pending Interrupt request held pending Interrupt request he...

Page 257: ... the contents are saved into the stacks in the order of the program status word PSW then program counter PC the IE flag is reset to 0 and the contents of the vector table 003EH 003FH are loaded into PC and branched Return from a software interrupt is possible with the RETB instruction Caution Do not use the RETI instruction for returning from the software interrupt 8 clocks 7 clocks Instruction In...

Page 258: ...urrently being serviced is generated during interrupt servicing it is not acknowledged for multiple interrupt servicing Interrupt requests that are not enabled because of the interrupt disable state or they have a lower priority are held pending When servicing of the current interrupt ends the pending interrupt request is acknowledged following execution of one main processing instruction executio...

Page 259: ... the EI instruction must always be issued to enable interrupt request acknowledge Example 2 Multiple interrupt servicing does not occur due to priority control Main processing INTxx servicing INTyy servicing INTxx PR 0 INTyy PR 1 EI RETI IE 0 IE 0 EI 1 instruction execution RETI Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because its priority is lower tha...

Page 260: ...g EI 1 instruction execution RETI RETI INTxx PR 0 INTyy PR 0 IE 0 IE 0 Interrupt is not enabled during servicing of interrupt INTxx EI instruction is not issued therefore interrupt request INTyy is not acknowledged and multiple interrupt servicing does not take place The INTyy interrupt request is held pending and is acknowledged following execution of one main processing instruction PR 0 Higher p...

Page 261: ...H PR1L PR1H EGP and EGN registers Caution The BRK instruction is not one of the above listed interrupt request hold instruction However the software interrupt activated by executing the BRK instruction causes the IE flag to be cleared to 0 Therefore even if a maskable interrupt request is generated during execution of the BRK instruction the interrupt request is not acknowledged However a non mask...

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Page 263: ...a memory low voltage hold down to VDD 2 0 V is possible Thus the STOP mode is effective to hold data memory contents with ultra low current consumption Because this mode can be cleared upon interrupt request it enables intermittent operations to be carried out However because a wait time is required to secure an oscillation stabilization time after the STOP mode is cleared select the HALT mode if ...

Page 264: ...5 4 3 2 1 0 OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Oscillation Stabilization Time Selection When STOP Mode Is Cleared 0 0 0 212 fX 488 µs 0 0 1 214 fX 1 95 ms 0 1 0 215 fX 3 91 ms 0 1 1 216 fX 7 81 ms 1 0 0 217 fX 15 6 ms Other than above Setting prohibited Caution The wait time after the STOP mode is cleared does not include the time see a in the illustration below from STOP mode clea...

Page 265: ...ow Table 20 1 HALT Mode Operating Status HALT Mode Setting During HALT Instruction Execution Using Main System Clock Item Clock generator Main system clock can be oscillated Clock supply to CPU stops CPU Operation stops Port Output latch Status before HALT mode setting is held 16 bit timer Operable 8 bit timer Watch timer Watchdog timer A D converter Operation stops Serial interface Operable LCD c...

Page 266: ...xecuted Figure 20 2 HALT Mode Clear upon Interrupt Generation HALT instruction Wait Wait Operation mode HALT mode Operation mode Oscillation Clock Standby release signal Remarks 1 The broken line indicates the case when the interrupt request which has cleared the standby mode is acknowledged 2 Wait times are as follows When vectored interrupt service is carried out 8 to 9 clocks When vectored inte...

Page 267: ...scillation stop Clock RESET signal Oscillation Oscillation Reset period Remarks 1 fX Main system clock oscillation frequency 2 Figures in parentheses apply to operation with fX 8 38 MHz Table 20 2 Operation after HALT Mode Clear Clear Source MK PR IE ISP Operation Maskable interrupt request 0 0 0 Next address instruction execution 0 0 1 Interrupt service execution 0 1 0 1 Next address instruction ...

Page 268: ...fter execution of the STOP instruction After the wait set using the oscillation stabilization time select register OSTS the operation mode is set The operating status in the STOP mode is described below Table 20 3 STOP Mode Operating Status STOP Mode Setting During STOP Instruction Execution Using Main System Clock Item Clock generator Only main system clock oscillation is stopped CPU Operation st...

Page 269: ... of oscillation stabilization time vectored interrupt service is carried out If interrupt acknowledge is disabled the next address instruction is executed Figure 20 4 STOP Mode Clear upon Interrupt Generation STOP instruction Wait Time set by OSTS Oscillation stabilization wait status Operation mode STOP mode Operation mode Oscillation Clock Standby release signal Oscillation stop Oscillation Rema...

Page 270: ... mode STOP mode Operation mode Oscillation stop Clock RESET signal Oscillation Oscillation Reset period Remarks 1 fX Main system clock oscillation frequency 2 Figures in parentheses apply to operation with fX 8 38 MHz Table 20 4 Operation after STOP Mode Clear Clear Source MK PR IE ISP Operation Maskable interrupt request 0 0 0 Next address instruction execution 0 0 1 Interrupt service execution 0...

Page 271: ...ilization time just after reset clear When a high level is input to the RESET pin the reset is cleared and program execution starts after the lapse of oscillation stabilization time 217 fX The reset applied by watchdog timer overflow is automatically cleared after a reset and program execution starts after the lapse of oscillation stabilization time 217 fX see Figures 21 2 to 21 4 Cautions 1 For a...

Page 272: ...g of Reset due to Watchdog Timer Overflow Hi Z Normal operation Reset period Oscillation stop Oscillation stabilization time wait Normal operation Reset processing X1 Watchdog timer overflow Internal reset signal Port pin Figure 21 4 Timing of Reset in STOP Mode by RESET Input Delay Delay Hi Z Normal operation Oscillation stabilization time wait Normal operation Reset processing X1 RESET Internal ...

Page 273: ...ntrol register PCC 04H Memory size switching register IMS CFH Internal expansion RAM size switching register IXS 0CH Oscillation stabilization time select register OSTS 04H Oscillator mode register OSCM Note 3 00H 16 bit timer 0 TM0 Timer register TM0 00H Capture registers CR00 to CR02 00H Prescaler mode register PRM0 00H Mode control register TMC0 00H Capture pulse control register 0 CRC0 00H Not...

Page 274: ...0H Baud rate generator control register BRGC 00H Transmit shift register TXS FFH Receive buffer register RXB Serial interface SIO2 Operation mode register 2 CSIM2 00H Shift register 2 SIO2 00H Receive data buffer register SIRB2 Undefined Receive data buffer status register SRBS2 00H Serial interface SIO3 Operation mode register 3 CSIM3 00H Shift register 3 SIO3 00H LCD controller driver Display mo...

Page 275: ...0851 A µPD780852 A Internal ROM type Flash memory Mask ROM Internal ROM capacity 40 Kbytes 32 Kbytes 40 Kbytes IC pin None Available VPP pin Available None Electrical specifications See data sheet of each product Quality grade Standard for general Special for highly reliable electronic devices electronic devices Caution There are differences in noise immunity and noise radiation between the flash ...

Page 276: ...ut sets IMS to CFH Figure 22 1 Memory Size Switching Register IMS Format Address FFF0H After Reset CFH R W Symbol 7 6 5 4 3 2 1 0 IMS RAM2 RAM1 RAM0 0 ROM3 ROM2 ROM1 ROM0 RAM2 RAM1 RAM0 Internal High Speed RAM Capacity Selection 1 1 0 1 024 bytes Other than above Setting prohibited ROM3 ROM2 ROM1 ROM0 Internal ROM Capacity Selection 1 0 0 0 32 Kbytes 1 0 1 0 40 Kbytes Other than above Setting proh...

Page 277: ... with an 8 bit memory manipulation instruction RESET input sets IXS to 0CH Figure 22 2 Internal Expansion RAM Size Switching Register IXS Format Address FFF4H After Reset 0CH R W Symbol 7 6 5 4 3 2 1 0 IXS 0 0 0 IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0 IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0 Internal Expansion RAM Capacity Selection 0 1 0 1 1 512 bytes Other than above Setting prohibited Caution The initial ...

Page 278: ... used The transmission methods are selected with the VPP pulse numbers shown in Table 22 3 Table 22 3 Transmission Method List Transmission Method Number of Channels Pin Used Note Number of VPP Pulses 3 wire serial I O 2 SI3 P52 0 SO3 P51 SCK3 P50 SI2 P05 1 SO2 P04 SCK2 P03 UART 1 RxD P53 8 TxD P54 Note When the device enters the flash memory programming mode the pins not used for flash memory pro...

Page 279: ... input data Batch delete Deletes the entire memory contents Batch blank check Checks the deletion status of the entire memory High speed write Performs writing to flash memory according to write start address and number of write data bytes Continuous write Performs successive write operations using the data input with high speed write operation Status Checks the current operation mode and operatio...

Page 280: ...22 4 22 5 and 22 6 Figure 22 4 Flashpro III Connection Using 3 Wire Serial I O Method SIO3 VPP VDD RESET SCK SO SI GND VPP VDD RESET SCK3 SI3 SO3 VSS Flashpro III PD78F0852 µ Figure 22 5 Flashpro III Connection Using 3 Wire Serial I O Method SIO2 VPP VDD RESET SCK SO SI GND VPP VDD RESET SCK2 SI2 SO2 VSS Flashpro III PD78F0852 µ Figure 22 6 Flashpro III Connection Using UART Method VPP VDD RESET S...

Page 281: ...UM00 CHAPTER 23 INSTRUCTION SET This chapter lists the instruction set of the µPD780852 Subseries For details of the operation and machine language instruction code refer to the separate document 78K 0 SERIES USER S MANUAL Instructions U12326E ...

Page 282: ... A C etc or absolute names names in parentheses in the table below R0 R1 R2 etc can be used for description Table 23 1 Operand Identifiers and Description Formats Identifier Description Format r X R0 A R1 C R2 B R3 E R4 D R5 L R6 H R7 rp AX RP0 BC RP1 DE RP2 HL RP3 sfr Special function register symbol Note sfrp Special function register symbol 16 bit manipulatable register even addresses only Note...

Page 283: ... flag AC Auxiliary carry flag Z Zero flag RBS Register bank select flag IE Interrupt request enable flag NMIS Non maskable interrupt servicing flag Memory contents indicated by address or register contents in parentheses H L Higher 8 bits and lower 8 bits of 16 bit register Logical product AND Logical sum OR Exclusive logical sum exclusive OR Inverted data addr16 16 bit immediate data or label jdi...

Page 284: ...te 2 8 9 A HL byte HL byte A 2 8 9 HL byte A A HL B 1 6 7 A HL B HL B A 1 6 7 HL B A A HL C 1 6 7 A HL C HL C A 1 6 7 HL C A A r Note 3 1 2 A r A saddr 2 4 6 A saddr A sfr 2 6 A sfr A addr16 3 8 10 A addr16 XCH A DE 1 4 6 A DE A HL 1 4 6 A HL A HL byte 2 8 10 A HL byte A HL B 2 8 10 A HL B A HL C 2 8 10 A HL C Notes 1 When the internal high speed RAM area is accessed or instruction with no data ac...

Page 285: ...A HL byte 2 8 9 A CY A HL byte A HL B 2 8 9 A CY A HL B A HL C 2 8 9 A CY A HL C A byte 2 4 A CY A byte CY saddr byte 3 6 8 saddr CY saddr byte CY A r Note 4 2 4 A CY A r CY r A 2 4 r CY r A CY A saddr 2 4 5 A CY A saddr CY A addr16 3 8 9 A CY A addr16 CY A HL 1 4 5 A CY A HL CY A HL byte 2 8 9 A CY A HL byte CY A HL B 2 8 9 A CY A HL B CY A HL C 2 8 9 A CY A HL C CY Notes 1 When the internal high...

Page 286: ...A addr16 CY A HL 1 4 5 A CY A HL CY A HL byte 2 8 9 A CY A HL byte CY A HL B 2 8 9 A CY A HL B CY A HL C 2 8 9 A CY A HL C CY A byte 2 4 A A byte saddr byte 3 6 8 saddr saddr byte A r Note 3 2 4 A A r r A 2 4 r r A A saddr 2 4 5 A A saddr A addr16 3 8 9 A A addr16 A HL 1 4 5 A A HL A HL byte 2 8 9 A A HL byte A HL B 2 8 9 A A HL B A HL C 2 8 9 A A HL C Notes 1 When the internal high speed RAM area...

Page 287: ...r16 A HL 1 4 5 A A HL A HL byte 2 8 9 A A HL byte A HL B 2 8 9 A A HL B A HL C 2 8 9 A A HL C A byte 2 4 A byte saddr byte 3 6 8 saddr byte A r Note 3 2 4 A r r A 2 4 r A A saddr 2 4 5 A saddr A addr16 3 8 9 A addr16 A HL 1 4 5 A HL A HL byte 2 8 9 A HL byte A HL B 2 8 9 A HL B A HL C 2 8 9 A HL C Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When a...

Page 288: ...cumulator after Addition Decimal Adjust Accumulator after Subtract CY saddr bit 3 6 7 CY saddr bit CY sfr bit 3 7 CY sfr bit CY A bit 2 4 CY A bit CY PSW bit 3 7 CY PSW bit CY HL bit 2 6 7 CY HL bit saddr bit CY 3 6 8 saddr bit CY sfr bit CY 3 8 sfr bit CY A bit CY 2 4 A bit CY PSW bit CY 3 8 PSW bit CY HL bit CY 2 6 8 HL bit CY Notes 1 When the internal high speed RAM area is accessed or instruct...

Page 289: ...bit CY PSW bit 3 7 CY CY PSW bit CY HL bit 2 6 7 CY CY HL bit saddr bit 2 4 6 saddr bit 1 sfr bit 3 8 sfr bit 1 SET1 A bit 2 4 A bit 1 PSW bit 2 6 PSW bit 1 HL bit 2 6 8 HL bit 1 saddr bit 2 4 6 saddr bit 0 sfr bit 3 8 sfr bit 0 CLR1 A bit 2 4 A bit 0 PSW bit 2 6 PSW bit 0 HL bit 2 6 8 HL bit 0 SET1 CY 1 2 CY 1 1 CLR1 CY 1 2 CY 0 0 NOT1 CY 1 2 CY CY Notes 1 When the internal high speed RAM area is...

Page 290: ...PCH SP 1 PCL SP SP SP 2 PCH SP 1 PCL SP RETI 1 6 PSW SP 2 SP SP 3 R R R NMIS 0 PCH SP 1 PCL SP PSW SP 2 SP SP 3 PSW 1 2 SP 1 PSW SP SP 1 SP 1 rpH SP 2 rpL SP SP 2 PSW 1 2 PSW SP SP SP 1 R R R rpH SP 1 rpL SP SP SP 2 SP word 4 10 SP word MOVW SP AX 2 8 SP AX AX SP 2 8 AX SP addr16 3 6 PC addr16 BR addr16 2 6 PC PC 2 jdisp8 AX 2 8 PCH A PCL X BC addr16 2 6 PC PC 2 jdisp8 if CY 1 BNC addr16 2 6 PC PC...

Page 291: ...eset sfr bit BTCLR PC PC 3 jdisp8 if A bit 1 then reset A bit PC PC 4 jdisp8 if PSW bit 1 then reset PSW bit PC PC 3 jdisp8 if HL bit 1 then reset HL bit B B 1 then PC PC 2 jdisp8 if B 0 C C 1 then PC PC 2 jdisp8 if C 0 saddr saddr 1 then PC PC 3 jdisp8 if saddr 0 SEL RBn 2 4 RBS1 0 n NOP 1 2 No Operation EI 2 6 IE 1 Enable Interrupt DI 2 6 IE 0 Disable Interrupt HALT 2 6 Set HALT Mode STOP 2 6 Se...

Page 292: ...RUCTION SET Preliminary User s Manual U14581EJ3V0UM00 23 3 Instructions Listed by Addressing Type 1 8 bit instructions MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MULU DIVUW INC DEC ROR ROL RORC ROLC ROR4 ROL4 PUSH POP DBNZ ...

Page 293: ...XCH ROL SUB ADD ADD ADD ADD ADD RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC AND SUB SUB SUB SUB SUB OR SUBC SUBC SUBC SUBC SUBC XOR AND AND AND AND AND CMP OR OR OR OR OR XOR XOR XOR XOR XOR CMP CMP CMP CMP CMP r MOV MOV INC ADD DEC ADDC SUB SUBC AND OR XOR CMP B C DBNZ sfr MOV MOV saddr MOV MOV DBNZ INC ADD DEC ADDC SUB SUBC AND OR XOR CMP addr16 MOV PSW MOV MOV PUSH POP DE MOV HL MOV ROR4 ROL4 HL by...

Page 294: ... Only when rp BC DE HL 3 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF BTCLR Second Operand First Operand A bit MOV1 BT SET1 BF CLR1 BTCLR sfr bit MOV1 BT SET1 BF CLR1 BTCLR saddr bit MOV1 BT SET1 BF CLR1 BTCLR PSW bit MOV1 BT SET1 BF CLR1 BTCLR HL bit MOV1 BT SET1 BF CLR1 BTCLR CY MOV1 MOV1 MOV1 MOV1 MOV1 SET1 AND1 AND1 AND1 AND1 AND1 CLR1 OR1 OR1 OR1 OR1 OR1 NOT1 XOR1 XOR...

Page 295: ... addr5 addr16 4 Call branch instructions CALL CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ Second Operand First Operand Basic instruction BR CALL CALLF CALLT BR BR BC BNC BZ BNZ Compound BT instruction BF BTCLR DBNZ 5 Other instructions ADJBA ADJBS BRK RET RETI RETB SEL NOP EI DI HALT STOP ...

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Page 297: ...r s Manual U14581EJ3V0UM00 APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the µPD780852 Subseries Figure A 1 shows the development tool configuration ...

Page 298: ... Real time OS OS Debugging Tools Assembler package C compiler package C library source file Device file Language Processing Software On chip flash memory version In circuit emulator Power unit Emulation probe Conversion socket or conversion adapter Target system Host machine PC Interface adapter PC card interface etc Emulation board Flash programmer Flash memory writing environment ...

Page 299: ... This compiler converts programs written in C language into an object code executable C Compiler Package with a microcontroller This compiler is used in combination with an optional assembler package RA78K 0 and device file DF780852 Caution when using in PC environment This C compiler package is a DOS based application however using Project Manager which is included in the assembler package enable...

Page 300: ...h version Note 3P16 HP9000 Series 700 HP UX Rel 9 05 DAT DDS 3K13 SPARCstation SunOS Rel 4 1 4 3 5 inch 2HC FD 3K15 Solaris Rel 2 5 1 1 4 inch CGMT 3R13 NEWS RISC NEWS OS Rel 6 1 3 5 inch 2HC FD Note WindowsNT is not supported A 2 Flash Memory Writing Tools Flashpro III part number FL PR3 PG FP3 Flash Writer Remark FL PR3 is a product of Naito Densei Machida Mfg Co Ltd For details contact Naito De...

Page 301: ...t notebook type as Interface Adapter the IE 78K0 NS host machine It is compatible with the C bus IE 70000 CD IF A These PC card and interface cable are required when using a notebook as the IE 78K0 NS PC Card Interface host machine It is compatible with the PCMCIA socket IE 70000 PC IF C This adapter is required when using an IBM PC AT or compatible as the IE 78K0 NS host Interface Adapter machine...

Page 302: ...e testing on an independent basis from hardware development without having to use an in circuit emulator thereby providing higher development efficiency and software quality The SM78K0 is used in combination with the optional device file DF780852 Part Number µS SM78K0 Remark in the part number differs depending on the host machine and OS used µS SM78K0 Host Machine OS Supply Medium AA13 PC 9800 Se...

Page 303: ...00 Series 700 HP UX Rel 9 05 DAT DDS 3K13 SPARCstation SunOS Rel 4 1 4 3 5 inch 2HC FD 3K15 Solaris Rel 2 5 1 1 4 inch CGMT 3R13 NEWS RISC NEWS OS Rel 6 1 3 5 inch 2HC FD Note WindowsNT is not supported This is a control program used to debug the 78K 0 Series The graphical user interfaces employed are Windows for personal computers and OSF MotifTM for EWSs offering the standard appearance and oper...

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Page 305: ...ication form in advance and sign the User Agreement Remark and in the part number differ depending on the host machine and OS used µS RX78013 Product Outline Upper Limit of Mass Production Quantity 001 Evaluation object Do not use for mass produced products 100K Object for mass produced product 0 1 million units 001M 1 million units 010M 10 million units S01 Source program Source program for mass ...

Page 306: ...machine and OS used µS MX78K0 Product Outline Note 001 Evaluation object Use for trial product XX Object for mass produced product Use for mass produced product S01 Source program Can be purchased only when object for mass produced product is purchased Host Machine OS Supply Medium AA13 PC 9800 Series Windows Japanese version Notes 1 2 3 5 inch 2HD FD AB13 IBM PC AT and compatibles Windows Japanes...

Page 307: ... 1 MCMPC1 235 Compare control register 2 MCMPC2 235 Compare control register 3 MCMPC3 235 Compare control register 4 MCMPC4 235 Compare register cos side MCMP11 233 Compare register cos side MCMP21 233 Compare register cos side MCMP31 233 Compare register cos side MCMP41 233 Compare register sin side MCMP10 233 Compare register sin side MCMP20 233 Compare register sin side MCMP30 233 Compare regis...

Page 308: ...ter IMS 276 O Oscillation stabilization time select register OSTS 264 Oscillator mode register OSCM 93 P Port 0 P0 38 77 Port 1 P1 38 78 Port 2 P2 39 79 Port 3 P3 39 80 Port 4 P4 39 81 Port 5 P5 40 82 Port 6 P6 40 83 Port 8 P8 41 84 Port 9 P9 41 85 Port mode control register PMC 236 Port mode register 0 PM0 86 192 Port mode register 2 PM2 86 Port mode register 3 PM3 86 Port mode register 4 PM4 86 ...

Page 309: ...eration mode register 2 CSIM2 189 Serial operation mode register 3 CSIM3 203 16 bit timer mode control register TMC0 105 16 bit timer register TM0 104 Sound generator amplitude register SGAM 227 Sound generator buzzer control register SGBR 227 Sound generator control register SGCR 225 T Timer clock select register 1 TCL1 115 Timer clock select register 2 TCL2 124 Timer clock select register 3 TCL3...

Page 310: ...register 2 123 CR3 8 bit compare register 3 123 CRC0 Capture pulse control register 106 CSIM2 Serial operation mode register 2 189 CSIM3 Serial operation mode register 3 203 D DAM1 D A converter mode register 168 E EGN External interrupt falling edge enable register 249 EGP External interrupt rising edge enable register 249 I IF0H Interrupt request flag register 0H 246 IF0L Interrupt request flag ...

Page 311: ... P P0 Port 0 38 77 P1 Port 1 38 78 P2 Port 2 39 79 P3 Port 3 39 80 P4 Port 4 39 81 P5 Port 5 40 82 P6 Port 6 40 83 P8 Port 8 41 84 P9 Port 9 41 85 PCC Processor clock control register 92 PFM Power fail compare mode register 159 PFT Power fail compare threshold value register 159 PM0 Port mode register 0 86 192 PM2 Port mode register 2 86 PM3 Port mode register 3 86 PM4 Port mode register 4 86 107 ...

Page 312: ...egister 191 T TCL1 Timer clock select register 1 115 TCL2 Timer clock select register 2 124 TCL3 Timer clock select register 3 124 TM0 16 bit timer register 104 TM1 8 bit counter 1 114 TM2 8 bit counter 2 123 TM3 8 bit counter 3 123 TMC0 16 bit timer mode control register 105 TMC1 8 bit timer mode control register 1 116 TMC2 8 bit timer mode control register 2 125 TMC3 8 bit timer mode control reg...

Page 313: ...ion Chapter 2nd edition Changing 1 5 Pin Configuration Top View CHAPTER 1 OUTLINE Changing description of supply voltage in 1 8 Outline of Function Changing 6 4 4 Port mode register 4 PM4 CHAPTER 6 16 BIT TIMER 0 TM0 Changing Figure 6 11 Capture Register Data Retention Timing Adding Caution 3 to Figure 16 4 LCD Display Control Register CHAPTER 16 LCD CONTROLLER LCDC Format DRIVER Adding Note to Ta...

Page 314: ...314 Preliminary User s Manual U14581EJ3V0UM00 MEMO ...

Page 315: ... 02 2719 5951 Address North America NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Technical Documentation Dept Fax 49 211 6503 274 South America NEC do Brasil S A Fax 55 11 6462 6829 Asian Nations except Philippines NEC Electronics Singapore Pte Ltd Fax 65 250 3583 Japan NEC Semiconductor Technical Hotline Fax 044 435 9608 I ...

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NEC mPD780851, Preliminary User'S Manual

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