NEC mPD780851, Preliminary User'S Manual

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CHAPTER 14 SERIAL INTERFACE SIO2
Preliminary User’s Manual U14581EJ3V0UM00
(5) Transfer format
A simultaneous transmit/receive operation can be performed when the receive data is transferred from the serial
I/O shift register 2 (SIO2) to the receive data buffer register (SIRB2).
(a) Clock phase and polarity
The phase and polarity of the serial clock can be selected from four combinations by setting bits 3 and 4
(CLPO and CLPH) of the serial operation mode register 2 (CSIM2).
Select a clock polarity by using CLPO. An active-high or active-low clock can be selected.
The clock phase is set by CLPH. The output timing of SO2 can be selected.
For the setting of CLPO and CLPH, serial transfer clock, data output, and the capture timing of input data,
see Figure 14-3.
(b) Transfer format when CLPH = 0
Figure 14-6 shows the operation timing when CLPH = 0. Two waves of SCK2, when CLPO = 0 and when
CLPO = 1, are shown in the figure.
Data is transmitted or received in 8-bit units. Each bit of data is transmitted or received in synchronization
with the serial clock.
SIO2 is shifted at the falling edge of SCK2 if CLPH = 0 and CLPO = 0. If CLPH = 0 and CLPO = 1, SIO2
is shifted at the rising edge of SCK2. The transmit data is held by the SO2 latch and output from the SO2
pin. The receive data input to the SI2 pin is latched to SIO2 at the rising edge of SCK2 (if CLPH = 0 and
CLPO = 0).
Completion of an 8-bit transfer automatically stops operation of SIO2 and sets a serial transfer completion
flag.
Figure 14-6. Operation Timing When CLPH Is Set to 0
(Serial output data: 55H, serial input data: AAH)
ABH 56H ADH 5AH B5H 6AH D5H AAH
AAH
(Write: SIO2 = 55H)
(AAH)
(55H)
SCK2
(CLPO = 0)
Serial output
data timing
Start trigger
operation timing
SIRB2
SI2
SO2
INTCSI2
(interrupt request
generated at rising edge)
SCK2
(CLPO = 1)
55H