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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53
User’s Manual U15104EJ2V0UD
(2) Timer clock select register 53 (TCL53)
This register selects the count clock of 8-bit timer counter 53 (TM53).
TCL53 is set with an 8-bit memory manipulation instruction.
Reset input clears TCL53 to 00H.
Figure 6-6. Format of Timer Clock Select Register 53 (TCL53)
TCL532 TCL531 TCL530
Count clock selection
0
0
0
Setting prohibited
0
0
1
Setting prohibited
0
1
0
f
X
/2
(2.25 MHz)
0
1
1
f
X
/2
3
(563 kHz)
1
0
0
f
X
/2
5
(141 kHz)
1
0
1
f
X
/2
7
(35.2 kHz)
1
1
0
f
X
/2
9
(8.79 kHz)
1
1
1
f
X
/2
11
(2.20 kHz)
Cautions 1. Before changing the data of TCL53, be sure to stop the timer operation.
2. Be sure to reset bits 3 to 7 to 0.
Remarks 1. In the cascade mode, the setting of bit TCL53 of the higher timer (TM53) is invalid.
2. f
X
: System clock oscillation frequency
3. ( ): f
X
= 4.5 MHz
(3) 8-bit timer mode control registers 50 to 52 (TMC50 to TMC52)
The TMC5n register is used for the following.
<1> Controlling count operation of 8-bit timer counter 5n (TM5n)
<2> Selecting operation mode of 8-bit timer counter 5n (TM5n)
<3> Selecting single mode or cascade mode
<4> Setting status of timer output F/F (flip-flop)
<5> Controlling timer F/F or selecting active level in PWM (free-running) mode
<6> Controlling timer output
TMC5n can be set with a 1-bit or 8-bit memory manipulation instruction.
Reset input clears TMC5n to 00H.
Remark
n = 0 to 2
7
6
5
4
3
0
0
0
TCL532 TCL531 TCL530
0
0
2
1
0
Symbol
TCL53
Address
FF77H
After reset
00H
R/W
R/W
