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NEC mPD178054 Series, User Manual

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NEC mPD178054 Series User Manual Download Page 18

18

User’s Manual  U15104EJ2V0UD

LIST OF FIGURES (4/4)

Figure No.

Title

Page

15-1

Format of Oscillation Stabilization Time Select Register (OSTS) ....................................................

204

15-2

HALT Mode Release upon Interrupt Generation ...............................................................................

206

15-3

HALT Mode Release by RESET Input ...............................................................................................

207

15-4

STOP Mode Release by Interrupt Request Generation ...................................................................

209

15-5

Release by STOP Mode RESET Input ..............................................................................................

210

16-1

Reset Function Block Diagram ...........................................................................................................

212

16-2

Timing of Reset by RESET Input .......................................................................................................

213

16-3

Timing of Reset due to Watchdog Timer Overflow ...........................................................................

214

16-4

Timing of Reset by Power-on Clear ...................................................................................................

215

16-5

Format of POC Status Register (POCS) ...........................................................................................

218

16-6

Format of POC Status Register (POCS) ...........................................................................................

219

17-1

Format of Memory Size Switching Register (IMS) ............................................................................

221

17-2

Format of Internal Expansion RAM Size Switching Register (IXS) ..................................................

222

17-3

Format of Communication Mode Selection .......................................................................................

223

17-4

Connection of Flashpro III in 3-Wire Serial I/O Mode .......................................................................

224

A-1

Configuration of Development Tools ..................................................................................................

253

A-2

EV-9200GC-80 Package Drawing (for Reference Only) ...................................................................

262

A-3

EV-9200GC-80 Recommended Board Mounting Pattern (for Reference Only) ..............................

263

Summary of Contents for mPD178054 Series

Page 1: ...User s Manual Printed in Japan PD178054 Subseries 8 Bit Single Chip Microcontrollers PD178053 PD178054 PD178F054 Document No U15104EJ2V0UD00 2nd edition Date Published January 2002 N CP K 2001...

Page 2: ...2 User s Manual U15104EJ2V0UD MEMO...

Page 3: ...devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to VDD or GND with a resistor if it is considered to have a possibility of being an outp...

Page 4: ...ing from the use of these circuits software and information While NEC endeavours to enhance the quality reliability and safety of NEC semiconductor products customers agree and acknowledge that the po...

Page 5: ...Electronics Germany GmbH Duesseldorf Germany Tel 0211 65 03 02 Fax 0211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Italiana s r l Milano Ita...

Page 6: ...Alternate Functions p 124 Modification of description in 3 Oscillation stabilization time select register OSTS in 8 3 Registers Controlling Watchdog Timer p 240 Addition of CHAPTER 19 ELECTRICAL SPECI...

Page 7: ...f electric and logic circuits and microcomputers When you want to understand the functions in general Read this manual in the order of the contents To know the PD178054 Subseries instruction function...

Page 8: ...embly Language U14446E Structured Assembly Language U11789E CC78K0 C Compiler Operation U14297E Language U14298E SM78K0S SM78K0 System Simulator Ver 2 10 or Later Operation U14611E Windows Based SM78K...

Page 9: ...er User s Manual U13502E Other Related Documents Document Name Document No SEMICONDUCTOR SELECTION GUIDE Products Packages X13769E Semiconductor Device Mounting Technology Manual C10535E Quality Grade...

Page 10: ...2 6 P60 to P67 Port 6 31 2 2 7 P70 to P77 Port 7 31 2 2 8 P120 to P125 Port 12 32 2 2 9 P130 to P132 Port 13 32 2 2 10 EO0 EO1 32 2 2 11 VCOL VCOH 32 2 2 12 AMIFC 33 2 2 13 FMIFC 33 2 2 14 RESET 33 2...

Page 11: ...ing 67 3 4 9 Stack addressing 67 CHAPTER 4 PORT FUNCTIONS 68 4 1 Port Functions 68 4 2 Port Configuration 70 4 2 1 Port 0 70 4 2 2 Port 1 71 4 2 3 Port 3 72 4 2 4 Port 4 74 4 2 5 Port 5 75 4 2 6 Port...

Page 12: ...ling Watchdog Timer 121 8 4 Operations of Watchdog Timer 125 8 4 1 Watchdog timer operation 125 8 4 2 Interval timer operation 126 CHAPTER 9 BUZZER OUTPUT CONTROLLER 127 9 1 Functions of Buzzer Output...

Page 13: ...f PLL frequency synthesizer 189 13 5 PLL Disable Status 194 13 6 Notes on PLL Frequency Synthesizer 194 CHAPTER 14 FREQUENCY COUNTER 195 14 1 Function of Frequency Counter 195 14 2 Configuration of Fr...

Page 14: ...CHAPTER 20 PACKAGE DRAWING 250 CHAPTER 21 RECOMMENDED SOLDERING CONDITIONS 251 APPENDIX A DEVELOPMENT TOOLS 252 A 1 Software Package 255 A 2 Language Processing Software 255 A 3 Control Software 256...

Page 15: ...ock Diagram of P30 to P32 and P35 72 4 6 Block Diagram of P33 and P34 73 4 7 Block Diagram of P36 and P37 73 4 8 Block Diagram of P40 to P47 74 4 9 Block Diagram of Key Input Detector 75 4 10 Block Di...

Page 16: ...imer Count Operation 116 7 1 Block Diagram of Basic Timer 117 7 2 Operation Timing of Basic Timer 118 7 3 Operating Timing to Poll BTMIF0 Flag 118 8 1 Block Diagram of Watchdog Timer 119 8 2 Format of...

Page 17: ...2 10 Interrupt Request Acknowledgement Processing Algorithm 170 12 11 Interrupt Request Acknowledgement Timing Minimum Time 171 12 12 Interrupt Request Acknowledgement Timing Maximum Time 171 12 13 Mu...

Page 18: ...Input 213 16 3 Timing of Reset due to Watchdog Timer Overflow 214 16 4 Timing of Reset by Power on Clear 215 16 5 Format of POC Status Register POCS 218 16 6 Format of POC Status Register POCS 219 17...

Page 19: ...advertent Program Loop Detection Time 125 8 5 Interval Timer Interval Time 126 9 1 Configuration of Buzzer Output Controllers 128 10 1 Configuration of A D Converter 130 11 1 Configuration of Serial I...

Page 20: ...ng Register 221 17 3 Set Value of Internal Expansion RAM Size Switching Register 222 17 4 Communication Modes 223 17 5 Major Functions of Flash Memory Programming 224 17 6 Setting Example for Flashpro...

Page 21: ...ce 3 channels 3 wire serial I O mode 2 channels 3 wire serial I O mode on chip time division transfer function 1 channel Timer 6 channels Basic timer timer carry FF 1 channel 8 bit timer event counter...

Page 22: ...104EJ2V0UD 1 2 Applications Car stereos 1 3 Ordering Information Part Number Package PD178053GC 8BT 80 pin plastic QFP 14 14 PD178054GC 8BT 80 pin plastic QFP 14 14 PD178F054GC 8BT 80 pin plastic QFP...

Page 23: ...ANI5 P70 SI30 P71 SO30 P72 SCK30 P73 P74 SI31 P75 SO31 P76 SCK31 P77 TI52 P130 TO50 P131 TO51 P132 TO52 P40 P41 P42 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 P37 BUZ P36 BEEP0 P35 P34 TI51 P...

Page 24: ...P47 Port 4 P50 to P57 Port 5 P60 to P67 Port 6 P70 to P77 Port 7 P120 to P125 Port 12 P130 to P132 Port 13 REGCPU Regulator for CPU power supply REGOSC Regulator for oscillator RESET Reset input SCK3...

Page 25: ...PD178F054 Enhanced timer 3 wire serial I O 80 pins 80 pins PD178054 Subseries PD178F124 On chip IEBus controller 80 pins 80 pins PD178024 Subseries On chip IEBusTM controller UART Enhanced timer 3 wi...

Page 26: ...ncy counter PLL voltage regulator Buzzer output 78K 0 CPU Core RAM 1024 bytes ROM Flash memory TI50 P33 TO50 P130 P00 to P06 P10 to P15 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P120 to P...

Page 27: ...er 4 channels Watchdog timer 1 channel Buzzer output BEEP pin 1 kHz 1 5 kHz 3 kHz 4 kHz BUZ pin 549 Hz 1 10 kHz 2 20 kHz 4 39 kHz Vectored Maskable Internal 11 interrupt External 5 sources Non maskabl...

Page 28: ...ied in 1 bit units An on chip pull up resistor can be specified by software Interrupt function by key input is provided P50 to P57 I O Port 5 Input 8 bit I O port Input output can be specified in 1 bi...

Page 29: ...utput Input P36 BUZ P37 ANI0 to ANI5 Input Analog input to A D converter Input P10 to P15 EO0 EO1 Output Error out output from charge pump of PLL frequency synthesizer VCOL Input Inputs local oscillat...

Page 30: ...to P15 constitute a 6 bit input port In addition to input port pins P10 to P15 function as A D converter analog inputs The following operating modes can be specified in 1 bit units 1 Port mode These...

Page 31: ...port These pins can be specified as input or output in 1 bit units using port mode register 6 PM6 2 2 7 P70 to P77 Port 7 P70 to P77 pins constitute an 8 bit I O port In addition to port pins P70 to P...

Page 32: ...1 bit units 1 Port mode These pins function as a 3 bit output port 2 Control mode These pins function as output pins for the 8 bit timer event counter TO50 TO51 TO52 These pins are output pins for th...

Page 33: ...y counter 2 2 14 RESET Low level active system reset input pin 2 2 15 X1 X2 Crystal resonator connection pins for system clock oscillation 2 2 16 REGOSC Regulator pin for oscillator Connect to GND via...

Page 34: ...s at delivery Connect it directly to the GND pin with the shortest possible wire in the normal operating mode When a potential difference is produced between the IC pin and GND pin because the wiring...

Page 35: ...DD VDDPORT GND or GNDPORT P30 to P32 5 I O Input Connect to VDD VDDPORT GND or GNDPORT via a resistor P33 TI50 5 K Output Leave open P34 TI51 P35 5 P36 BEEP0 P37 BUZ P40 to P47 5 A P50 to P57 5 P60 to...

Page 36: ...DD and GND as VDDPORT and GNDPORT Type 2 Type 5 Type 5 A Type 5 K Type 8 Type 19 IN Schmitt triggered input with hysteresis characteristics VDD P ch P ch N ch IN OUT Pull up enable Data Output disable...

Page 37: ...le by software only for the VCOL and VCOH pins Remark VDD and GND are the positive power supply and ground pins for all port pins Read VDD and GND as VDDPORT and GNDPORT Type 25 Input enable Comparato...

Page 38: ...CHITECTURE 3 1 Memory Space The initial value of the memory size switching register IMS is CFH The following values must be set to the registers of each model Part Number IMS PD178053 C6H PD178054 C8H...

Page 39: ...H F E E 0 H F E D F H F B 0 0 H F A F F H 6 0 0 0 H 5 F F F H 0 0 0 0 H 5 F F F H 1 0 0 0 H 0 F F F H 0 8 0 0 H 0 7 F F H 0 0 8 0 H 0 0 7 F H 0 0 4 0 H 0 0 3 F H Special function registers SFRs 256 8...

Page 40: ...H F E E 0 H F E D F H F B 0 0 H F A F F H 8 0 0 0 H 7 F F F H 0 0 0 0 H 7 F F F H 1 0 0 0 H 0 F F F H 0 8 0 0 H 0 7 F F H 0 0 8 0 H 0 0 7 F H 0 0 4 0 H 0 0 3 F H Special function registers SFRs 256 8...

Page 41: ...0 0 0 0 H F F 0 0 H F E F F H F E E 0 H F E D F H F B 0 0 H F A F F H 8 0 0 0 H 7 F F F H 0 0 0 0 H 7 F F F H 1 0 0 0 H 0 F F F H 0 8 0 0 H 0 7 F F H 0 0 8 0 H 0 0 7 F H 0 0 4 0 H 0 0 3 F H Special fu...

Page 42: ...owing areas are assigned to the internal program memory space 1 Vector table area The 64 byte area 0000H to 003FH is reserved as a vector table area The reset input and program start addresses for bra...

Page 43: ...ncorporate the following RAMs 1 Internal high speed RAM The PD178053 178054 and 178F054 have a RAM structure of 1024 8 bits In this area four banks of general purpose registers each bank consisting of...

Page 44: ...containing data memory in particular special addressing methods designed for the functions of special function registers SFR and general purpose registers are available for use Data memory addressing...

Page 45: ...H F E 2 0 H F E 1 F H F B 0 0 H F A F F H 8 0 0 0 H 7 F F F H 0 0 0 0 H Special function registers SFRs 256 8 bits Internal high speed RAM 1024 8 bits General purpose registers 32 8 bits Reserved Int...

Page 46: ...F H F E 2 0 H F E 1 F H F B 0 0 H F A F F H 8 0 0 0 H 7 F F F H 0 0 0 0 H Special function registers SFRs 256 8 bits Internal high speed RAM 1024 8 bits General purpose registers 32 8 bits Reserved Fl...

Page 47: ...truction to be fetched When a branch instruction is executed immediate data and register contents are set Reset input sets the reset vector table values at addresses 0000H and 0001H to the program cou...

Page 48: ...ne of the four register banks In these flags the 2 bit information which indicates the register bank selected by SEL RBn instruction execution is stored d Auxiliary carry flag AC If the operation resu...

Page 49: ...input makes SP contents undefined be sure to initialize the SP before instruction execution Figure 3 10 Data to Be Saved to Stack Memory Figure 3 11 Data to Be Restored from Stack Memory SP15 SP SP14...

Page 50: ...register bank configuration an efficient program can be created by switching between a register for normal processing and a register for interrupt for each bank Table 3 3 Absolute Address of General P...

Page 51: ...egister a Absolute Name b Function Name BANK0 BANK1 BANK2 BANK3 FEFFH FEF8H FEE0H RP3 RP2 RP1 RP0 R7 15 0 7 0 R6 R5 R4 R3 R2 R1 R0 16 bit processing 8 bit processing FEE0H FEE8H BANK0 BANK1 BANK2 BANK...

Page 52: ...an address 16 bit manipulation Use the symbol reserved in the assembler for the 16 bit manipulation instruction operand sfrp When addressing an address use an even address Table 3 4 gives a list of s...

Page 53: ...Port mode register 4 PM4 FF25H Port mode register 5 PM5 FF26H Port mode register 6 PM6 FF27H Port mode register 7 PM7 FF2CH Port mode register 12 PM12 FF34H Pull up resistor option register 4 PU4 00H...

Page 54: ...mer counter 51 TM51 FF84H Timer clock select register 50 TCL50 R W FF85H 8 bit timer mode control register 50 TMC50 FF87H Timer clock select register 51 TCL51 FF88H 8 bit timer mode control register 5...

Page 55: ...Memory size switching register IMS CFHNote 2 FFF4H Internal expansion RAM size switching register IXS 0CHNote 3 FFF9H Watchdog timer mode register WDTM 00H FFFAH Oscillation stabilization time switchi...

Page 56: ...elative addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the p...

Page 57: ...BR addr16 or CALLF addr11 instruction is executed The CALL addr16 and BR add16 instructions can be used to branch to any location in the memory The CALLF addr11 instruction is used to branch to the ar...

Page 58: ...are transferred to the program counter PC and branched This addressing is used when the CALLT addr5 instruction is executed This instruction references an address stored in the memory table between 40...

Page 59: ...4 Register addressing Function Register pair AX contents to be specified with an instruction word are transferred to the program counter PC and branched This function is carried out when the BR AX in...

Page 60: ...struction Register to Be Specified by Implied Addressing MULU A register for multiplicand and AX register for product storage DIVUW AX register for dividend and quotient storage ADJBA ADJBS A register...

Page 61: ...n instruction with the following operand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the operation code Operand format Symbol Descript...

Page 62: ...data in an instruction word is directly addressed Operand format Symbol Description addr16 Label or 16 bit immediate data Example MOV A 0FE00H when setting addr16 to FE00H Operation code 1 0 0 0 1 1 1...

Page 63: ...e register of the timer event counter are mapped and these SFRs can be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is s...

Page 64: ...40 byte spaces FF00H to FFCFH and FFE0H to FFFFH However the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing Operand format Symbol Description sfr Special function register n...

Page 65: ...ified by the register pair code in an instruction word as the operand address The register pair specified is in the register bank specified by the register bank select flags RBS0 and RBS1 This address...

Page 66: ...as a base register The HL register pair accessed is the register in the register bank specified by the register bank select flags RBS0 and RBS1 Addition is performed by expanding the offset data as a...

Page 67: ...ing the offset data as a positive number to 16 bits A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format Symbol Description HL B HL C Exampl...

Page 68: ...4 1 shows the port configuration Every port is capable of 1 bit and 8 bit manipulations and can carry out considerably varied control operations Besides port functions the ports can also serve as on c...

Page 69: ...ed in 1 bit units An on chip pull up resistor can be specified by software Interrupt function by key input is provided P50 to P57 I O Port 5 8 bit I O port Input output can be specified in 1 bit units...

Page 70: ...tions include external interrupt request input Reset input sets port 0 to the input mode Figures 4 2 and 4 3 show the block diagrams of port 0 Caution Because port 0 also serves as an external interru...

Page 71: ...ut Figure 4 4 shows the block diagram of port 1 Figure 4 4 Block Diagram of P10 to P15 RD Port 1 read signal Figure 4 3 Block Diagram of P05 and P06 PM Port mode register RD Port 0 read signal WR Port...

Page 72: ...ort mode register 3 PM3 Alternate functions include timer input and buzzer output Reset input sets port 3 to the input mode Figures 4 5 to 4 7 show the block diagrams of port 3 Figure 4 5 Block Diagra...

Page 73: ...WR Port 3 write signal Figure 4 7 Block Diagram of P36 and P37 PM Port mode register RD Port 3 read signal WR Port 3 write signal P33 TI50 P34 TI51 RD WRPORT WRPM Alternate function Output latch P33 P...

Page 74: ...errupt request flag KYIF can be set to 1 by detecting key inputs When using this function be sure to set the MEM register to 01H Reset input sets port 4 to input mode Figures 4 8 and 4 9 show a block...

Page 75: ...turn can be detected only when all the pins of P40 to P47 are high level When any one is low level even if falling edge is generated at the other pins the key return signal cannot be detected 4 2 5 Po...

Page 76: ...specified for port 6 in 1 bit units using port mode register 6 PM6 Reset input sets port 6 to the input mode Figure 4 11 shows the block diagram of port 6 Figure 4 11 Block Diagram of P60 to P67 PM Po...

Page 77: ...Alternate functions include serial interface data I O clock I O and timer input Reset input sets port 7 to the input mode Figures 4 12 to 4 15 show the block diagrams of port 7 Figure 4 12 Block Diag...

Page 78: ...register RD Port 7 read signal WR Port 7 write signal RD P71 SO30 P75 SO31 WRPORT WRPM Output latch P71 P75 PM71 PM75 Selector Alternate function Internal bus PM Port mode register RD Port 7 read sign...

Page 79: ...R 4 PORT FUNCTIONS User s Manual U15104EJ2V0UD Figure 4 15 Block Diagram of P73 PM Port mode register RD Port 7 read signal WR Port 7 write signal RD P73 WRPORT WRMM Output latch P73 PM73 Selector Int...

Page 80: ...ster 12 PM12 Alternate functions include serial interface data I O and clock I O Reset input sets port 12 to the input mode Figures 4 16 to 4 18 show the block diagrams of port 12 Figure 4 16 Block Di...

Page 81: ...ignal Figure 4 18 Block Diagram of P122 and P125 PM Port mode register RD Port 12 read signal WR Port 12 write signal WRPM WRPORT RD Selector Output latch P121 P124 PM121 PM124 Internal bus Alternate...

Page 82: ...f this port are also used as timer output pins Reset input sets port 13 in the general purpose output port mode The port 13 block diagram is shown in Figure 4 19 Figure 4 19 Block Diagram of P130 to P...

Page 83: ...t with a 1 bit or 8 bit memory manipulation instruction Reset input sets these registers to FFH When using a port pin as an alternate function pin set the values of the port mode registers and the out...

Page 84: ...0 SI30 Input 1 P71 SO30 Output 0 0 P72 SCK30 Input 1 Output 0 0 P74 SI31 Input 1 P75 SO31 Output 0 0 P76 SCK31 Input 1 Output 0 0 P77 TI52 Input 1 P120 SI32 Input 1 P121 SO32 Output 0 0 P122 SCK32 Inp...

Page 85: ...et R W PM77 PM76 PM75 PM74 PM73 PM72 PM71 PM70 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 PM6 FF26H FFH R W PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60 PM05 PM04 PM12...

Page 86: ...ly for the bit specified by PU4 PU4 can be set with a 1 bit or 8 bit memory manipulation instruction Reset input sets PU4 to 00H Figure 4 21 Format of Pull up Resistor Option Register 4 PU4 PU4n Selec...

Page 87: ...pins the output latch contents for pins specified as input are undefined except for the manipulated bit 4 4 2 Reading from I O ports 1 Output mode The output latch contents are read by a transfer ins...

Page 88: ...system clock select register DTSCK to 1 Set the DTSCK0 flag after power application and reset by the RESET pin and before using the basic timer buzzer output control circuit PLL frequency synthesizer...

Page 89: ...Configuration Control register Processor clock control register PCC Oscillator System clock oscillator Figure 5 2 Block Diagram of Clock Generator System clock oscillator X2 X1 STOP 0 0 0 0 PCC2 PCC1...

Page 90: ...to 04H Figure 5 3 Format of Processor Clock Control Register PCC Note Bits 3 to 7 are read only Remarks 1 fX System clock oscillation frequency 2 Minimum instruction execution time 2 fCPU at fX 4 5 MH...

Page 91: ...When using a system clock oscillator wire as follows in the area enclosed by the broken lines in Figure 5 4 to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possib...

Page 92: ...Connection 1 2 a Wiring of connection b Signal lines cross circuits is too long each other c High fluctuating current is near a d Current flows through the ground line signal lines of the oscillator...

Page 93: ...RATOR User s Manual U15104EJ2V0UD Figure 5 5 Examples of Incorrect Resonator Connection 2 2 e Signals are fetched 5 4 2 Divider The divider divides the system clock oscillator output fX and generates...

Page 94: ...by the processor clock control register PCC a Upon generation of the RESET signal the lowest speed mode of the system clock 7 11 s when operated at 4 5 MHz is selected PCC 04H System clock oscillation...

Page 95: ...ructions 2 instructions 1 0 0 1 instruction 1 instruction 1 instruction 1 instruction Set Values After Switching Set Values Before Switching Remark One instruction is the minimum instruction execution...

Page 96: ...In this mode the following functions can be used Interval timer External event counter Square wave output PWM output Caution Timer 53 can be used only as an interval timer since it does not include ti...

Page 97: ...us TCE50 TMC506 TMC504 LVS50 LVR50 TMC501 TOE50 Level inversion Timer mode control register 50 TMC50 S R S Q R INV Selector INTTM50 TO50 P130 fX 2 Output latch P130 Selector Selector Mask circuit Inte...

Page 98: ...TCL520 Timer clock select register 52 TCL52 Internal bus TCE52 TMC526 TMC524 LVS52 LVR52 TMC521 TOE52 Level inversion Timer mode control register 52 TMC52 S R S Q R INV Selector INTTM52 TO52 P132 fX 2...

Page 99: ...ecause TM50 and TM51 are connected with the internal 8 bit bus they are read one at a time Therefore read the value of TM50 and TM51 when used as a 16 bit timer two times for comparison taking changes...

Page 100: ...mpared and when the two values match an interrupt request INTTM50 is generated At this time the interrupt request INTTM51 is also generated Therefore mask INTTM51 when using TM50 and TM51 in the casca...

Page 101: ...Registers 50 to 52 TCL50 to TCL52 TCL5n2 TCL5n1 TCL5n0 Count clock selection 0 0 0 Falling edge of TI5n 0 0 1 Rising edge of TI5n 0 1 0 fX 2 2 25 MHz 0 1 1 fX 23 563 kHz 1 0 0 fX 25 141 kHz 1 0 1 fX...

Page 102: ...operation 2 Be sure to reset bits 3 to 7 to 0 Remarks 1 In the cascade mode the setting of bit TCL53 of the higher timer TM53 is invalid 2 fX System clock oscillation frequency 3 fX 4 5 MHz 3 8 bit t...

Page 103: ...F to 1 1 1 Setting prohibited TMC5n1 Other than PWM mode TMC5n6 0 PWM mode TMC5n6 1 Control of timer F F Selection of active level 0 Disables inversion operation High active 1 Enables inversion operat...

Page 104: ...with a 1 bit or 8 bit memory manipulation instruction Reset input clears TMC53 to 00H Figure 6 8 Format of 8 Bit Timer Mode Control Register 53 TMC53 TCE53 Control of count operation of TM53 0 Clears...

Page 105: ...TM5n is generated The count clock of TM5n can be selected by using bits 0 to 2 TCL5n0 to TCL5n2 of timer clock select register 5n TCL5n For the operation if the value of the compare register is change...

Page 106: ...Operation 1 3 a Basic operation Remarks 1 Interval time N 1 t N 00H to FFH 2 n 0 to 3 t Count clock TM5n count value CR5n TCE5n INTTM5n TO5n Count starts Cleared Cleared 00H 01H N 00H 01H N 00H 01H N...

Page 107: ...iming of Interval Timer Operation 2 3 b When CR5n 00H c When CR5n FFH t Count clock TM5n CR5n TCE5n INTTM5n TO5n Interval time 00H 00H 00H 00H 00H t Count clock TM5n CR5n TCE5n INTTM5n TO5n 01 FE FF 0...

Page 108: ...imer Operation 3 3 d Operation when CR5n is changed M N e Operation when CR5n is changed M N Count clock TM5n CR5n TCE5n INTTM5n TO5n N 00H M N FFH 00H M 00H N M CR5n is changed TM5n overflows because...

Page 109: ...to 0 and an interrupt request signal INTTM5n is generated After that each time the value of TM5n matches the value of CR5n INTTM5n is generated Setting 1 Set each register TCL5n Select the valid edge...

Page 110: ...lock CR5n Compare value TMC5n Mode in which TM5n is cleared and started on match between TM5n and CR5n LVS5n LVR5n Sets Status of Timer Output F F 1 0 High level output 0 1 Low level output Enable inv...

Page 111: ...t Setting 1 Set port latches P130 and P131 to 0 2 Select the active level width using the 8 bit compare register CR5n 3 Select the count clock by using timer clock select register 5n TCL5n 4 Select th...

Page 112: ...E5n INTTM5n TO5n 00H 01H FFH 00H 01H 02H N N 1 FFH 00H 01H 02H M 00H N Active level Inactive level Active level Count clock TM5n CR5n TCE5n INTTM5n TO5n Inactive level Inactive level 01H 00H FFH 00H 0...

Page 113: ...for duration of 2 clocks immediately after overflow of TM5n Caution The value of CR5n can be changed only once in one cycle in the PWM mode Count clock TM5n CR5n TCE5n INTTM5n TO5n CR5n changed N M N...

Page 114: ...TM50 The count clock for TM51 which is cascaded does not have to be set CR50 and CR51 Compare values Each compare value can be set in a range of 00H to FFH TMC50 and TMC51 Select a mode in which the...

Page 115: ...a match signal is generated This is because 8 bit timer counter 5n TM5n is started asynchronously with the count pulse Figure 6 15 Start Timing of 8 Bit Timer Counter Count clock TM50 TM51 CR50 CR51 T...

Page 116: ...ing CR5n Figure 6 16 Timing After Changing Compare Register Value During Timer Count Operation Caution Be sure to clear TCE5n to 0 to set the STOP status except when TI5n input is selected Remarks 1 N...

Page 117: ...c Timer Figure 7 1 Block Diagram of Basic Timer Caution Use the basic timer after setting bit 0 DTSCK0 of the DTS system clock select register DETSCK to 1 after power application and after reset by th...

Page 118: ...ure 7 2 Operation Timing of Basic Timer By polling the interrupt request flag BTMIF0 of this basic timer by software time management can be carried out Note that BTMIF0 is not a Read Reset flag Figure...

Page 119: ...mer mode register WDTM The watchdog timer and interval timer cannot be used simultaneously Figure 8 1 shows a block diagram Figure 8 1 Block Diagram of Watchdog Timer fX 28 RUN Clock input controller...

Page 120: ...rogram Loop Detection Time 212 fX 910 s 213 fX 1 82 ms 214 fX 3 64 ms 215 fX 7 28 ms 216 fX 14 6 ms 217 fX 29 1 ms 218 fX 58 3 ms 220 fX 233 ms Remarks 1 fX System clock oscillation frequency 2 fX 4 5...

Page 121: ...uration Control registers Watchdog timer clock select register WDCS Watchdog timer mode register WDTM Oscillation stabilization time select register OSTS 8 3 Registers Controlling Watchdog Timer The f...

Page 122: ...ars WDCS to 00H Figure 8 2 Format of Watchdog Timer Clock Select Register WDCS Remarks 1 fX System clock oscillation frequency 2 fX 4 5 MHz 0 7 0 6 0 0 4 0 3 2 1 0 FF42H Address WDCS Symbol WDCS2 WDCS...

Page 123: ...ation at a time RUN is set to 1 Caution When RUN is set to 1 so that the watchdog timer is cleared the actual overflow time is up to 0 5 shorter than the time set by the timer clock select register WD...

Page 124: ...on Reset input sets OSTS to 04H Therefore it takes 217 fX to release the STOP mode by RESET input Figure 8 4 Format of Oscillation Stabilization Time Select Register OSTS OSTS2 OSTS1 OSTS0 Selection o...

Page 125: ...r can be cleared and counting started by setting RUN to 1 If RUN is not set to 1 and the inadvertent program loop detection time has elapsed a system reset or a non maskable interrupt request is gener...

Page 126: ...flag WDTPR are validated and the maskable request interrupt INTWDT can be generated Among maskable interrupt requests the INTWDT default has the highest priority The interval timer continues operatin...

Page 127: ...quare wave of the buzzer frequency selected by the clock output select register CKS from the BUZ P37 pin Figures 9 1 and 9 2 show the block diagrams of BEEP0 and BUZ Figure 9 1 Block Diagram of BEEP0...

Page 128: ...P clock select register 0 BEEPCL0 1 BEEP clock select register 0 BEEPCL0 This register selects the frequency of the buzzer output BEEPCL0 is set with a 1 bit or 8 bit memory manipulation instruction R...

Page 129: ...fX 212 1 10 kHz 1 1 fX 213 549 Hz Remarks 1 fX System clock frequency 2 fX 4 5 MHz 9 4 Operation of Buzzer Output Controllers The buzzer frequency is output by the following procedure 1 BEEP0 1 Select...

Page 130: ...and carry out A D conversion When A D conversion is complete the next A D conversion is started immediately Each time an A D conversion operation ends an interrupt request INTAD3 is generated 10 2 Co...

Page 131: ...Successive approximation register SAR A D conversion result register 3 ADCR3 Controller Controller VDD GND ADCS3 INTAD3 PFEN3 ADCS3 ADS33 ADS32 ADS31 ADS30 0 FR32 FR31 FR30 0 0 0 PFCM3 PFHRM3 Power fa...

Page 132: ...tten with an 8 bit memory manipulation instruction 4 Sample hold circuit The sample hold circuit samples each analog input signal sequentially applied from the input circuit and sends it to the voltag...

Page 133: ...clears this register to 00H Figure 10 2 Format of A D Converter Mode Register 3 ADM3 ADCS3 Control of A D conversion operation 0 Stops conversion operation 1 Enables conversion operation FR32 FR31 FR...

Page 134: ...emory manipulation instruction Reset input clears this register to 00H Figure 10 3 Format of Analog Input Channel Specification Register 3 ADS3 ADS33 ADS32 ADS31 ADS30 Specification of analog input ch...

Page 135: ...ection of power fail comparison mode 0 Generates interrupt request INTAD when ADCR3 PFT 1 Generates interrupt request INTAD when ADCR3 PFT Note PFHRM3 Selection of power fail HALT repeat mode 0 Disabl...

Page 136: ...input is greater than 1 2 VDD the MSB of SAR remains set If the input is smaller than 1 2 VDD the MSB is reset 6 Next bit 6 of SAR is automatically set and the operation proceeds to the next comparis...

Page 137: ...ware If a write to ADM3 or ADS3 is performed during an A D conversion operation the conversion operation is initialized and if the ADCS3 bit is set 1 conversion starts again from the beginning After r...

Page 138: ...r ADCR3 0 5 VIN ADCR3 0 5 Remark INT Function which returns integer parts of value in parentheses VIN Analog input voltage VDD VDD pin voltage ADCR3 A D conversion result register 3 ADCR3 value Figure...

Page 139: ...egister 3 PFM3 an interrupt request signal INTAD3 is generated 1 A D conversion operation mode When bit 7 ADCS3 of A D converter mode register 3 ADM3 is set to 1 the A D conversion starts on the volta...

Page 140: ...it 7 ADCS3 of A D converter mode register 3 ADM3 has been set to 1 to enable conversion Caution Reset bit 5 PFHRM3 of power fail comparison mode register 3 PFM3 to 0 Conversion start ADCS3 1 A D conve...

Page 141: ...on matches the condition set by bit 6 PFCM3 of PFM3 an interrupt request signal INTAD3 is generated Figure 10 8 Power Fail Comparison Threshold Value Register 3 PFT3 Remark Bit 7 PFT37 is the MSB and...

Page 142: ...sibility that it will be determined that the comparison condition has matched even if it has not Caution Set power fail comparison threshold value register 3 PFT3 and power fail comparison mode regist...

Page 143: ...er 3 PFM3 has been set to 1 before executing the HALT instruction 3 The first result of the A D conversion A D conversion result and interrupt request is not correct Do not use this result because the...

Page 144: ...has been set to 1 before executing the HALT instruction 3 The first result of the A D conversion A D conversion result and interrupt request is not correct Do not use this result because there is a p...

Page 145: ...above VDD or below GND is input even if within the absolute maximum rating range the conversion value for that channel will be undefined The conversion values of the other channels may also be affecte...

Page 146: ...S3 rewrite and when ADIF is read immediately after the ADM rewrite ADIF may be set despite the fact that the A D conversion for the post change analog input has not ended When the A D conversion is st...

Page 147: ...e executed simultaneously in this mode the processing time of data transfer can be shortened The first bit of the 8 bit data to be transferred is the MSB The 3 wire serial I O mode is useful for conne...

Page 148: ...O shift register 31 SIO31 SI31 P74 SO31 P75 P75 output latch PM75 PM76 SCK31 P76 INTCSI31 fX 2 4 fX 2 5 fX 2 6 P76 output latch 8 Internal bus Selector Selector Selector Selector PM121 PM122 PM125 P1...

Page 149: ...data into serial data and transmit or receive the serial data shift operation in synchronization with a serial clock SIO3n is set with an 8 bit memory manipulation instruction Serial operation is star...

Page 150: ...operation Serial function port functionNote 2 MODE3n Transfer operation mode flag Operating mode Transfer start trigger SO3n output 0 Transmit or transmit receive mode SIO3n write Serial output 1 Rece...

Page 151: ...0 PM124 0 mode set P71 SO30 pin to set P75 SO31 pin to set P121 SO32 pin set P124 SO321 pin output mode output mode to output mode to output mode In receive mode PM70 1 PM74 1 PM120 1 PM123 1 set P70...

Page 152: ...SIE3n Enable disable of SIO3n operation Shift register operation Serial counter Port 0 Disables operation Cleared Port functionNote 1 1 Enables operation Enables count operation Serial function port f...

Page 153: ...nctionNote 2 MODE3n Transfer operation mode flag Operating mode Transfer start trigger SO3n output 0 Transmit or transmit receive mode SIO3n write Serial output 1 Receive only mode SIO3n read Fixed to...

Page 154: ...n set P124 SO321 pin output mode output mode to output mode to output mode In receive mode PM70 1 PM74 1 PM120 1 PM123 1 set P70 SI30 pin to set P74 SI31 pin to set P120 SI32 pin to set P123 SI321 pin...

Page 155: ...the internal serial clock is stopped or SCK3n is high level after transfer of 8 bit serial data Transmit receive mode Transfer is started if SIO3n is written when bit 7 CSIE3n of CSIM3n 1 and bit 2 M...

Page 156: ...upt servicing is possible if a high priority interrupt is generated while a low priority interrupt is being serviced If two or more interrupts with the same priority are simultaneously generated each...

Page 157: ...M0 Generation of basic timer match signal 0014H 9 INTAD3 End of conversion by A D converter 0016H 10 INTCSI32 End of transfer by serial interface SIO32 0018H 11 INTCSI30 End of transfer by serial inte...

Page 158: ...errupt Internal bus Priority controller Vector table address generator Standby release signal Interrupt request Internal bus IE PR ISP MK IF Interrupt request Priority controller Vector table address...

Page 159: ...onfiguration of Interrupt Function 2 2 D Software interrupt Remark IF Interrupt request flag IE Interrupt enable flag ISP Inservice priority flag MK Interrupt mask flag PR Priority specification flag...

Page 160: ...k flags and priority specification flags corresponding to interrupt request sources Table 12 2 Various Flags Corresponding to Interrupt Request Sources Interrupt Source Interrupt Request Flag Interrup...

Page 161: ...uest Flag Registers IF0L IF0H IF Interrupt request flag 0 No interrupt request signal 1 Interrupt request signal is generated Interrupt request state Cautions 1 WDTIF flag is R W enabled only when a w...

Page 162: ...Registers MK0L MK0H MK Interrupt servicing control 0 Interrupt servicing enabled 1 Interrupt servicing disabled Cautions 1 If the WDTMK flag is read when the watchdog timer is used in watchdog timer...

Page 163: ...PR0 use a 16 bit memory manipulation instruction for the setting Reset input sets these registers to FFH Figure 12 4 Format of Priority Specification Flag Registers PR0L PR0H PR Priority level select...

Page 164: ...nstructions Reset input clears these registers to 00H Figure 12 5 Format of External Interrupt Rising Edge Enable Register EGP and External Interrupt Falling Edge Enable Register EGN EGPn EGNn INTPn p...

Page 165: ...d the IE flag is reset to 0 When a maskable interrupt request is acknowledged the contents of the priority specification flag of the acknowledged interrupt are transferred to the ISP flag The acknowle...

Page 166: ...ranched A new non maskable interrupt request generated during execution of a non maskable interrupt servicing program is acknowledged after the current execution of the non maskable interrupt servicin...

Page 167: ...ment Timing WDTM4 1 with watchdog timer mode selected Overflow in WDT WDTM3 0 with non maskable interrupt request selected Interrupt request generation WDT interrupt servicing Interrupt control regist...

Page 168: ...on b If two non maskable interrupt requests are generated during non maskable interrupt servicing program execution Main routine NMI request Execution of one instruction NMI request NMI request is hel...

Page 169: ...Note If an interrupt request is generated just before a divide instruction the wait time is maximized Remark 1 clock fCPU CPU clock If two or more maskable interrupt requests are generated simultaneou...

Page 170: ...d or interrupt with low priority serviced Start IF 1 MK 0 PR 0 Any simultaneously generated PR 0 interrupt requests Any simultaneously generated high priority interrupt requests IE 1 ISP 1 Vectored in...

Page 171: ...cknowledgement Timing Maximum Time 1 fCPU Remark 1 clock fCPU CPU clock Instruction Instruction PSW and PC save jump to interrupt servicing 6 clocks Interrupt servicing program 8 clocks 7 clocks CPU p...

Page 172: ...ot be disabled If a software interrupt request is acknowledged it is saved to the stack the program status word PSW and program counter PC in that order the IE flag is reset to 0 and the contents of t...

Page 173: ...t cannot be acknowledged and serviced An interrupt that is not acknowledged and serviced because it is disabled or it has a low priority is held pending This interrupt is acknowledged after servicing...

Page 174: ...interrupt is enabled Interrupt request INTyy that is generated while interrupt INTxx is being serviced is not acknowledged because its priority is lower than that of INTxx and therefore multiple inte...

Page 175: ...abled EI instruction is not issued in interrupt servicing INTxx interrupt request INTyy is not acknowledged and multiple interrupt does not occur The INTyy request is held pending and is acknowledged...

Page 176: ...on Because the IE flag is cleared to 0 by the software interrupt caused by execution of the BRK instruction a maskable interrupt request is not acknowledged even if it occurs while the BRK instruction...

Page 177: ...ecified by bit 3 VCOHDMD of PLLMD 3 Pulse swallow VHF mode The VCOH pin is used The VCOL pin is set in the status specified by bit 2 VCOLDMD of PLLMD 4 VCOL and VCOH pin disable The VCOL and VCOH pins...

Page 178: ...Pin and Division Value Division Mode Pin Used Value That Can Be Set Direct division MF VCOL 32 to 212 1 Pulse swallow HF VCOL 1024 to 217 1 Pulse swallow VHF VCOH 1024 to 217 1 Caution For the freque...

Page 179: ...PLL unlock F F judge register PLLUL PLL data transfer register PLLNS Figure 13 1 Block Diagram of PLL Frequency Synthesizer Note External circuit Internal bus Internal bus PLL mode select register PLL...

Page 180: ...mplifiers of the respective pins 3 Programmable divider The programmable divider consists of two modulus prescalers a programmable counter 12 bits a swallow counter 5 bits and a division mode select s...

Page 181: ...HALT mode it holds the value immediately before the HALT mode was set Figure 13 2 Format of PLL Mode Select Register PLLMD VCOH Selection of disable status of VCOH pin DMD 0 Connected to pull down re...

Page 182: ...Format of PLL Reference Mode Register PLLRF PLLRF3 PLLRF2 PLLRF1 PLLRF0 Setting of reference frequency fr of PLL frequency synthesizer 0 0 0 0 50 kHz 0 0 0 1 25 kHz 0 0 1 0 12 5 kHz 0 0 1 1 9 kHz 0 1...

Page 183: ...s set Figure 13 4 Format of PLL Unlock F F Judge Register PLLUL PLLUL0 Detection of status of unlock F F 0 Unlock F F 0 PLL lock status 1 Unlock F F 1 PLL unlock status Notes 1 The value of bit 0 PLLU...

Page 184: ...register is 00H after reset and in the STOP mode In the HALT mode this register holds the previous value immediately before the HALT mode is set Figure 13 5 Format of PLL Data Transfer Register PLLNS...

Page 185: ...grammable counter and swallow counter frequency division is performed in the selected division mode according to the status of bit 0 PLLNS0 of the PLL data transfer register Figure 13 6 shows the conf...

Page 186: ...r than the reference frequency fr the up request signal is output If fN is higher than fr the down request signal is output Figure 13 9 shows the relation among reference frequency fr divided frequenc...

Page 187: ...result of the up request UP or down request DW signal from the phase comparator DET from the error out pins EO0 and EO1 pins Table 13 3 shows the output signals The EO0 and EO1 pins are of voltage dri...

Page 188: ...tput Signal Relationship Between Divided Frequency Error Out Output Signal fN and Reference Frequency fr When fr fN Low level When fr fN High level When fr fN Floating high impedance Figure 13 10 Conf...

Page 189: ...eference frequency 13 4 2 Operation to set N value of PLL frequency synthesizer The division value N value is set to the programmable counter 12 bits and swallow counter 5 bits by the PLL data registe...

Page 190: ...uency of VCOL pin fr Reference frequency b Example of setting PLL data register An example of setting the PLL data register to receive broadcasting stations in the following SW band is shown below Rec...

Page 191: ...shifting the N value resulting from calculation 1 bit to the right If the N value is calculated as follows with the least significant bit of the N value in PLLSCN fixed to 0 the result of the calcula...

Page 192: ...10 7 2214 decimal fr 0 05 08A6H hexadecimal Because the least significant bit of the division value N must be set to the PLL data register 0 PLLR0 data must be set by shifting the value calculated by...

Page 193: ...e of half the N value is set to the higher 16 bits of the PLL data register PLLR by shifting the N value resulting from calculation 1 bit to the right If the N value is calculated as follows with the...

Page 194: ...us set in bit 3 VCOHDMD and bit 2 VCOLDMD of PLLMD Programmable divider Division stops Reference frequency generator Output stops Phase comparator Output stops EO0 and EO1 pin High impedance PLL mode...

Page 195: ...of the frequency counter is stored in the IF counter register For the range of the frequency that can be input to the FMIFC and AMIFC pins refer to CHAPTER 19 ELECTRICAL SPECIFICATIONS 14 2 Configurat...

Page 196: ...he IF counter register block is a 16 bit register that counts up the frequency input in the set gate time The count value is stored to the IF counter register IFCR When the count value reaches FFFFH t...

Page 197: ...truction The value of this register is reset to 00H after reset or in the STOP mode In the HALT mode this register holds the value immediately before the HALT mode is set Figure 14 2 Format of IF Coun...

Page 198: ...judge register IFCJG This register detects opening closing of the gate of the frequency counter The value of this register is reset to 00H after reset and in the STOP mode In the HALT mode this regis...

Page 199: ...T has been set to 1 When the gate time has elapsed bit 0 IFCJG0 of the IF counter gate judge register IFCJG is automatically cleared to 0 If it is specified that the gate be open however IFCJG0 is not...

Page 200: ...register IFCMD H L Internal 1 kHz IFCJG0 Sets IFCST IFCJG0 is automatically set at this point Counting starts Gate is opened at this point Clears IFCJG0 Counting ends if gate time is 8 ms Gate time 8...

Page 201: ...ure that sufficient wait time elapses after a pin has been selected and before counting is started IFCST 1 Figure 14 7 Frequency Counter Input Pin Circuit 2 Notes in HALT mode The FMIFC and AMIFC pins...

Page 202: ...ounter is created by dividing 4 5 MHz Therefore if 4 5 MHz is shifted x ppm the gate time is also shifted x ppm 2 Count error The frequency counter counts the frequency at the rising edge of the input...

Page 203: ...e considerably decreased Data memory low voltage hold down to VDD 2 2 V is possible Thus the STOP mode is effective to hold data memory contents with ultra low current consumption If the supply voltag...

Page 204: ...tion frequency fX 4 5 MHz Caution The wait time when the STOP mode is released does not include the time required for the clock oscillation to start after the STOP mode has been released see a in the...

Page 205: ...ter Retains operation performed when HALT mode is set However comparison cannot be performed correctly in A D conversion operation mode In power fail comparison mode operation is as follows depending...

Page 206: ...eneration Remarks 1 The broken lines indicate the case when the interrupt request that released the standby status is acknowledged 2 Wait time will be as follows When vectored interrupt servicing is c...

Page 207: ...tion After HALT Mode Release Release Source MK PR IE ISP Operation Maskable interrupt 0 0 0 Next address instruction execution request 0 0 1 Interrupt servicing execution 0 1 0 1 Next address instruct...

Page 208: ...s the STOP mode is reset to the HALT mode immediately after execution of the STOP instruction After the wait set using the oscillation stabilization time select register OSTS the operation mode is set...

Page 209: ...t is generated the STOP mode is released If interrupt request acknowledgement is enabled after the lapse of oscillation stabilization time vectored interrupt servicing is carried out If interrupt requ...

Page 210: ...MHz Table 15 4 Operation After STOP Mode Release Release Source MK PR IE ISP Operation Maskable interrupt request 0 0 0 Next address instruction execution 0 0 1 Interrupt servicing execution 0 1 0 1 N...

Page 211: ...tion stabilization time immediately after the effect of reset has been cleared each pin goes into a high impedance state however the P130 to P132 pins become low level and the VCOH and VCOL pins are p...

Page 212: ...n the STOP mode is released by RESET input the STOP mode register contents are held during reset input However the I O port pin becomes high impedance Output dedicated port pin P130 to P132 becomes lo...

Page 213: ...rmal operation Reset period oscillation stop Oscillation stabilization time wait Normal operation reset processing Output port pin P130 to P132 RESET Internal reset signal I O port pin Delay Delay Hig...

Page 214: ...Timing of Reset due to Watchdog Timer Overflow X1 Normal operation Watchdog timer overflow Internal reset signal I O port pin Reset period oscillation stop Oscillation stabilization time wait Normal o...

Page 215: ...P130 to P132 4 5 V 3 5 V 2 2 V L High impedance Normal operation I O port pin Reset period oscillation stop Stop status oscillation stop Oscillation stabilization time wait Normal operation reset pro...

Page 216: ...registers 50 to 53 CR50 to CR53 Undefined Clock select registers 50 to 53 TCL50 to TCL53 00H Mode control registers 50 to 53 TMC50 to TMC53 00H Watchdog timer Clock select register WDCS 00H Mode regis...

Page 217: ...flag registers PR0L and PR0H FFH External interrupt rising edge enable register EGP 00H External interrupt falling edge enable register EGN 00H PLL frequency synthesizer PLL mode select register PLLMD...

Page 218: ...detecting this POCM after reset by power on clear has been cleared after program execution has been started from address 0000H Figure 16 5 Format of POC Status Register POCS POCM Detection of power o...

Page 219: ...wever that this 4 5 V voltage detection function does not cause internal reset Figure 16 6 Format of POC Status Register POCS VM45 Detection of voltage level of VDD pin 0 Does not detect if VDD pin is...

Page 220: ...78054 are shown in Table 17 1 Table 17 1 Differences Between PD178F054 and Mask ROM Versions Item PD178F054 PD178053 178054 Internal memory ROM structure Flash memory Mask ROM ROM capacity 32 KB PD178...

Page 221: ...e to set IMS to C6H or C8H Figure 17 1 Format of Memory Size Switching Register IMS RAM2 RAM1 RAM0 Selection of internal high speed RAM capacity 0 1 0 512 bytes 1 1 0 1024 bytes Other than above Setti...

Page 222: ...struction Reset input sets this register to 0CH Caution Do not set a value other than the initial value Figure 17 2 Format of Internal Expansion RAM Size Switching Register IXS IXRAM4 IXRAM3 IXRAM2 IX...

Page 223: ...emory is written by using Flashpro III and by means of serial communication Select a communication mode from those listed in Table 17 4 To select a communication mode the format shown in Figure 17 3 i...

Page 224: ...e Erases all memory contents Batch blank check Checks erased status of entire memory Data write Writes data to flash memory starting from write start address and based on number of data bytes to be wr...

Page 225: ...LK On Target Board In Flashpro On Target Board 4 1943 MHz SIO CLK 1 0 MHz In Flashpro 4 0 MHz SIO CLK 1 0 MHz 3 wire serial I O SIO31 COMM PORT SIO ch1 1 CPU CLK On Target Board In Flashpro On Target...

Page 226: ...J2V0UD CHAPTER 18 INSTRUCTION SET This chapter describes each instruction set of the PD178054 Subseries as list table For details of its operation and operation code refer to the 78K 0 Series User s M...

Page 227: ...tion names X A C etc or absolute names names in parentheses in the table below R0 R1 R2 etc can be used Table 18 1 Operand Symbols and Descriptions Symbol Description r X R0 A R1 C R2 B R3 E R4 D R5 L...

Page 228: ...C Auxiliary carry flag Z Zero flag RBS Register bank select flag IE Interrupt request enable flag NMIS Non maskable interrupt servicing flag Memory contents indicated by address or register contents i...

Page 229: ...A 1 4 5 DE A A HL 1 4 5 A HL HL A 1 4 5 HL A A HL byte 2 8 9 A HL byte HL byte A 2 8 9 HL byte A A HL B 1 6 7 A HL B HL B A 1 6 7 HL B A A HL C 1 6 7 A HL C HL C A 1 6 7 HL C A XCH A r Note 3 1 2 A r...

Page 230: ...2 4 5 A CY A saddr A addr16 3 8 9 A CY A addr16 A HL 1 4 5 A CY A HL A HL byte 2 8 9 A CY A HL byte A HL B 2 8 9 A CY A HL B A HL C 2 8 9 A CY A HL C ADDC A byte 2 4 A CY A byte CY saddr byte 3 6 8 sa...

Page 231: ...CY A saddr 2 4 5 A CY A saddr CY A addr16 3 8 9 A CY A addr16 CY A HL 1 4 5 A CY A HL CY A HL byte 2 8 9 A CY A HL byte CY A HL B 2 8 9 A CY A HL B CY A HL C 2 8 9 A CY A HL C CY AND A byte 2 4 A A by...

Page 232: ...r A A saddr 2 4 5 A A saddr A addr16 3 8 9 A A addr16 A HL 1 4 5 A A HL A HL byte 2 8 9 A A HL byte A HL B 2 8 9 A A HL B A HL C 2 8 9 A A HL C CMP A byte 2 4 A byte saddr byte 3 6 8 saddr byte A r N...

Page 233: ...ime ROR4 HL 2 10 12 A3 0 HL 3 0 HL 7 4 A3 0 HL 3 0 HL 7 4 ROL4 HL 2 10 12 A3 0 HL 7 4 HL 3 0 A3 0 HL 7 4 HL 3 0 BCD ADJBA 2 4 Decimal Adjust Accumulator after adjust Addition ADJBS 2 4 Decimal Adjust...

Page 234: ...bit 3 7 CY CY sfr bit CY A bit 2 4 CY CY A bit CY PSW bit 3 7 CY CY PSW bit CY HL bit 2 6 7 CY CY HL bit SET1 saddr bit 2 4 6 saddr bit 1 sfr bit 3 8 sfr bit 1 A bit 2 4 A bit 1 PSW bit 2 6 PSW bit 1...

Page 235: ...P SP 3 Stack PUSH PSW 1 2 SP 1 PSW SP SP 1 manipulate rp 1 4 SP 1 rpH SP 2 rpL SP SP 2 POP PSW 1 2 PSW SP SP SP 1 R R R rp 1 4 rpH SP 1 rpL SP SP SP 2 MOVW SP word 4 10 SP word SP AX 2 8 SP AX AX SP 2...

Page 236: ...en reset saddr bit sfr bit addr16 4 12 PC PC 4 jdisp8 if sfr bit 1 then reset sfr bit A bit addr16 3 8 PC PC 3 jdisp8 if A bit 1 then reset A bit PSW bit addr16 4 12 PC PC 4 jdisp8 if PSW bit 1 then r...

Page 237: ...C A ADD MOV MOV MOV MOV MOV MOV MOV MOV ROR ADDC XCH XCH XCH XCH XCH XCH XCH ROL SUB ADD ADD ADD ADD ADD RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC AND SUB SUB SUB SUB SUB OR SUBC SUBC SUBC SUBC SUBC XOR...

Page 238: ...MOVW addr16 MOVW SP MOVW MOVW Note Only when rp BC DE HL 3 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF BTCLR 2nd Operand A bit sfr bit saddr bit PSW bit HL bit CY addr16 Non...

Page 239: ...nstructions CALL CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ 2nd Operand AX addr16 addr11 addr5 addr16 1st Operand Basic instruction BR CALL CALLF CALLT BR BR BC BNC BZ BNZ Compound BT instruction B...

Page 240: ...normal operation mode 40 to 85 C During flash memory programming 10 to 40 PD178F054 only Storage temperature Tstg 55 to 125 C Notes 1 Keep the voltage at VDDPORT and VDDPLL same as that at the VDD pin...

Page 241: ...7 0 0 2 VDD V P120 P122 P123 P125 RESET Output voltage high VOH1 P00 to P06 P30 to P37 4 5 V VDD 5 5 V VDD 1 0 V P40 to P47 P50 to P57 IOH 1 mA P60 to P67 P70 to P77 3 5 V VDD 4 5 V VDD 0 5 V P120 to...

Page 242: ...78054 Sine wave input to X1 pin PD178F054 5 0 18 mA At fX 4 5 MHz VIN VDD IDD2 In HALT mode with PLL PD178053 0 2 0 8 mA stopped PD178054 Sine wave input to X1 pin PD178F054 0 3 0 8 mA At fX 4 5 MHz V...

Page 243: ...ve input to VCOH pin At fIN 160 MHz VIN 0 15 VP P AC Characteristics 1 Basic operation TA 40 to 85 C VDD 3 5 to 5 5 V Parameter Symbol Conditions MIN TYP MAX Unit Cycle time TCY fX 4 5 MHz 0 44 7 11 s...

Page 244: ...from SCK3 tKSI1 400 ns Output delay time from SCK3 to tKSO1 C 100 pF Note 300 ns SO3 Note C is the load capacitance of SCK3 and SO3 output line b 3 wire serial I O mode SCK3 external clock input Para...

Page 245: ...NS User s Manual U15104EJ2V0UD AC Timing Test Point Excluding X1 Input TI Timing Interrupt Input Timing RESET Input Timing 0 8 VDD 0 2 VDD 0 8 VDD 0 2 VDD Test points 1 fTI5 tTIL5 tTIH5 TI50 TI51 TI52...

Page 246: ...HAPTER 19 ELECTRICAL SPECIFICATIONS User s Manual U15104EJ2V0UD Serial Transfer Timing 3 wire serial I O mode Remark m 1 2 n 2 tKCYm tKLm tKHm SCK3 SI3 SO3 tSIKm tKSIm tKSOm Input data Output data tRn...

Page 247: ...C VDD 4 5 to 5 5 V Parameter Symbol Conditions MIN TYP MAX Unit Operating frequency fIN1 VCOL pin MF mode sine wave input VIN 0 15 VP P 0 5 3 0 MHz fIN2 VCOL pin HF mode sine wave input VIN 0 15 VP P...

Page 248: ...erwrite Delete and write are counted as one cycle 20 times VPP power supply voltage VPP0 In normal mode 0 0 2 VDD V VPP1 During flash memory programming 9 7 10 0 10 3 V Note Port current including cur...

Page 249: ...249 CHAPTER 19 ELECTRICAL SPECIFICATIONS User s Manual U15104EJ2V0UD Flash Write Mode Setting Timing VDD VDD 0 V VDD RESET input 0 V VPPH VPPL VPP VPP tRFCF tPSRON tPSRRF tDRPSR tCH tCL tCOUNT...

Page 250: ...position T P at maximum material condition ITEM MILLIMETERS A B D G 17 20 0 20 14 00 0 20 0 13 0 825 I 17 20 0 20 J C 14 00 0 20 H 0 32 0 06 0 65 T P K 1 60 0 20 P 1 40 0 10 Q 0 125 0 075 L 0 80 0 20...

Page 251: ...tic QFP 14 14 PD178054GC 8BT 80 pin plastic QFP 14 14 PD178F054GC 8BT 80 pin plastic QFP 14 14 Soldering Soldering Conditions Recommended Method Condition Symbol Infrared reflow Package peak temperatu...

Page 252: ...onfiguration example of the tools Support for PC98 NX series Unless otherwise specified products supported by IBM PC ATTM compatibles can be used for PC98 NX series computers When using PC98 NX series...

Page 253: ...ware Assembler package C compiler package Device file C compiler source fileNote 1 Debugging Software Integrated debugger System simulator Host Machine PC or EWS Interface adapter PC card interface et...

Page 254: ...tegrated debugger Device file Embedded Software Real time OS OS Debugging Tool Assembler package C compiler package C library source file Device file Language Processing Software Flash memory write ad...

Page 255: ...ombination with an optical device file DF178054 Precaution when using RA78K0 in PC environment This assembler package is a DOS based application It can also be used in Windows however by using the Pro...

Page 256: ...4 inch CGMT A 3 Control Software Project manager This is control software designed to enable efficient user program development in the Windows environment All operations used in development of a user...

Page 257: ...extending the IE 78K0 NS functions and is used connected to the IE 78K0 NS With the addition of this board the addition of a coverage function enhancement of tracer and timer functions and other such...

Page 258: ...ng the PC 9800 series computer except notebook type as the IE 78001 R A host machine C bus compatible This adapter is required when using the IBM PC AT compatible computers as the IE 78001 R A host ma...

Page 259: ...ed debugger ID78K0 NS and ID78K0 are Windows based software supporting in circuit emulators ID78K0 Supports in circuit emulator IE 78001 R A IE 78K0 NS and IE 78K0 NS A ID78K0 NS Supports in circuit e...

Page 260: ...using in Windows Part number S RX78013 Caution When purchasing the RX78K0 fill in the purchase application form in advance and sign the user agreement Remark and in the part number differ depending o...

Page 261: ...that in circuit emulator can operate as an equivalent to the IE 78001 R A by replacing its internal break board with the IE 78001 R BK Table A 1 System Upgrade Method from Former In circuit Emulator f...

Page 262: ...e Drawing for Reference Only A F D 1 No 1 pin index E EV 9200GC 80 B C M N O L K S R Q P I H J G EV 9200GC 80 G1E ITEM MILLIMETERS INCHES A B C D E F G H I J K L M N O P Q R S 18 0 14 4 14 4 18 0 4 C...

Page 263: ...0 0 05 6 0 0 05 0 35 0 02 2 36 0 03 2 3 1 57 0 03 0 776 0 591 0 591 0 776 0 236 0 236 0 014 0 093 0 091 0 062 0 65 0 02 19 12 35 0 05 0 65 0 02 19 12 35 0 05 0 001 0 002 0 003 0 002 0 001 0 002 0 003...

Page 264: ...n result register 3 ADCR3 132 146 A D converter mode register 3 ADM3 133 Analog input channel specification register 3 ADS3 134 B BEEP clock select register 0 BEEPCL0 128 C Clock output select registe...

Page 265: ...82 Port mode register 0 PM0 83 Port mode register 3 PM3 83 Port mode register 4 PM4 83 Port mode register 5 PM5 83 Port mode register 6 PM6 83 Port mode register 7 PM7 83 Port mode register 12 PM12 8...

Page 266: ...UD T Timer clock select register 50 TCL50 101 Timer clock select register 51 TCL51 101 Timer clock select register 52 TCL52 101 Timer clock select register 53 TCL53 102 W Watchdog timer clock select r...

Page 267: ...31 150 CSIM32 Serial operating mode register 32 150 D DTSCK DTS system clock select register 88 E EGN External interrupt falling edge enable register 164 EGP External interrupt rising edge enable reg...

Page 268: ...e register 6 83 PM7 Port mode register 7 83 PM12 Port mode register 12 83 POCS POC status register 218 219 PR0H Priority specification flag register 0H 163 PR0L Priority specification flag register 0L...

Page 269: ...269 APPENDIX B REGISTER INDEX User s Manual U15104EJ2V0UD W WDCS Watchdog timer clock select register 122 WDTM Watchdog timer mode register 123...

Page 270: ...3 Port Mode Register and Output Latch CHAPTER 4 Settings When Using Alternate Functions PORT FUNCTIONS Modification of description in 3 Oscillation stabilization time select register CHAPTER 8 OSTS i...

Page 271: ...886 2 2719 5951 Address North America NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Market Communication Dept Fax 49 211 6503 2...

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