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CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 50 TO 53
User’s Manual U15104EJ2V0UD
(2) 8-bit compare registers 50, 51, 52, and 53 (CR50 to CR53)
The value set to CR5n is always compared with the value of 8-bit timer counter 5n (TM5n). When the value
of a compare register matches the count value of the corresponding counter, an interrupt request (INTTM5n)
is generated (in a mode other than PWM mode).
If TM50 and TM51 are cascaded and used as a 16-bit timer, CR50 and CR51 operate together as a 16-bit
compare register. The 16-bit counter value and 16-bit compare register value are compared, and when the
two values match, an interrupt request (INTTM50) is generated. At this time, the interrupt request INTTM51
is also generated. Therefore, mask INTTM51 when using TM50 and TM51 in the cascade mode.
If TM52 and TM53 are cascaded and used as a 16-bit timer, CR52 and CR53 operate together as a 16-bit
compare register. The 16-bit counter value and 16-bit compare register value are compared, and when the
two values match, an interrupt request (INTTM52) is generated. At this time, the interrupt request INTTM53
is also generated. Therefore, mask INTTM53 when using TM52 and TM53 in the cascade mode.
Caution
When TM50 and TM51 or TM52 and TM53 are cascaded, be sure to change the CR5n setting
value after stopping the timer operation of cascaded TM5n.
Remark
n = 0 to 3
