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CHAPTER 3 CPU ARCHITECTURE
User’s Manual U15104EJ2V0UD
(3)
µ
PD178F054
Set the value of the memory size switching register (IMS) to the value corresponding to that of the mask ROM
versions. The initial value is CFH.
Figure 3-3. Memory Map of
µ
PD178F054
F F F F H
0 0 0 0 H
F F 0 0 H
F E F F H
F E E 0 H
F E D F H
F B 0 0 H
F A F F H
8 0 0 0 H
7 F F F H
0 0 0 0 H
7 F F F H
1 0 0 0 H
0 F F F H
0 8 0 0 H
0 7 F F H
0 0 8 0 H
0 0 7 F H
0 0 4 0 H
0 0 3 F H
Special function
registers (SFRs)
256
×
8 bits
Internal high-speed RAM
1024
×
8 bits
General-purpose registers
32
×
8 bits
Reserved
Flash memory
32768
×
8 bits
Program
memory
space
Data memory
space
Vector table area
CALLT table area
Program area
CALLF entry area
Program area
