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**

DRCS_Serial “DRCS_ser_fft.m” is the script
intended for analysis of the DRCS 24-bit serial out-
put data. Fsample is set to a default of 52e6/192
which is the GSM standard output rate of
270.833KS/s. The “search’ option is enabled;
therefore, excluding the DC bins, the peak FFT bin
is assumed to be the input fundamental. A default 4-
term data window is used. 

**

DRCS_Debug “DRCS_par_fft.m” is the script
intended for analysis of the DRCS 16-20 bit parallel
debug data. The hardware setting will determine the
actual Fsample variable needed. The data is always
placed within a 24-bit word with MSB justification.
The default Fsample is set to the assumed clock
frequency of 52MHz with no decimation. If a debug
port is selected which has decimated data, the
Fsample variable will require an appropriate adjust-
ment. Carefully edit and save the new value into the
script file. The original file can be recovered from the
CDROM. 

** 

14-bit FFT “b14_FFT.m” is the script intended for

data analysis in conjunction with the CLC5958 Eval-
uation Board. All the FFT routines can be run with a
rectangular window by setting the variable to “0”.
Setting the “Dither” variable excludes a lower portion
of the spectrum from the FFT analysis and is
intended to be used in conjunction with a base-band
dither signal being present at the ADC analog input. 

** 

12-bit FFT “b12_FFT.m” is the script intended for

data analysis in conjunction with the CLC5956
Evaluation Boards. 

** 

DNL_INL “dnl_inl.m” - is the script intended for data
analysis of the histogram data file generated by the
Data Capture Board. The data file has a fixed 2^15
length (i.e. the number of histogram bins). SW1 on
the Capture Board is set to LSB justify the ADC data
within the 2^15 bins. 12-18 bit histograms are
supported. This Matlab script automatically scales
to the data source. In addition to the graphic plots,
the routine gives the number of samples, input
amplitude (dBFS of ADC), and data DC offset (in
LSBs). See the Data Capture Board User Manual
for more info. 

**

Plot_Data this script is contained within
“analysis_menu.m”. It simply clears the figure, loads
the data file from the default location, and plots the
new data. 

No data manipulation occurs. If the user

wishes to view offset binary formatted data which
has been normalized to ±1, he should first run the
appropriate FFT analysis, then clear the plot figure
(use 

“clf“at Matlab command line) and plot the

variable 

“u” (use “plot(u,’.’)” at Matlab command line). 

Summary of Contents for CLC-CAPT-PCASM

Page 1: ...s Receiver Transmitter an oscillator and a level translator IC The captured data is stored in either three 32K x 8 static RAMs organized into 24 bit words or in a FIFO containing 32K 18 bit words LEDs provide a visual indication of activity DIP switches and a jumper configure several capture functions Section II Capturing Data from ADC Evaluation Boards Getting Started To use the Data Capture boar...

Page 2: ...on board An amplitude of 10 to 16dBm is recommended Here again the HP 8644B is a good choice Software 1 National Semiconductor Software All of the required software is provided on a CD ROM To install the software now insert the CD ROM into your computer and follow the directions The default installation copies all of the files to a directory called c nsc The data capture software is called capture...

Page 3: ...ion board pin 20B The third jumper block J2 is unused Data Capture Board Block Diagram DIP Switches Five of the eight DIP switches are used to configure several capture functions as follows DIP switch 1 This DIP switch specifies whether a Diversity Receiver Evaluation Board or an ADC Evaluation Board is attached to the Data Capture Board ON ADC Evaluation Board is attached Captured data is aligned...

Page 4: ...he Data Capture Board is powered up and the FPGA is initialized it is on to indicate that the board is ready After all the SRAM data has been output it is off LED 2 This LED is on when captured data is available to be output to the serial port After all the data has been output it is off LED 6 This LED is connected to the clock signal selected by DIP switch 1 When the clock is toggling it will be ...

Page 5: ...you start with the default file name and location shown Click on Default and then on OK If you do not have a C temp directory please make one The reason for this is that the Matlab script files for data analysis look auto matically for the file C temp data dat If you wish to store the data elsewhere you will need to modify the Matlab m files to look for your data file in a different loca tion Obvi...

Page 6: ... configuration menu Select Histogram Debug as shown above and click on OK When the data capture control panel returns you can verify your capture settings by positioning the mouse over the progress bar You will see the following display When you press Start now the SRAM will be cleared and then the board will count the number of times each code is output When any count reaches the number that you ...

Page 7: ... and Capture Board combination require 5V at 1A 4 An IBM Compatible Personal Computer running Windows 95 Windows 98 or Windows NT with a serial port capable of 115 200 baud 5 Serial data cable to connect the data capture board to the PC 6 Low noise filtered IF Signal source for analog input to DRCS 7 OPTIONAL Low jitter clock source 10 16dBm sinewave if DRCS crystal oscillator is removed Software ...

Page 8: ...ion The SRAM is useful for displaying time records of data or collecting contiguous blocks of slower data that have been decimated by the CLC5902 DDC The SRAM is the memory element used for the board s hardwired histogram data generation Capture Board Hardware Configuration Options for DRCS data capture Place the WCLK FIFO write clock jumper in the PIN 120 position the VCORE should be in the 5V po...

Page 9: ...arted Next is a discussion of the Mode functions and the related sub functions MODES There are four primary modes in which to run the data capture system each with its own associated options 1 Capture mode configures the Capture Board for data reception from the DRCS evaluation board Both serial and the parallel output ports can be used as the source data path a The 24 Bits option captures serial ...

Page 10: ...ata source The DRCS Debug data will be displayed at the 15 bit resolution limit this is also the case for the DRCS 24 bit Serial Out data and the histogram will be centered about 16 384 assuming there is no intentional DC offset The following figure displays the sine wave histo gram data of the DRCS output generated by the Capture Board at an input frequency of 150MHz and 16dBm in amplitude using ...

Page 11: ...nditions The main portion of the noise power is contained in the carrier s immediate sidebands 5KHz Another point of interest is that there are several spectral lines about 75dBFS and 25KHz on either side of the fundamental These have been traced to the ground loop created by the PC serial interface Both serial interface cables were connected while this data was being collected Removing the cable ...

Page 12: ...e variable to 0 Setting the Dither variable excludes a lower portion of the spectrum from the FFT analysis and is intended to be used in conjunction with a base band dither signal being present at the ADC analog input 12 bit FFT b12_FFT m is the script intended for data analysis in conjunction with the CLC5956 Evaluation Boards DNL_INL dnl_inl m is the script intended for data analysis of the hist...

Page 13: ...13 http www national com CLC CAPT PCASM Evaluation Board Layer 1 CLC CAPT PCASM Evaluation Board Layer 2 CLC CAPT PCASM Evaluation Board Layer 3 CLC CAPT PCASM Evaluation Board Layer 4 ...

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Page 15: ...to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd Japan Ltd 1111 West Bardin Road Fax 49 0 180 530 85 86 13th Floor Straight Block Tel 81 043 299 2309 Arlington TX 76017 E mail europe supp...

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