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#4 & #5 as indicated in the Histogram Max Target
table. Due to a high data resolution and relatively
slow data rate, a relatively long period of time is
required for generating histogram data from the
DRCS with high decimation values in the DDC.
Under some circumstances, the serial PC interface
will time out. The program detects this condition and
queries the user to continue. Click 

“Yes” to continue

and wait for the Progress Bar to run to completion.
Be patient, it could take several minutes depending
on the input amplitude and DDC decimation value
and Histogram Target Value. The last mode
description, 

Debug Histogram, provides further

description of the output file generated by the hard-
wired histogram generator. 

Histogram Target Table

3.

Capture Debug mode configures the Capture
Board to collect data from the DRCS evaluation
board’s 20-bit parallel debug data bus. Because the
FIFO memory is limited to 18 bits, the user is given
the option to collect the full data width in the SRAM
by selecting the 

20 Bits menu button. As previously

mentioned, parallel data which runs at the full clock
speed (i.e. 

Mixer Out at Debug port) gets deci-

mated by 6 due to the fact that the FPGA requires
multiple clock strobes to address and write data into
the SRAM. Choosing the 

Upper 18 Bits option will

use the high speed FIFO for the memory element
and collect a contiguous 32K block of data. The
Debug data port provides users access to nodes
internal to the CLC5902 DDC. Refer to the DRCS
Evaluation Board User Manual and CLC5902 data
sheet for more detailed information. 

4.

Histogram Debug mode configures the Capture
Board to generate a histogram file using the parallel
data as the source. The hardware requires multiple
clock strobes to increment each SRAM value. Even
though the data used is not a contiguous block, the
probability density information is retained. The
SRAM depth (32K) is used to store the data bin
values; therefore, the histogram generator is limited
to 15-bits of resolution (there are only 32,767 bins).
The values of all 32K bins will be read out of the
SRAM and sent out to the users PC regardless of
the resolution of the data source. The DRCS 

Debug

data will be displayed at the 15-bit resolution limit
(this is also the case for the DRCS 24-bit Serial Out
data) and the histogram will be centered about
16,384 assuming there is no intentional DC offset.
The following figure displays the sine wave histo-

gram data of the DRCS output generated by the
Capture Board at an input frequency of 150MHz and
16dBm in amplitude using all the default DRCS set-
tings. The data source was the DDC serial output
(

Capture Histogram mode was used where

Fsample is 270KHz) and therefore took several
minutes to collect. In this scenario the 24-bit data
source resolution is truncated to the 15-bits (32K) of
available SRAM. The histogram peak target was set
to 16K which required over 16 million data points be
processed for the input level of -2dB below full scale.
The number of data points is proportional to the Max
Target and the amplitude range of the data (the X-
axis). The “Plot Data” menu function of the analysis
tools was used to generate the actual Matlab plot figure.

DRCS Evaluation Setup Sanity Check
The following discussion is to confirm the DRCS
evaluation setup. The example uses a Fourier analysis of
a simple, single tone, sinusoidal IF input to the DRCS. It
is assumed that Setup.exe on the evaluation kit’s
CDROM has installed the necessary files in the user’s
PC and the DRCS and Data Capture hardware is config-
ured as shown in the diagram at the front of 

Section III. It

is also assumed that Matlab (version 5.1 or higher) is
available. Reconfiguration of the DRCS through its Con-
trol Panel software is not required for these two tests. The
DRCS default values contained within the micro-control-
ler with SW2:1-8 = OFF (on DRCS board) will configure
the CLC5902 with the proper values. If the power has
been applied while in another state or if the user has
RESET the micro-controller with a different switch set-
ting, then set the SW2 switches to OFF and press the
RESET button on the DRCS Evaluation board.

** 

Apply an IF input signal to the AIN1 jack on the
DRCS Evaluation board at 150MHz and 0dBm. The
DDC mixer is set to -5.97MHz which brings the
aliased (Fclk ADC = 52MHz; 3rd alias = 156MHz)
signal down to +30KHz. The DDC then filters and
decimates the data and sends it out the serial port
(

AOUT) in the “packed”, “muxed_mode” format. 

SW1; #4

SW1; #5

Histogram
Target Value

0

0

16K

0

1

8K

1

0

4K

1

1

2K

Summary of Contents for CLC-CAPT-PCASM

Page 1: ...s Receiver Transmitter an oscillator and a level translator IC The captured data is stored in either three 32K x 8 static RAMs organized into 24 bit words or in a FIFO containing 32K 18 bit words LEDs provide a visual indication of activity DIP switches and a jumper configure several capture functions Section II Capturing Data from ADC Evaluation Boards Getting Started To use the Data Capture boar...

Page 2: ...on board An amplitude of 10 to 16dBm is recommended Here again the HP 8644B is a good choice Software 1 National Semiconductor Software All of the required software is provided on a CD ROM To install the software now insert the CD ROM into your computer and follow the directions The default installation copies all of the files to a directory called c nsc The data capture software is called capture...

Page 3: ...ion board pin 20B The third jumper block J2 is unused Data Capture Board Block Diagram DIP Switches Five of the eight DIP switches are used to configure several capture functions as follows DIP switch 1 This DIP switch specifies whether a Diversity Receiver Evaluation Board or an ADC Evaluation Board is attached to the Data Capture Board ON ADC Evaluation Board is attached Captured data is aligned...

Page 4: ...he Data Capture Board is powered up and the FPGA is initialized it is on to indicate that the board is ready After all the SRAM data has been output it is off LED 2 This LED is on when captured data is available to be output to the serial port After all the data has been output it is off LED 6 This LED is connected to the clock signal selected by DIP switch 1 When the clock is toggling it will be ...

Page 5: ...you start with the default file name and location shown Click on Default and then on OK If you do not have a C temp directory please make one The reason for this is that the Matlab script files for data analysis look auto matically for the file C temp data dat If you wish to store the data elsewhere you will need to modify the Matlab m files to look for your data file in a different loca tion Obvi...

Page 6: ... configuration menu Select Histogram Debug as shown above and click on OK When the data capture control panel returns you can verify your capture settings by positioning the mouse over the progress bar You will see the following display When you press Start now the SRAM will be cleared and then the board will count the number of times each code is output When any count reaches the number that you ...

Page 7: ... and Capture Board combination require 5V at 1A 4 An IBM Compatible Personal Computer running Windows 95 Windows 98 or Windows NT with a serial port capable of 115 200 baud 5 Serial data cable to connect the data capture board to the PC 6 Low noise filtered IF Signal source for analog input to DRCS 7 OPTIONAL Low jitter clock source 10 16dBm sinewave if DRCS crystal oscillator is removed Software ...

Page 8: ...ion The SRAM is useful for displaying time records of data or collecting contiguous blocks of slower data that have been decimated by the CLC5902 DDC The SRAM is the memory element used for the board s hardwired histogram data generation Capture Board Hardware Configuration Options for DRCS data capture Place the WCLK FIFO write clock jumper in the PIN 120 position the VCORE should be in the 5V po...

Page 9: ...arted Next is a discussion of the Mode functions and the related sub functions MODES There are four primary modes in which to run the data capture system each with its own associated options 1 Capture mode configures the Capture Board for data reception from the DRCS evaluation board Both serial and the parallel output ports can be used as the source data path a The 24 Bits option captures serial ...

Page 10: ...ata source The DRCS Debug data will be displayed at the 15 bit resolution limit this is also the case for the DRCS 24 bit Serial Out data and the histogram will be centered about 16 384 assuming there is no intentional DC offset The following figure displays the sine wave histo gram data of the DRCS output generated by the Capture Board at an input frequency of 150MHz and 16dBm in amplitude using ...

Page 11: ...nditions The main portion of the noise power is contained in the carrier s immediate sidebands 5KHz Another point of interest is that there are several spectral lines about 75dBFS and 25KHz on either side of the fundamental These have been traced to the ground loop created by the PC serial interface Both serial interface cables were connected while this data was being collected Removing the cable ...

Page 12: ...e variable to 0 Setting the Dither variable excludes a lower portion of the spectrum from the FFT analysis and is intended to be used in conjunction with a base band dither signal being present at the ADC analog input 12 bit FFT b12_FFT m is the script intended for data analysis in conjunction with the CLC5956 Evaluation Boards DNL_INL dnl_inl m is the script intended for data analysis of the hist...

Page 13: ...13 http www national com CLC CAPT PCASM Evaluation Board Layer 1 CLC CAPT PCASM Evaluation Board Layer 2 CLC CAPT PCASM Evaluation Board Layer 3 CLC CAPT PCASM Evaluation Board Layer 4 ...

Page 14: ...1 1 1 1 1 6 287 287 287 1 9 9 1 1 1 1 1 1 1 6 6 287 9 9 9 9 5 9 9 9 9 1 4 5 2 2 5 1 57 4 4 9 4 3 3 1 1 5 5 1 2 9 1 4 1 4 602 9 4 1 4 4 4 4 4 4 9 4 4 1 4 4 1 4 56 1 1 1 1 1 865 21 B 21 6 7 7 7 7 7 7 7 7 B B B 1 B 1 B 1 B 1 9B2 1 17 1 17 1 17 1 17 1 17 1 17 1 17 1 17 1 17 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 7B 21 06 06 1 1 2 1 21 1 6 1 9B 5 156 167 786 17567 1 6 1B 1B 1B 1B 1B 1B 1B 1B...

Page 15: ...to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd Japan Ltd 1111 West Bardin Road Fax 49 0 180 530 85 86 13th Floor Straight Block Tel 81 043 299 2309 Arlington TX 76017 E mail europe supp...

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