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Hardware

 

1.  CLC3790093 Data Capture Board 

(CLC-CAPT-PCASM)

2.  CLC Evaluation Board. Several ADC products can

be evaluated with this system. Currently, the choices
are the CLC5956 (12-bit 65MSPS ADC), or the
CLC5958 (14-bit 52MSPS ADC). Each product
has a unique evaluation board (CLC5956PCASM
or CLC5958PCASM) which plugs into the data
capture board. 

3.  Personal Computer. An IBM-Compatible PC running

Windows

 

®

 

 95, Windows

 

®

 

 98, or Windows

 

®

 

 NT. The

PC should have an available serial port capable of
operating at 115,200 baud. These ports are usually
labeled and referred to as COM1 and COM2. The
captured data is stored in a file on the PC to allow
custom analysis.

4. Serial Cable. A standard serial interface cable is

provided. This cable connects the data capture
board to the PC. 

5. Power Supply. The data capture board requires a

5V supply. This power is applied at
connector J3. A 2-amp supply will provide enough
current for the evaluation board and the data cap-
ture board. Note that the power for the evaluation
board is provided from the data capture board
through the 64-pin connector J1. 

6. Input signal. You can provide any type of input

signal that you feel is appropriate to your system
testing. The data analysis software provided with the
data capture board is oriented toward analysis of
single tone sinewave inputs. Our recommendation
for high purity, low phase noise reference signal
sources is the Hewlett Packard HP8644B synthe-
sizer. It provides an excellent input stimulus for
evaluating ADC performance. 

7. Bandpass or lowpass filter. Even with a good

sinewave  source, you will need to filter out the har-
monics of the signal source. A bandpass filter also
enables filtering of the wideband noise of the refer-
ence source. As an example, Allen Avionics
(Mineola, NY) passive filters are used for most of
our converter testing.   

8. Clock Source. If you wish to test the ADC with a fixed

clock frequency, you may install a standard TTL
oscillator in the socket provided on the evaluation
board. Otherwise, you will need to provide a low
phase noise sinewave or square wave clock source
at the appropriate SMA connector on the evaluation
board. An amplitude of 10 to 16dBm is recommended.
Here, again, the HP 8644B is a good choice. 

 

Software

 

1. 

National Semiconductor Software. All of the
required software is provided on a CD-ROM. To
install the software now, insert the CD-ROM into
your computer and follow the directions. The default
installation copies all of the files to a directory called
“c:\nsc”. The data capture software is called
“capture.exe”.  

2. Matlab. A copy of Matlab version 5.1 or later is

required to operate the analysis routines. If you sim-
ply wish to capture data to a file on your PC and pro-
cess the data with your own analysis software, then
you will not need Matlab. For more information
about Matlab, please see their website at http://
www.mathworks.com. 

3.  Matlab script files. The Matlab script files for data

analysis are located in the “c:\nsc\mfiles” directory.
These script files are run from the Matlab command
prompt. 

 

Documentation

 

The CD-ROM includes all of the following documentation,
with the most current versions available on our website at
http:// www.national.com:

1. CLC5956 data sheet

2. CLC5958 data sheet

3. Data Capture Board User’s guide (this document).

Additional information is included on other products and
their evaluation boards. If you are evaluating the
Diversity  Receiver Chip Set, please refer to Section III of
this manual. 

 

Operation of Data Capture Board

 

When evaluating the performance of an ADC, the data
capture board has two main modes of operation. In the
first mode, data is captured from the evaluation board
under test at the full sample rate of the ADC. A contigu-
ous set of 32k data samples is captured into a FIFO
memory on the board, and then this data is moved over
to the PC at a slower rate. The data set is stored in a file
on the hard drive for later analysis. The data is stored in
an ASCII file in exactly the format that it is output from the
converter. For the CLC5956, the two’s complement 12-Bit
data is stored as numbers ranging from 0 to 4095. In the
case of the 14-bit ADC5958, the two’s complement data
ranges from 0 to 16383. Each value is terminated with a
carriage return, hexadecimal 0D. Note that the two’s

BPF

Ain

CLK

VCC

GND

OPTIONAL

CLOCK SOURCE

FILTERED

SIGNAL

SOURCE

+5V

VCC

(2A)

Data

10-16dBm

To PC Serial

COMM PORT #1 or #2

64P I/O

CONNECTOR

Clock

Power

Optional

TTL

Oscillator

ADC

Evaluation

Board

Data

Capture

Board

Serial I/O

Summary of Contents for CLC-CAPT-PCASM

Page 1: ...s Receiver Transmitter an oscillator and a level translator IC The captured data is stored in either three 32K x 8 static RAMs organized into 24 bit words or in a FIFO containing 32K 18 bit words LEDs provide a visual indication of activity DIP switches and a jumper configure several capture functions Section II Capturing Data from ADC Evaluation Boards Getting Started To use the Data Capture boar...

Page 2: ...on board An amplitude of 10 to 16dBm is recommended Here again the HP 8644B is a good choice Software 1 National Semiconductor Software All of the required software is provided on a CD ROM To install the software now insert the CD ROM into your computer and follow the directions The default installation copies all of the files to a directory called c nsc The data capture software is called capture...

Page 3: ...ion board pin 20B The third jumper block J2 is unused Data Capture Board Block Diagram DIP Switches Five of the eight DIP switches are used to configure several capture functions as follows DIP switch 1 This DIP switch specifies whether a Diversity Receiver Evaluation Board or an ADC Evaluation Board is attached to the Data Capture Board ON ADC Evaluation Board is attached Captured data is aligned...

Page 4: ...he Data Capture Board is powered up and the FPGA is initialized it is on to indicate that the board is ready After all the SRAM data has been output it is off LED 2 This LED is on when captured data is available to be output to the serial port After all the data has been output it is off LED 6 This LED is connected to the clock signal selected by DIP switch 1 When the clock is toggling it will be ...

Page 5: ...you start with the default file name and location shown Click on Default and then on OK If you do not have a C temp directory please make one The reason for this is that the Matlab script files for data analysis look auto matically for the file C temp data dat If you wish to store the data elsewhere you will need to modify the Matlab m files to look for your data file in a different loca tion Obvi...

Page 6: ... configuration menu Select Histogram Debug as shown above and click on OK When the data capture control panel returns you can verify your capture settings by positioning the mouse over the progress bar You will see the following display When you press Start now the SRAM will be cleared and then the board will count the number of times each code is output When any count reaches the number that you ...

Page 7: ... and Capture Board combination require 5V at 1A 4 An IBM Compatible Personal Computer running Windows 95 Windows 98 or Windows NT with a serial port capable of 115 200 baud 5 Serial data cable to connect the data capture board to the PC 6 Low noise filtered IF Signal source for analog input to DRCS 7 OPTIONAL Low jitter clock source 10 16dBm sinewave if DRCS crystal oscillator is removed Software ...

Page 8: ...ion The SRAM is useful for displaying time records of data or collecting contiguous blocks of slower data that have been decimated by the CLC5902 DDC The SRAM is the memory element used for the board s hardwired histogram data generation Capture Board Hardware Configuration Options for DRCS data capture Place the WCLK FIFO write clock jumper in the PIN 120 position the VCORE should be in the 5V po...

Page 9: ...arted Next is a discussion of the Mode functions and the related sub functions MODES There are four primary modes in which to run the data capture system each with its own associated options 1 Capture mode configures the Capture Board for data reception from the DRCS evaluation board Both serial and the parallel output ports can be used as the source data path a The 24 Bits option captures serial ...

Page 10: ...ata source The DRCS Debug data will be displayed at the 15 bit resolution limit this is also the case for the DRCS 24 bit Serial Out data and the histogram will be centered about 16 384 assuming there is no intentional DC offset The following figure displays the sine wave histo gram data of the DRCS output generated by the Capture Board at an input frequency of 150MHz and 16dBm in amplitude using ...

Page 11: ...nditions The main portion of the noise power is contained in the carrier s immediate sidebands 5KHz Another point of interest is that there are several spectral lines about 75dBFS and 25KHz on either side of the fundamental These have been traced to the ground loop created by the PC serial interface Both serial interface cables were connected while this data was being collected Removing the cable ...

Page 12: ...e variable to 0 Setting the Dither variable excludes a lower portion of the spectrum from the FFT analysis and is intended to be used in conjunction with a base band dither signal being present at the ADC analog input 12 bit FFT b12_FFT m is the script intended for data analysis in conjunction with the CLC5956 Evaluation Boards DNL_INL dnl_inl m is the script intended for data analysis of the hist...

Page 13: ...13 http www national com CLC CAPT PCASM Evaluation Board Layer 1 CLC CAPT PCASM Evaluation Board Layer 2 CLC CAPT PCASM Evaluation Board Layer 3 CLC CAPT PCASM Evaluation Board Layer 4 ...

Page 14: ...1 1 1 1 1 6 287 287 287 1 9 9 1 1 1 1 1 1 1 6 6 287 9 9 9 9 5 9 9 9 9 1 4 5 2 2 5 1 57 4 4 9 4 3 3 1 1 5 5 1 2 9 1 4 1 4 602 9 4 1 4 4 4 4 4 4 9 4 4 1 4 4 1 4 56 1 1 1 1 1 865 21 B 21 6 7 7 7 7 7 7 7 7 B B B 1 B 1 B 1 B 1 9B2 1 17 1 17 1 17 1 17 1 17 1 17 1 17 1 17 1 17 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 7B 21 06 06 1 1 2 1 21 1 6 1 9B 5 156 167 786 17567 1 6 1B 1B 1B 1B 1B 1B 1B 1B...

Page 15: ...to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd Japan Ltd 1111 West Bardin Road Fax 49 0 180 530 85 86 13th Floor Straight Block Tel 81 043 299 2309 Arlington TX 76017 E mail europe supp...

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